5M240ZT100C5N - 240 Logic Element MAX V CPLD, 100TQFP | Intel / Altera
MPN: 5M240ZT100C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.1613 | $8.16 |
| 10 | $7.5 | $75.00 |
| 100 | $6.4 | $640.00 |
| 500 | $5.6 | $2,800.00 |
| 1,000 | $4.9816 | $4,981.60 |
Drop-in alternatives for 5M240ZT100C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
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View Datasheet β5M240ZT100C5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Logic Elements (LEs) | 240 |
| Macrocells | 192 |
| User I/Os | 79 |
| User Flash Memory | 8 Kbits |
| Maximum Internal Frequency | 118.3 MHz |
| Pin-to-Pin Logic Delay (Tpd1) | 7.5 ns (per distributor classification) |
| Operating Voltage (VCCINT) | 3.3 V (internal 1.8 V core derived) |
| I/O Bank Voltages Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| Configuration Memory | Internal flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) |
| Package | TQFP-100 (14 x 14 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (commercial grade) |
| RoHS Status | Compliant (per LCSC listing) |
5M240ZT100C5N Pin Configuration
| Pin 1 | I/O β User I/O (Bank 1) / per MAX V pinout table |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | I/O β User I/O (Bank 1) |
| Pin 7 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 8 | I/O β User I/O (Bank 1) |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O (Bank 2) |
| Pin 12 | I/O β User I/O (Bank 2) |
| Pin 13 | I/O β User I/O (Bank 2) |
| Pin 14 | I/O β User I/O (Bank 2) |
| Pin 15 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 16 | I/O β User I/O (Bank 2) |
| Pin 17 | I/O β User I/O (Bank 2) |
| Pin 18 | I/O β User I/O (Bank 2) |
| Pin 19 | I/O β User I/O (Bank 2) |
| Pin 20 | I/O β User I/O (Bank 2) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (Bank 2) |
| Pin 23 | I/O β User I/O (Bank 2) |
| Pin 24 | I/O β User I/O (Bank 2) |
| Pin 25 | I/O β User I/O (Bank 2) |
| Pin 26 | VCCINT β Core supply voltage (3.3V) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | I/O β User I/O (Bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | TDI β JTAG Test Data In |
| Pin 32 | TMS β JTAG Test Mode Select |
| Pin 33 | TCK β JTAG Test Clock |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | I/O β User I/O (Bank 2) |
| Pin 37 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 38 | I/O β User I/O (Bank 2) |
| Pin 39 | I/O β User I/O (Bank 2) |
| Pin 40 | I/O β User I/O (Bank 2) |
| Pin 41 | I/O β User I/O (Bank 2) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O (Bank 3) |
| Pin 44 | I/O β User I/O (Bank 3) |
| Pin 45 | I/O β User I/O (Bank 3) |
| Pin 46 | I/O β User I/O (Bank 3) |
| Pin 47 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 48 | I/O β User I/O (Bank 3) |
| Pin 49 | I/O β User I/O (Bank 3) |
| Pin 50 | I/O β User I/O (Bank 3) |
| Pin 51 | I/O β User I/O (Bank 3) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | I/O β User I/O (Bank 3) |
| Pin 55 | I/O β User I/O (Bank 3) |
| Pin 56 | I/O β User I/O (Bank 3) |
| Pin 57 | VCCINT β Core supply voltage (3.3V) |
| Pin 58 | I/O β User I/O (Bank 3) |
| Pin 59 | I/O β User I/O (Bank 3) |
| Pin 60 | I/O β User I/O (Bank 3) |
| Pin 61 | I/O β User I/O (Bank 3) |
| Pin 62 | GND β Ground |
| Pin 63 | TDO β JTAG Test Data Out |
| Pin 64 | I/O β User I/O (Bank 3) |
| Pin 65 | I/O β User I/O (Bank 3) |
| Pin 66 | I/O β User I/O (Bank 3) |
| Pin 67 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 68 | I/O β User I/O (Bank 3) |
| Pin 69 | I/O β User I/O (Bank 3) |
| Pin 70 | I/O β User I/O (Bank 3) |
| Pin 71 | I/O β User I/O (Bank 4) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O (Bank 4) |
| Pin 74 | I/O β User I/O (Bank 4) |
| Pin 75 | I/O β User I/O (Bank 4) |
| Pin 76 | I/O β User I/O (Bank 4) |
| Pin 77 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 78 | I/O β User I/O (Bank 4) |
| Pin 79 | I/O β User I/O (Bank 4) |
| Pin 80 | I/O β User I/O (Bank 4) |
| Pin 81 | I/O β User I/O (Bank 4) |
| Pin 82 | GND β Ground |
| Pin 83 | I/O β User I/O (Bank 4) |
| Pin 84 | I/O β User I/O (Bank 4) |
| Pin 85 | I/O β User I/O (Bank 4) |
| Pin 86 | I/O β User I/O (Bank 4) |
| Pin 87 | VCCINT β Core supply voltage (3.3V) |
| Pin 88 | I/O β User I/O (Bank 4) |
| Pin 89 | I/O β User I/O (Bank 4) |
| Pin 90 | I/O β User I/O (Bank 4) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O (Bank 4) |
| Pin 93 | I/O β User I/O (Bank 1) |
| Pin 94 | I/O β User I/O (Bank 1) |
| Pin 95 | I/O β User I/O (Bank 1) |
| Pin 96 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 97 | I/O β User I/O (Bank 1) |
| Pin 98 | I/O β User I/O (Bank 1) |
| Pin 99 | I/O β User I/O (Bank 1) |
| Pin 100 | I/O β User I/O (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M240ZT100C5N is suitable for 6 applications: I/O Expansion and Voltage Translation, Power Sequencing in Multi-Rail Systems, Bus Interface Bridging, LED Display and Lighting Control, Industrial Control and Glue Logic Replacement, Consumer Electronics and Set-Top Box Logic.
I/O Expansion and Voltage Translation
The 5M240ZT100C5N's 79 user I/Os distributed across 4 MultiVolt banks (1.5V / 1.8V / 2.5V / 3.3V LVCMOS) make it ideal for expanding microcontroller GPIO and translating between mismatched voltage domains without external level shifters. With 240 logic elements it can implement 8-16 bits of bidirectional translation plus handshake logic on a single device, and the flash-based non-volatile configuration provides instant-on operation at power-up - critical for industrial controllers that must respond within microseconds of supply rail stabilization. Instant-on behavior is unavailable on SRAM-based FPGAs without external boot memory.
Recommended
Power Sequencing in Multi-Rail Systems
The 5M240ZT100C5N excels at power-up and power-down sequencing for complex multi-rail boards (FPGA + DDR + serdes + analog). Its instant-on flash configuration brings the device out of reset in <1 ms and the 240 LEs comfortably implement state machines that control 4-8 enable signals with programmable delays. The 1.8V internal core derived from 3.3V VCCINT simplifies the supply tree, and the commercial 0-85C temperature grade suits most indoor industrial enclosures. Pair with an external supervisor or PMIC for fault-aware sequencing.
Recommended
Bus Interface Bridging
The 5M240ZT100C5N bridges incompatible processor buses such as SPI-to-parallel, I2C-to-GPIO, UART-to-parallel, and legacy 8-bit MCU buses to modern 16/32-bit peripherals. Its 118.3 MHz internal frequency comfortably handles 50 MHz SPI peripherals and even modest parallel-burst interfaces. The on-chip 8 Kbits of user flash can store configuration constants, and JTAG-based in-system programmability lets engineers iterate bus timing in-circuit. This application commonly replaces 2-4 discrete 74-series glue-logic ICs and the associated board area.
Recommended
LED Display and Lighting Control
The 5M240ZT100C5N drives LED matrices, seven-segment displays, and addressable LED strings (WS281x, APA102) by generating precise multi-channel PWM waveforms with sub-microsecond dead-time control. Its 79 user I/Os can refresh up to 16 multiplexed 7-segment digits or drive ~80 discrete LEDs directly with current-limited drivers. Compared to microcontrollers, the CPLD delivers deterministic timing independent of interrupt latency, eliminating visible flicker in high-refresh-rate LED panels. The instant-on flash configuration also lights displays immediately at power-up.
Recommended
Industrial Control and Glue Logic Replacement
The 5M240ZT100C5N replaces clusters of 74HC/74AHC glue logic on industrial PLC I/O boards, motor-control front-ends, and sensor interface cards. The 240-LE capacity typically absorbs 5-15 discrete logic ICs, reducing PCB area, BOM count, and supply-chain risk. Its MultiVolt I/O banks interface directly to 1.8V sensors, 3.3V MCUs, and 5V industrial transceivers within one chip. The commercial 0-85C grade suits factory-floor enclosures with adequate thermal design; for harsher environments use the I-temp 5M240ZT100I5N variant.
Recommended
Consumer Electronics and Set-Top Box Logic
The 5M240ZT100C5N provides HDMI level shifters, IR receiver decoding, keypad scanning, and standby power management in set-top boxes, smart-TVs, and home audio products. Its instant-on flash configuration enables sub-100 ms remote-control responsiveness, and the 4 MultiVolt I/O banks connect 1.8V SoC, 3.3V peripherals, and 5V legacy interfaces in a single device. The TQFP-100 14x14 mm package with 0.5 mm pitch is hand-solderable for prototypes and supports standard SMT reflow for volume manufacturing.
Recommended
Recommended Products Summary
Engineering reference data for 5M240ZT100C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M240ZT100C4N | 5M240ZT100I5N | 5M240ZT100A5N | 5M240ZM100C5N | 5M160ZT100C5N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements | 240 | 240 | 240 | 240 | 240 | 160 |
| Speed Grade | C5 (7.5 ns Tpd1) | C4 (slower Tpd1) | I5 (industrial temp, 7.5 ns Tpd1) | A5 (extended temp) | C5 (M100 variant) | C5 (smaller density) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | -40C to +100C (industrial) | Extended (automotive/industrial) | 0C to +85C | 0C to +85C |
| User I/Os | 79 | 79 | 79 | 79 | [DATA_NEEDED: exact I/O count for M100 variant] | 79 |
| Configuration Memory | Internal flash (non-volatile) | Internal flash | Internal flash | Internal flash | Internal flash | Internal flash |
| Unit Price (qty 1, as of 2026-09-06) | ~$8.16 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Same-density, faster speed grade within same family (vs 5M240ZT100C4N)
- Industrial temperature grade option in same footprint (vs 5M240ZT100I5N)
- Higher density than 160-LE predecessor in same package (vs 5M160ZT100C5N)
Design Notes
The MAX V device family integrates an on-chip voltage regulator that derives the internal 1.8V core from the external 3.3V VCCINT supply rail, so the user only needs to provide a single 3.3V rail for the core. Each I/O bank has its own VCCIO pin that can be independently powered at 1.5V, 1.8V, 2.5V, or 3.3V to interface with mixed-voltage peripherals. Decoupling recommendation: place one 0.1uF ceramic capacitor as close as possible to every VCCINT and VCCIO pin, plus a bulk 10uF tantalum or ceramic capacitor on the 3.3V supply plane to suppress switching transients during in-system programming via JTAG.
Route the JTAG signals (TCK, TMS, TDI, TDO) as a daisy-chain with 10K pull-ups on TCK/TMS/TDI to VCCIO of their bank, and place the JTAG header within 50 mm of the device to keep programming reliable. For high-speed designs targeting >50 MHz, route clock signals on inner PCB layers with continuous ground reference, keep I/O traces under 25 mm to minimize reflections, and provide a solid ground plane under the TQFP-100 footprint for thermal dissipation (typical standby power is <100 mW but dynamic current can rise to 200-300 mA during simultaneous-switching events).
Do not assume the EPM240T100I5N (MAX II) is a 100% drop-in for the 5M240ZT100C5N (MAX V): per the Altera community forum, pin 1 is reassigned (GND on MAX II vs I/O on MAX V) and the core voltage scheme differs (3.3V on MAX II vs 1.8V-derived on MAX V). Always verify pin 1 routing and confirm Quartus software version supports your device (Quartus II 13.0sp1 or Quartus Prime 18.1+ recommended for MAX V). When migrating from MAX II to MAX V, recompile the design rather than reusing the .pof file directly, as the bitstream formats differ.
Compliance Information
RoHS compliance confirmed via LCSC listing; REACH / halogen-free / conflict-mineral status not explicitly stated in verified distributor data. For automotive applications, select the 'A' suffix variant (5M240ZT100A5N) which is AEC-Q100 qualified per the MAX V family datasheet.
