EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
MPN: EP1S20F672I7 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 250 | $213.75 | $53,437.50 |
| 500 | $199.5 | $99,750.00 |
Drop-in alternatives for EP1S20F672I7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1S20F672I7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$198 / Unit
View Datasheet →EP1S20F672C7N
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View Datasheet →EP1S20F672C7
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View Datasheet →EP1S20F672C6N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →EP1S20F672C6
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$470 / Unit
View Datasheet →EP1S20B672C7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$320 / Unit
View Datasheet →EP1S20B672C6N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$425 / Unit
View Datasheet →EP1S20F672I7 Maximum Ratings & Electrical Characteristics
| Family | Stratix (first generation) |
| Logic Elements (LEs) | 18,460 |
| Maximum RAM Bits | 1,669,248 |
| Maximum User I/Os | 426 |
| Supply Voltage (VCCINT core) | 1.5 V |
| Logic Family | CMOS |
| Package | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Operating Temperature | -40C to +85C (industrial grade, I7 suffix) |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG |
| Number of Pins / Balls | 672 |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | unknown |
| Lead-Free / Finish | SnPb (e0 per Partstack datasheet extract) |
| MSL Level | unknown |
| Status | Last Time Buy (per distributor notices) |
EP1S20F672I7 672-bbga (fineline bga), 35 x 35 mm, 1.27 mm pitch Pin Configuration Guide
Complete pinout information for EP1S20F672I7 (672-bbga (fineline bga), 35 x 35 mm, 1.27 mm pitch package) with 672 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1S20F672I7.
Refer to the datasheet for full pin configuration.
Estimated pin count: 672 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1S20F672I7 is suitable for 6 applications: Telecommunications Base-Station Channel Cards, ASIC Prototyping and Emulation, Military and Aerospace Signal Processing, High-Speed Protocol Bridging, Video and Image Processing Pipelines, Industrial Test and Measurement.
Telecommunications Base-Station Channel Cards
The EP1S20F672I7 is well suited to 3G/4G base-station channel cards where its 18,460 LEs and 1,669,248 bits of TriMatrix memory enable parallel implementation of chip-rate processing, scrambling, channel coding, and modulation. The 426 user I/Os accommodate multiple antenna paths and backhaul interfaces. Per the Stratix handbook, the device's high-speed LVDS pairs support SPI-4.2, SFI-4, and XAUI PHY interconnect. The industrial -40C to +85C grade matches outdoor cabinet and thermally-challenged enclosure environments common in telecom infrastructure.
Recommended
ASIC Prototyping and Emulation
The EP1S20F672I7's mid-density 18,460-LE fabric, 672-ball BGA, and Quartus II toolchain support make it a common target for ASIC register-transfer-level (RTL) prototyping. Designers partition large ASICs across multiple Stratix devices using TDM pin multiplexing, validating functional correctness, software/firmware interaction, and timing closure before committing to silicon. Per Intel/Altera application notes, multiple EP1S20F672I7 devices can be time-multiplexed on a single PCB to emulate ASICs up to several million gates, dramatically reducing pre-silicon design risk.
Recommended
Military and Aerospace Signal Processing
The EP1S20F672I7's industrial -40C to +85C operating range, high DSP block count, and abundant LVDS I/O make it suitable for radar signal processing, electronic warfare, and software-defined radio platforms. The wide TriMatrix memory provides fast data-path buffering between antenna samples and DSP pipelines, while the 1.5 V core delivers predictable power consumption for airborne and shipboard power budgets. Per the Stratix handbook, the device's radiation-tolerant characteristics have been used in satellite payload processing with appropriate derating.
Recommended
High-Speed Protocol Bridging
The EP1S20F672I7 integrates 426 user I/Os with LVDS support up to 840 Mbps per channel (per the Stratix handbook), enabling high-speed bridging between legacy parallel interfaces (UTOPIA, POS-PHY, SPI-4.2) and newer serial protocols. The dedicated PLLs handle multi-clock-domain bridging, while TriMatrix memory implements elastic buffers to absorb rate mismatches. The 672-ball BGA provides sufficient signal integrity for parallel buses up to 64 bits wide at 200 MHz DDR. This makes the EP1S20F672I7 a popular choice for storage area network (SAN) routers and SONET/SDH muxponder designs.
Recommended
Video and Image Processing Pipelines
Broadcast and medical imaging systems leverage the EP1S20F672I7's 18,460 LEs and DSP blocks to implement real-time video processing pipelines, including de-interlacing, scaling, color-space conversion, and motion compensation. The TriMatrix memory holds several lines of video for block-level operations, while the 426 user I/Os accept parallel video buses (BT.1120, BT.656, DVI/HDMI bridges). Per Intel application notes, the Stratix DSP blocks can also accelerate JPEG/JPEG2000 and H.264 codec functions. The industrial temperature grade supports medical imaging carts and outdoor broadcast vehicles.
Recommended
Industrial Test and Measurement
Automated test equipment (ATE) and laboratory instrumentation use the EP1S20F672I7 for pattern generation, signal capture, and protocol-aware triggering. The FPGA's parallel logic fabric generates stimulus waveforms at rates exceeding discrete processor capabilities, while the TriMatrix memory buffers captured samples for downstream analysis. Per the Stratix handbook, the 1.5 V core and configurable I/O standards (LVTTL, LVCMOS, SSTL, HSTL) allow direct interface to virtually any digital logic family. The industrial temperature range supports factory-floor and outdoor test installations.
Recommended
Recommended Products Summary
Engineering reference data for EP1S20F672I7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1S20F672I7N | EP1S20F672C7N | EP1S20F672C7 | EP1S20F672C6N | EP1S20F672C6 | EP1S20B672C7N | EP1S20B672C6N |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA (FineLine BGA), 35x35 mm, 1.27 mm pitch | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 (B variant) | 18,460 (B variant) |
| RAM Bits | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 (B variant) | 1,669,248 (B variant) |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | -7 | -7 | -7 | -7 | -6 | -6 | -7 (B variant) | -6 (B variant) |
| Lead-Free / Finish | SnPb (e0) | Lead-free (N suffix) | Lead-free (N suffix) | SnPb (e0) | Lead-free (N suffix) | SnPb (e0) | Lead-free (N suffix) | Lead-free (N suffix) |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Industrial temperature grade (-40C to +85C) (vs EP1S20F672C7)
- Same-package drop-in replacement within Intel Stratix family (vs EP1S20F672C7N)
- Higher performance tier than B-variant Stratix devices (vs EP1S20B672C7N)
Design Notes
The EP1S20F672I7 requires four separate power rails: VCCINT (1.5 V core), VCCIO (1.5 V/1.8 V/2.5 V/3.3 V selectable per bank), VCCA (1.5 V analog supply for PLLs), and VCCD_PLL (digital PLL supply). Per the Stratix handbook, all rails must ramp monotonically and reach within 5% of nominal within 100 ms to avoid inrush damage. Decoupling recommendations: 100 uF bulk + 10 uF + 1 uF + 0.1 uF per rail with the smallest caps placed closest to the balls. Estimated: at 80% utilization and 200 MHz operation, expect 4-6 W core power plus 0.5-1.5 W IO power.
The 672-ball FineLine BGA on 1.27 mm pitch requires 6+ layer PCB stack-up with microvia or via-in-pad technology for breakout. Per Altera AN 315 (BGA design guidelines), maintain a continuous reference plane under the BGA, escape on inner layers through microvias, and stitch GND vias around the perimeter for return path integrity. Use differential pair routing with 100 ohm differential impedance for LVDS signals and 50 ohm single-ended for general-purpose I/O. A 4-layer stack-up is feasible but constrains routing density significantly.
Estimated: Quoting the Quartus II compilation report for IO timing is essential because Speed Grade -7 is approximately 15% faster than -6 but only 5-7% faster than -8. The Stratix handbook recommends running Slow 1100 mV 85C model for industrial-grade timing closure and Slow 1100 mV 0C for commercial. A common pitfall is using the wrong temperature corner: for industrial-grade parts, designs must close timing over the full -40C to +85C range. Also note that BGA rework without proper reflow profile can damage the FineLine substrate - use pre-qualified profiles per J-STD-020.
Compliance Information
Per Partstack and DigChip datasheet extracts, the EP1S20F672I7 base part uses SnPb finish (JESD-609 e0). Lead-free (RoHS-compliant) variants carry the 'N' suffix, e.g. EP1S20F672I7N. AEC-Q100 not applicable (FPGA, not an automotive-grade IC in the AEC sense).
