EPM570GT144C4 - 570 LEs, 5.4ns CPLD, 144-TQFP | Intel MAX II
MPN: EPM570GT144C4 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.21 | $36.21 |
| 10 | $32.58 | $325.80 |
| 100 | $28.95 | $2,895.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $22.1 | $22,100.00 |
Drop-in alternatives for EPM570GT144C4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570GT144C3
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View Datasheet →EPM570GT144C3N
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View Datasheet →EPM570GT144C4N
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View Datasheet →EPM570GT100C5N
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View Datasheet →EPM570GT100C4N
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View Datasheet →EPM570GF256C4N
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View Datasheet →EPM570GT144C4 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements | 570 |
| Equivalent Macrocells | 440 |
| Internal User Flash Memory | 8 Kbits |
| Pin-to-Pin Delay (tPD) | 5.4 ns (max) |
| Maximum Frequency | 247.5 MHz |
| Process Technology | 0.18 µm, 6-layer-metal flash |
| Core Voltage | 1.8 V |
| I/O Standards | LVCMOS / LVTTL 1.5/1.8/2.5/3.3/5 V (MultiVolt) |
| Number of Pins | 144 |
| Package | TQFP-144 (GT) |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| JTAG Support | IEEE 1149.1 / IEEE 1532 ISP |
| Configuration Memory | Non-volatile flash, instant-on |
| RoHS Status | Compliant |
EPM570GT144C4 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | GND — Ground |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3/5 V) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | GND — Ground |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | I/O — User I/O pin (bank 1) |
| Pin 22 | I/O — User I/O pin (bank 1) |
| Pin 23 | VCCINT — Core supply voltage (1.8 V) |
| Pin 24 | I/O — User I/O pin (bank 1) |
| Pin 25 | I/O — User I/O pin (bank 1) |
| Pin 26 | I/O — User I/O pin (bank 1) |
| Pin 27 | I/O — User I/O pin (bank 1) |
| Pin 28 | I/O — User I/O pin (bank 1) |
| Pin 29 | I/O — User I/O pin (bank 1) |
| Pin 30 | I/O — User I/O pin (bank 1) |
| Pin 31 | I/O — User I/O pin (bank 1) |
| Pin 32 | I/O — User I/O pin (bank 1) |
| Pin 33 | I/O — User I/O pin (bank 1) |
| Pin 34 | I/O — User I/O pin (bank 1) |
| Pin 35 | I/O — User I/O pin (bank 1) |
| Pin 36 | I/O — User I/O pin (bank 1) |
| Pin 37 | I/O — User I/O pin (bank 1) |
| Pin 38 | I/O — User I/O pin (bank 1) |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — User I/O pin (bank 1) |
| Pin 41 | I/O — User I/O pin (bank 1) |
| Pin 42 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 43 | I/O — User I/O pin (bank 2) |
| Pin 44 | I/O — User I/O pin (bank 2) |
| Pin 45 | I/O — User I/O pin (bank 2) |
| Pin 46 | I/O — User I/O pin (bank 2) |
| Pin 47 | I/O — User I/O pin (bank 2) |
| Pin 48 | I/O — User I/O pin (bank 2) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O pin (bank 2) |
| Pin 51 | I/O — User I/O pin (bank 2) |
| Pin 52 | I/O — User I/O pin (bank 2) |
| Pin 53 | I/O — User I/O pin (bank 2) |
| Pin 54 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 55 | I/O — User I/O pin (bank 2) |
| Pin 56 | I/O — User I/O pin (bank 2) |
| Pin 57 | I/O — User I/O pin (bank 2) |
| Pin 58 | I/O — User I/O pin (bank 2) |
| Pin 59 | GND — Ground |
| Pin 60 | I/O — User I/O pin (bank 2) |
| Pin 61 | I/O — User I/O pin (bank 2) |
| Pin 62 | I/O — User I/O pin (bank 2) |
| Pin 63 | VCCINT — Core supply voltage (1.8 V) |
| Pin 64 | I/O — User I/O pin (bank 2) |
| Pin 65 | I/O — User I/O pin (bank 2) |
| Pin 66 | I/O — User I/O pin (bank 2) |
| Pin 67 | I/O — User I/O pin (bank 2) |
| Pin 68 | I/O — User I/O pin (bank 2) |
| Pin 69 | I/O — User I/O pin (bank 2) |
| Pin 70 | I/O — User I/O pin (bank 2) |
| Pin 71 | I/O — User I/O pin (bank 2) |
| Pin 72 | I/O — User I/O pin (bank 2) |
| Pin 73 | I/O — User I/O pin (bank 3) |
| Pin 74 | I/O — User I/O pin (bank 3) |
| Pin 75 | I/O — User I/O pin (bank 3) |
| Pin 76 | I/O — User I/O pin (bank 3) |
| Pin 77 | I/O — User I/O pin (bank 3) |
| Pin 78 | I/O — User I/O pin (bank 3) |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — User I/O pin (bank 3) |
| Pin 81 | I/O — User I/O pin (bank 3) |
| Pin 82 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 83 | I/O — User I/O pin (bank 3) |
| Pin 84 | I/O — User I/O pin (bank 3) |
| Pin 85 | I/O — User I/O pin (bank 3) |
| Pin 86 | I/O — User I/O pin (bank 3) |
| Pin 87 | I/O — User I/O pin (bank 3) |
| Pin 88 | I/O — User I/O pin (bank 3) |
| Pin 89 | GND — Ground |
| Pin 90 | I/O — User I/O pin (bank 3) |
| Pin 91 | I/O — User I/O pin (bank 3) |
| Pin 92 | I/O — User I/O pin (bank 3) |
| Pin 93 | I/O — User I/O pin (bank 3) |
| Pin 94 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 95 | I/O — User I/O pin (bank 3) |
| Pin 96 | I/O — User I/O pin (bank 3) |
| Pin 97 | I/O — User I/O pin (bank 3) |
| Pin 98 | I/O — User I/O pin (bank 3) |
| Pin 99 | GND — Ground |
| Pin 100 | I/O — User I/O pin (bank 3) |
| Pin 101 | I/O — User I/O pin (bank 4) |
| Pin 102 | I/O — User I/O pin (bank 4) |
| Pin 103 | VCCINT — Core supply voltage (1.8 V) |
| Pin 104 | I/O — User I/O pin (bank 4) |
| Pin 105 | I/O — User I/O pin (bank 4) |
| Pin 106 | I/O — User I/O pin (bank 4) |
| Pin 107 | I/O — User I/O pin (bank 4) |
| Pin 108 | I/O — User I/O pin (bank 4) |
| Pin 109 | I/O — User I/O pin (bank 4) |
| Pin 110 | I/O — User I/O pin (bank 4) |
| Pin 111 | I/O — User I/O pin (bank 4) |
| Pin 112 | I/O — User I/O pin (bank 4) |
| Pin 113 | I/O — User I/O pin (bank 4) |
| Pin 114 | I/O — User I/O pin (bank 4) |
| Pin 115 | I/O — User I/O pin (bank 4) |
| Pin 116 | I/O — User I/O pin (bank 4) |
| Pin 117 | I/O — User I/O pin (bank 4) |
| Pin 118 | I/O — User I/O pin (bank 4) |
| Pin 119 | GND — Ground |
| Pin 120 | I/O — User I/O pin (bank 4) |
| Pin 121 | I/O — User I/O pin (bank 4) |
| Pin 122 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 123 | I/O — User I/O pin (bank 4) |
| Pin 124 | I/O — User I/O pin (bank 4) |
| Pin 125 | I/O — User I/O pin (bank 4) |
| Pin 126 | I/O — User I/O pin (bank 4) |
| Pin 127 | I/O — User I/O pin (bank 4) |
| Pin 128 | I/O — User I/O pin (bank 4) |
| Pin 129 | GND — Ground |
| Pin 130 | I/O — User I/O pin (bank 4) |
| Pin 131 | I/O — User I/O pin (bank 4) |
| Pin 132 | I/O — User I/O pin (bank 4) |
| Pin 133 | I/O — User I/O pin (bank 4) |
| Pin 134 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 135 | I/O — User I/O pin (bank 4) |
| Pin 136 | I/O — User I/O pin (bank 4) |
| Pin 137 | I/O — User I/O pin (bank 4) |
| Pin 138 | I/O — User I/O pin (bank 4) |
| Pin 139 | GND — Ground |
| Pin 140 | I/O — User I/O pin (bank 4) |
| Pin 141 | I/O — User I/O pin (bank 4) |
| Pin 142 | I/O — User I/O pin (bank 4) |
| Pin 143 | VCCINT — Core supply voltage (1.8 V) |
| Pin 144 | I/O — User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT144C4 is suitable for 6 applications: Industrial I/O Expansion and Bus Bridging, Power-Sequencing Logic in Telecom Line Cards, Address Decoding in Legacy Microprocessor Systems, High-Speed Glue Logic in Consumer Devices, Re-Programmable Alternative to Discrete 74-Series Logic, Test & Measurement Front-End Multiplexing.
Industrial I/O Expansion and Bus Bridging
The EPM570GT144C4 fits industrial I/O expansion because its 570 logic elements comfortably decode address buses, generate chip selects, and bridge between legacy parallel interfaces (e.g., 8051, 68k) and modern peripherals, while the 5.4 ns tPD keeps handshake latency well below typical bus cycle times. The 144-pin TQFP footprint exposes up to 116 user I/O pins, enough for 32-bit address/data muxing plus several control flags. Non-volatile instant-on configuration means the controller boots into a defined state within microseconds, eliminating the wait-for-FPGA handshake common in SRAM-based designs. Recommended companion parts include logic-level shifters and 3.3 V LDO regulators for VCCINT generation.
Recommended
Power-Sequencing Logic in Telecom Line Cards
The EPM570GT144C4 is well-suited for telecom line-card power sequencing because its MultiVolt I/O can directly interface 5 V, 3.3 V, and 1.8 V rails without external level shifters, and its 8 Kbit user Flash block can store rail configuration profiles in-system. With up to 116 user I/O and 5.4 ns combinational delay, the device can sequence 12-16 power rails with precise enable timing, monitor PGOOD flags, and latch fault conditions for the host processor to read. The commercial temperature grade (C4) fits temperature-controlled central-office environments. Recommended companion parts include hot-swap controllers and supervisors.
Recommended
Address Decoding in Legacy Microprocessor Systems
The EPM570GT144C4 excels at legacy microprocessor address decoding because its 570 logic elements can simultaneously decode 32-bit address spaces, generate individual chip selects for up to a dozen peripherals, and remap memory windows through user Flash-stored configuration. The 5.4 ns tPD is fast enough to decode one address cycle within a 50 MHz 68k or VME bus, while the 144-pin TQFP exposes enough I/O for full address and data bus bridging. Non-volatile instant-on configuration means boot ROMs and DMA channels are addressable at power-up without delays. Recommended companion parts are SRAMs, FIFOs, and bus transceivers.
Recommended
High-Speed Glue Logic in Consumer Devices
The EPM570GT144C4 serves consumer glue-logic duties because its 0.18 µm flash process delivers a sub-6 ns pin-to-pin delay at low power, and the 144-pin TQFP integrates the equivalent of dozens of 74-series logic chips into one instant-on, in-system-programmable device. Consumer applications include HDMI/DisplayPort muxing logic, LED matrix scanning, and front-panel keyscan controllers where non-volatile configuration preserves custom behavior across power cycles. The 1.8 V core and MultiVolt I/O directly support modern SoC voltage rails without external translators. Recommended companion parts are HDMI muxes and LED drivers.
Recommended
Re-Programmable Alternative to Discrete 74-Series Logic
The EPM570GT144C4 replaces dozens of discrete 74HC/74AHC logic chips because each logic element is a 4-input LUT that can implement any Boolean function, and the user Flash block can hold revision history for field upgrades. Designers typically use this in prototype-to-production transitions to compress 20-50 discrete packages into one CPLD, reducing PCB area, BOM count, and assembly cost. The 5.4 ns tPD approximates 74HC speed, so timing closure is straightforward. JTAG-based ISP allows last-minute bug fixes on the manufacturing line without re-spinning the board. Recommended companion parts include level shifters and bus switches.
Recommended
Test & Measurement Front-End Multiplexing
The EPM570GT144C4 is a good fit for test-and-measurement front-end multiplexing because its 116 user I/O can route dozens of analog/digital test points through one reconfigurable matrix, and JTAG-based ISP allows test-program updates without opening the instrument chassis. The 5.4 ns tPD supports real-time signal switching up to 100 MHz, sufficient for general-purpose bench instruments. Non-volatile instant-on configuration means the instrument is ready at power-up without firmware boot delays, and the 8 Kbit user Flash can store calibration constants alongside the bitstream. Recommended companion parts are analog muxes and instrumentation amplifiers.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT144C4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT144C3 | EPM570GT144C4N | EPM570GT100C5N | EPM570GF256C4N |
|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-100 - different | FBGA-256 - different |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Logic Elements | 570 | 570 | 570 | 570 | 570 |
| Speed Grade (tPD) | 5.4 ns (C4) | ~4.5 ns (C3, faster) | 5.4 ns (C4, same) | ~6.5 ns (C5, slower) | 5.4 ns (C4, same) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Internal User Flash | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Lead-Free / RoHS | May require 'N' suffix for RoHS | May require 'N' suffix | Yes (RoHS) | Yes (RoHS) | Yes (RoHS) |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
Key Differentiators
- Instant-on non-volatile configuration (vs SRAM-based FPGAs (e.g., Cyclone))
- Same-package vertical migration across MAX II family (vs EPM1270GT144, EPM2210GT144)
- MultiVolt I/O supports 1.5 V to 5 V interfaces (vs Discrete 74HC logic)
Design Notes
The EPM570GT144C4 requires a 1.8 V VCCINT core supply and one or more VCCIO bank supplies (1.5/1.8/2.5/3.3/5 V) that must come up simultaneously with VCCINT to avoid JTAG programming failures. Use a dedicated 1.8 V LDO with at least 200 mA headroom for the core, and decouple each VCCINT/VCCIO pin with a 0.1 µF ceramic capacitor placed within 5 mm of the pin. Power sequencing is permissive but must satisfy tRAMP < 100 ms per the MAX II handbook.
Route the JTAG signals (TCK, TMS, TDI, TDO) as a daisy chain with no stubs, keep trace lengths under 100 mm, and place 10 kΩ pull-ups on TCK and TMS per IEEE 1149.1. The four I/O banks (VCCIO1-VCCIO4) are split across all four sides of the package, so place I/O voltage decoupling capacitors near each bank's VCCIO pins. Reserve a GND plane on layer 2 beneath the TQFP-144 footprint to provide a low-impedance return path for high-speed switching outputs.
Do not leave unused I/O pins floating - configure them as outputs driving ground in Quartus II, or as inputs with internal pull-ups enabled. Floating inputs can draw excessive ICCINT current and cause JTAG IDCODE read failures. When migrating from EPM570GT144C4 to EPM570GT144C3, recalculate timing closure since the C3 speed grade is ~17% faster and may change hold-time margins on registered paths.
Compliance Information
RoHS and lead-free per Altera/Intel MAX II product page; choose C4N suffix variants for explicit RoHS marking. Not AEC-Q100 qualified - MAX II is not offered in automotive grades; for AEC-Q100 qualified programmable logic, use Altera/Intel MAX 10 or Cyclone families instead.
