EPM570ZM144C7N - 570 LEs MAX II CPLD, 144-MBGA, 7ns | Intel
MPN: EPM570ZM144C7N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $25.55 | $25.55 |
| 10 | $22.85 | $228.50 |
| 100 | $19.5 | $1,950.00 |
| 500 | $17.2 | $8,600.00 |
| 1,000 | $15.4 | $15,400.00 |
Drop-in alternatives for EPM570ZM144C7N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570ZM144C6N
β Drop-Inβ In Stock
$7.85 / Unit
View Datasheet βEPM1270ZM144C7N
β Drop-Inπ Reference alternative (not in catalog)
EPM2210ZM144C7N
β Drop-Inπ Reference alternative (not in catalog)
EPM570ZM144C7N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device Sub-Family | EPM570Z (MAX II Z) |
| Logic Elements | 570 |
| Macrocells (Equivalent) | 440 |
| User I/Os (Maximum) | 116 |
| User Flash Memory (UFM) | 8 Kbits |
| Pin-to-Pin Logic Delay | 7.0 ns (speed grade 7) |
| Process Technology | 0.18 um, 6-layer-metal flash |
| Core Supply Voltage | 3.3 V / 2.5 V / 1.8 V (multi-voltage) |
| I/O Bank Voltages | Independent of core (multi-voltage I/O) |
| Package | 144-MBGA (FineLine BGA) |
| Operating Temperature | 0C to +85C (commercial, C suffix) |
| Programming Interface | JTAG (IEEE 1149.1) |
| Internal Oscillator | Yes (on-chip) |
| Configuration Storage | On-chip flash (non-volatile, instant-on) |
| RoHS Status | Compliant |
EPM570ZM144C7N Pin Configuration
| Pin A1 | I/O β User I/O - bank 3 (LVCMOS/LVTTL, multi-voltage) |
| Pin A2 | I/O β User I/O - bank 3 |
| Pin A3 | I/O β User I/O - bank 3 |
| Pin A4 | GND β Ground |
| Pin A5 | I/O β User I/O - bank 2 |
| Pin A6 | I/O β User I/O - bank 2 |
| Pin A7 | I/O β User I/O - bank 2 |
| Pin A8 | I/O β User I/O - bank 2 |
| Pin A9 | I/O β User I/O - bank 2 |
| Pin A10 | I/O β User I/O - bank 2 |
| Pin A11 | I/O β User I/O - bank 2 |
| Pin A12 | I/O β User I/O - bank 2 |
| Pin B1 | I/O β User I/O - bank 3 |
| Pin B2 | I/O β User I/O - bank 3 |
| Pin B3 | I/O β User I/O - bank 3 |
| Pin B4 | GND β Ground |
| Pin B5 | I/O β User I/O - bank 2 |
| Pin B6 | I/O β User I/O - bank 2 |
| Pin B7 | I/O β User I/O - bank 2 |
| Pin B8 | I/O β User I/O - bank 2 |
| Pin B9 | I/O β User I/O - bank 2 |
| Pin B10 | I/O β User I/O - bank 2 |
| Pin B11 | I/O β User I/O - bank 2 |
| Pin B12 | I/O β User I/O - bank 2 |
| Pin C1 | I/O β User I/O - bank 3 |
| Pin C2 | VCCIO3 β I/O bank 3 supply voltage |
| Pin C3 | I/O β User I/O - bank 3 |
| Pin C4 | I/O β User I/O - bank 3 |
| Pin C5 | I/O β User I/O - bank 3 |
| Pin C6 | I/O β User I/O - bank 2 |
| Pin C7 | I/O β User I/O - bank 2 |
| Pin C8 | I/O β User I/O - bank 2 |
| Pin C9 | I/O β User I/O - bank 2 |
| Pin C10 | I/O β User I/O - bank 2 |
| Pin C11 | VCCIO2 β I/O bank 2 supply voltage |
| Pin C12 | I/O β User I/O - bank 2 |
| Pin D1 | I/O β User I/O - bank 3 |
| Pin D2 | I/O β User I/O - bank 3 |
| Pin D3 | GND β Ground |
| Pin D4 | I/O β User I/O - bank 3 |
| Pin D5 | I/O β User I/O - bank 3 |
| Pin D6 | I/O β User I/O - bank 2 |
| Pin D7 | I/O β User I/O - bank 2 |
| Pin D8 | I/O β User I/O - bank 2 |
| Pin D9 | I/O β User I/O - bank 2 |
| Pin D10 | I/O β User I/O - bank 2 |
| Pin D11 | GND β Ground |
| Pin D12 | I/O β User I/O - bank 2 |
| Pin E1 | I/O β User I/O - bank 3 |
| Pin E2 | I/O β User I/O - bank 3 |
| Pin E3 | I/O β User I/O - bank 3 |
| Pin E4 | I/O β User I/O - bank 3 |
| Pin E5 | VCCINT β Core supply voltage (3.3/2.5/1.8 V) |
| Pin E6 | I/O β User I/O - bank 1 |
| Pin E7 | I/O β User I/O - bank 1 |
| Pin E8 | I/O β User I/O - bank 1 |
| Pin E9 | I/O β User I/O - bank 1 |
| Pin E10 | VCCIO1 β I/O bank 1 supply voltage |
| Pin E11 | I/O β User I/O - bank 1 |
| Pin E12 | I/O β User I/O - bank 1 |
| Pin F1 | I/O β User I/O - bank 3 |
| Pin F2 | I/O β User I/O - bank 3 |
| Pin F3 | I/O β User I/O - bank 3 |
| Pin F4 | I/O β User I/O - bank 3 |
| Pin F5 | VCCINT β Core supply voltage |
| Pin F6 | GND β Ground |
| Pin F7 | I/O β User I/O - bank 1 |
| Pin F8 | I/O β User I/O - bank 1 |
| Pin F9 | I/O β User I/O - bank 1 |
| Pin F10 | VCCIO1 β I/O bank 1 supply voltage |
| Pin F11 | I/O β User I/O - bank 1 |
| Pin F12 | I/O β User I/O - bank 1 |
| Pin G1 | I/O β User I/O - bank 3 |
| Pin G2 | I/O β User I/O - bank 3 |
| Pin G3 | I/O β User I/O - bank 3 |
| Pin G4 | I/O β User I/O - bank 3 |
| Pin G5 | VCCINT β Core supply voltage |
| Pin G6 | I/O β User I/O - bank 1 |
| Pin G7 | I/O β User I/O - bank 1 |
| Pin G8 | I/O β User I/O - bank 1 |
| Pin G9 | I/O β User I/O - bank 1 |
| Pin G10 | VCCIO1 β I/O bank 1 supply voltage |
| Pin G11 | I/O β User I/O - bank 1 |
| Pin G12 | I/O β User I/O - bank 1 |
| Pin H1 | I/O β User I/O - bank 3 |
| Pin H2 | I/O β User I/O - bank 3 |
| Pin H3 | I/O β User I/O - bank 3 |
| Pin H4 | I/O β User I/O - bank 3 |
| Pin H5 | VCCINT β Core supply voltage |
| Pin H6 | I/O β User I/O - bank 1 |
| Pin H7 | I/O β User I/O - bank 1 |
| Pin H8 | I/O β User I/O - bank 1 |
| Pin H9 | I/O β User I/O - bank 1 |
| Pin H10 | VCCIO1 β I/O bank 1 supply voltage |
| Pin H11 | I/O β User I/O - bank 1 |
| Pin H12 | I/O β User I/O - bank 1 |
| Pin J1 | I/O β User I/O - bank 4 |
| Pin J2 | I/O β User I/O - bank 4 |
| Pin J3 | I/O β User I/O - bank 4 |
| Pin J4 | I/O β User I/O - bank 4 |
| Pin J5 | VCCIO4 β I/O bank 4 supply voltage |
| Pin J6 | I/O β User I/O - bank 1 |
| Pin J7 | I/O β User I/O - bank 1 |
| Pin J8 | I/O β User I/O - bank 1 |
| Pin J9 | I/O β User I/O - bank 1 |
| Pin J10 | GND β Ground |
| Pin J11 | I/O β User I/O - bank 1 |
| Pin J12 | I/O β User I/O - bank 1 |
| Pin K1 | I/O β User I/O - bank 4 |
| Pin K2 | I/O β User I/O - bank 4 |
| Pin K3 | I/O β User I/O - bank 4 |
| Pin K4 | I/O β User I/O - bank 4 |
| Pin K5 | VCCIO4 β I/O bank 4 supply voltage |
| Pin K6 | GND β Ground |
| Pin K7 | I/O β User I/O - bank 1 |
| Pin K8 | I/O β User I/O - bank 1 |
| Pin K9 | I/O β User I/O - bank 1 |
| Pin K10 | I/O β User I/O - bank 1 |
| Pin K11 | I/O β User I/O - bank 1 |
| Pin K12 | I/O β User I/O - bank 1 |
| Pin L1 | I/O β User I/O - bank 4 |
| Pin L2 | I/O β User I/O - bank 4 |
| Pin L3 | I/O β User I/O - bank 4 |
| Pin L4 | I/O β User I/O - bank 4 |
| Pin L5 | VCCIO4 β I/O bank 4 supply voltage |
| Pin L6 | I/O β User I/O - bank 1 |
| Pin L7 | I/O β User I/O - bank 1 |
| Pin L8 | I/O β User I/O - bank 1 |
| Pin L9 | I/O β User I/O - bank 1 |
| Pin L10 | VCCIO1 β I/O bank 1 supply voltage |
| Pin L11 | I/O β User I/O - bank 1 |
| Pin L12 | I/O β User I/O - bank 1 |
| Pin M1 | I/O β User I/O - bank 4 |
| Pin M2 | I/O β User I/O - bank 4 |
| Pin M3 | I/O β User I/O - bank 4 |
| Pin M4 | I/O β User I/O - bank 4 |
| Pin M5 | VCCIO4 β I/O bank 4 supply voltage |
| Pin M6 | I/O β User I/O - bank 4 |
| Pin M7 | I/O β User I/O - bank 4 |
| Pin M8 | I/O β User I/O - bank 4 |
| Pin M9 | I/O β User I/O - bank 4 |
| Pin M10 | VCCIO4 β I/O bank 4 supply voltage |
| Pin M11 | I/O β User I/O - bank 4 |
| Pin M12 | I/O β User I/O - bank 4 |
| Pin N1 | I/O β User I/O - bank 4 |
| Pin N2 | I/O β User I/O - bank 4 |
| Pin N3 | GND β Ground |
| Pin N4 | I/O β User I/O - bank 4 |
| Pin N5 | I/O β User I/O - bank 4 |
| Pin N6 | I/O β User I/O - bank 4 |
| Pin N7 | I/O β User I/O - bank 4 |
| Pin N8 | I/O β User I/O - bank 4 |
| Pin N9 | I/O β User I/O - bank 4 |
| Pin N10 | I/O β User I/O - bank 4 |
| Pin N11 | GND β Ground |
| Pin N12 | I/O β User I/O - bank 4 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570ZM144C7N is suitable for 7 applications: Industrial Glue Logic and Bus Bridging, Power-Up and Power-Down Sequencing, I/O Expansion for Microcontrollers, LED Display Multiplexing and Driving, Protocol Bridging and Legacy Interface Conversion, Test and Measurement Instrumentation Front-End, Automotive Body Electronics (Non-AEC-Q100).
Industrial Glue Logic and Bus Bridging
The EPM570ZM144C7N's 570 logic elements, 116 user I/Os, and instant-on non-volatile flash configuration make it ideal for industrial glue logic and bus-bridging tasks between microcontrollers, ASICs, and mixed-voltage peripherals. Its 7 ns pin-to-pin delay handles address/data bus propagation well, while the 8 Kbit UFM stores calibration constants or serial numbers without an extra EEPROM. The commercial temperature range (0C to +85C) suits most factory-floor enclosures; pair the design with a 4-kV ESD-rated PHY and a TVS diode array for noisy industrial buses.
Recommended
Power-Up and Power-Down Sequencing
The EPM570ZM144C7N's deterministic, instant-on flash configuration makes it a robust supervisor for power-sequencing multi-rail systems. Place it downstream of a 3.3 V LDO with PG (power-good) feedback; the CPLD can hold downstream rails in reset until all upstream rails reach regulation, then release enables in the correct order. Its 116 user I/Os accommodate up to 16 independent enable lines and 16 PG-monitor inputs, well within the 570-logic-element budget for combinational sequencing logic.
Recommended
I/O Expansion for Microcontrollers
When a microcontroller's GPIO budget is exhausted, the EPM570ZM144C7N can serve as an I/O expander with deterministic response (no software stack involved). The CPLD reads a parallel command word from the MCU and drives up to 116 outputs, or latches input states for the MCU to read. Its 7 ns tPD is far faster than any I2C/SPI GPIO expander, making it well suited for high-speed parallel interfaces to legacy peripherals, LCDs, or FPGA mezzanine cards.
Recommended
LED Display Multiplexing and Driving
The EPM570ZM144C7N's 116 user I/Os and 7 ns logic delay suit large LED matrix multiplexing with minimal flicker. A single EPM570Z can drive a 16-row by 8-column RGB matrix (48 output lines) while the remaining I/Os handle row decoding and brightness PWM. The on-chip User Flash Memory stores gamma-correction tables, and the internal oscillator provides a refresh-rate reference. Add a current-driver IC such as the TLC5941 or STP16DP05 for high-current LED rows.
Recommended
Protocol Bridging and Legacy Interface Conversion
The EPM570ZM144C7N can bridge between legacy and modern protocols - for example, parallel-bus to SPI/UART/I2C, or custom industrial protocols to standard interfaces. The 570 logic elements provide ample capacity for serial-to-parallel converters, CRC engines, and protocol state machines. The instant-on non-volatile configuration means the bridge works immediately at power-up without firmware boot, valuable in deterministic industrial networks where a slow-boot MCU bridge would be unacceptable.
Recommended
Test and Measurement Instrumentation Front-End
The EPM570ZM144C7N's 7 ns logic delay and 116 I/Os make it a flexible front-end for test and measurement: digital pattern generation, signal routing matrices, and trigger logic. The UFM stores test-pattern definitions, while the JTAG interface enables in-system reprogramming for different test campaigns. Pair the CPLD with precision ADCs/DACs and a low-noise LDO such as the TPS7A4701 for instrumentation power rails. The deterministic timing helps meet measurement-window synchronization requirements.
Recommended
Automotive Body Electronics (Non-AEC-Q100)
For non-safety automotive body electronics such as body control modules, lighting controllers, and HVAC panels, the EPM570ZM144C7N provides 116 user I/Os for switch scanning, relay driving, and LIN/CAN bus expansion. Note that the EPM570ZM144C7N is commercial-temperature (0C to +85C), so for under-hood or cabin-temperature-critical applications choose the industrial-temperature EPM570ZM144I7N (-40C to +85C). The MAX II family does not offer an AEC-Q100-qualified variant.
Recommended
Recommended Products Summary
Engineering reference data for EPM570ZM144C7N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570ZM144C6N | EPM1270ZM144C7N | EPM2210ZM144C7N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 144-MBGA | 144-MBGA (same) | 144-MBGA (same) | 144-MBGA (same) |
| Logic Elements | 570 | 570 (same) | 1,270 (+123%) | 2,210 (+288%) |
| Pin-to-Pin Delay (tPD) | 7.0 ns | 6.0 ns (faster) | 7.0 ns (same) | 7.0 ns (same) |
| User I/Os | 116 | 116 (same) | 116 (same) | 116 (same) |
| User Flash Memory (UFM) | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit |
| Process Technology | 0.18 um flash | 0.18 um flash (same) | 0.18 um flash (same) | 0.18 um flash (same) |
| Vertical Migration Support | Yes (MAX II family) | Yes | Yes (same package, higher density) | Yes (same package, highest density) |
Key Differentiators
- Vertical migration within 144-MBGA footprint across MAX II family (vs EPM1270ZM144C7N / EPM2210ZM144C7N)
- Faster 6 ns speed grade available in identical 144-MBGA package (vs EPM570ZM144C6N)
- 8 Kbit on-chip User Flash Memory eliminates external EEPROM (vs Discrete I2C EEPROM (e.g., 24LC256))
Design Notes
The EPM570ZM144C7N requires three separate supply rails: VCCINT (3.3 V / 2.5 V / 1.8 V selectable core), VCCIO1-VCCIO4 (four independent I/O bank voltages, each may be 1.5 V / 1.8 V / 2.5 V / 3.3 V). Decouple each VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed within 100 mils of the BGA ball, plus a bulk 10 uF tantalum or ceramic on each rail. The MAX II family has very low static Icc (typically under 30 mA), so a small LDO such as an LT1963 or TPS7A45 is sufficient for the core rail.
Design the 144-MBGA land pattern on a 0.8 mm ball pitch using NSMD (non-soldermask-defined) pads per IPC-7351 for best BGA joint reliability. Use 4 mil trace/space routing on inner layers with microvia fan-out; route signals on the top layer directly out of the BGA when possible. Provide at least 4 via-in-pad or dog-bone fan-out vias per signal. Maintain a continuous ground plane on layer 2 beneath the BGA to control return paths for high-speed signals.
Do not leave unused I/O pins floating - configure them as outputs driving low or as inputs with internal weak pull-up enabled in the Quartus assignment, otherwise they can float mid-rail and draw shoot-through current. Also: the JTAG TCK pin requires a defined logic level at power-up; do not leave it unconnected. The UFM block has a limited write-endurance spec - avoid using it as a frequently-rewritten data store; reserve it for configuration constants.
Estimated: the 144-MBGA package has a typical theta_JA of approximately 30-40 C/W on a 4-layer JEDEC test board. With typical Icc of 25 mA at 3.3 V core, dissipation is only ~80 mW - well below the thermal limit. Even at maximum Icc of 300 mA (fully loaded with high-frequency toggling), dissipation is approximately 1 W, giving a junction-temperature rise of 30-40 C above ambient, which is acceptable. Forced-air cooling is rarely required for MAX II CPLDs.
Compliance Information
RoHS compliant per Altera/Intel MAX II product family compliance documentation. Lead-free (Pb-free) BGA balls. Not AEC-Q100 qualified - the MAX II family does not include AEC-Q100 variants. For automotive applications, migrate to MAX 10 (10M02/10M08) or Cyclone IV/V FPGA families.
