EPM7128STC100-6 - MAX 7000S CPLD 128-Macrocell 6ns | Intel
MPN: EPM7128STC100-6 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $7.92 | $79.20 |
| 100 | $6.88 | $688.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.2 | $5,200.00 |
Drop-in alternatives for EPM7128STC100-6 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM7128STC100-7
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View Datasheet βEPM7128STC100-6 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Macrocells | 128 |
| Equivalent Gates | 2,500 |
| User I/O Pins | 84 |
| Pin-to-Pin Delay (tPD) | 6 ns |
| Maximum Internal Frequency (fCNT) | 147.1 MHz |
| Supply Voltage (VCCINT / VCCIO) | 5 V |
| Package | 100-pin TQFP (STC100) |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP |
| Operating Temperature | 0C to +70C (commercial) |
| PCI Compliance | 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) |
| Lead Pitch | 1.0 mm (TQFP) |
| Lead-Free / RoHS | Contains lead (non-RoHS original; -6N variant is lead-free) |
| Configuration Memory | On-chip EEPROM (non-volatile) |
EPM7128STC100-6 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell) |
| Pin 2 | I/O β User I/O pin (macrocell) |
| Pin 3 | I/O β User I/O pin (macrocell) |
| Pin 4 | I/O β User I/O pin (macrocell) |
| Pin 5 | I/O β User I/O pin (macrocell) |
| Pin 6 | I/O β User I/O pin (macrocell) |
| Pin 7 | I/O β User I/O pin (macrocell) |
| Pin 8 | I/O β User I/O pin (macrocell) |
| Pin 9 | VCCIO β I/O supply voltage (5 V) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O pin (macrocell) |
| Pin 12 | I/O β User I/O pin (macrocell) |
| Pin 13 | I/O β User I/O pin (macrocell) |
| Pin 14 | I/O β User I/O pin (macrocell) |
| Pin 15 | TDI β JTAG Test Data In |
| Pin 16 | TMS β JTAG Test Mode Select |
| Pin 17 | TCK β JTAG Test Clock |
| Pin 18 | I/O β User I/O pin (macrocell) |
| Pin 19 | I/O β User I/O pin (macrocell) |
| Pin 20 | I/O β User I/O pin (macrocell) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (macrocell) |
| Pin 23 | I/O β User I/O pin (macrocell) |
| Pin 24 | I/O β User I/O pin (macrocell) |
| Pin 25 | I/O β User I/O pin (macrocell) |
| Pin 26 | I/O β User I/O pin (macrocell) |
| Pin 27 | I/O β User I/O pin (macrocell) |
| Pin 28 | VCCINT β Internal core supply voltage (5 V) |
| Pin 29 | I/O β User I/O pin (macrocell) |
| Pin 30 | I/O β User I/O pin (macrocell) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (macrocell) |
| Pin 33 | I/O β User I/O pin (macrocell) |
| Pin 34 | I/O β User I/O pin (macrocell) |
| Pin 35 | I/O β User I/O pin (macrocell) |
| Pin 36 | I/O β User I/O pin (macrocell) |
| Pin 37 | I/O β User I/O pin (macrocell) |
| Pin 38 | I/O β User I/O pin (macrocell) |
| Pin 39 | I/O β User I/O pin (macrocell) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (macrocell) |
| Pin 42 | I/O β User I/O pin (macrocell) |
| Pin 43 | I/O β User I/O pin (macrocell) |
| Pin 44 | I/O β User I/O pin (macrocell) |
| Pin 45 | I/O β User I/O pin (macrocell) |
| Pin 46 | I/O β User I/O pin (macrocell) |
| Pin 47 | INPUT/GCLK β Dedicated input / Global clock |
| Pin 48 | INPUT/OE β Dedicated input / Output enable |
| Pin 49 | I/O β User I/O pin (macrocell) |
| Pin 50 | VCCIO β I/O supply voltage (5 V) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (macrocell) |
| Pin 53 | I/O β User I/O pin (macrocell) |
| Pin 54 | I/O β User I/O pin (macrocell) |
| Pin 55 | I/O β User I/O pin (macrocell) |
| Pin 56 | I/O β User I/O pin (macrocell) |
| Pin 57 | I/O β User I/O pin (macrocell) |
| Pin 58 | I/O β User I/O pin (macrocell) |
| Pin 59 | I/O β User I/O pin (macrocell) |
| Pin 60 | I/O β User I/O pin (macrocell) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (macrocell) |
| Pin 63 | I/O β User I/O pin (macrocell) |
| Pin 64 | I/O β User I/O pin (macrocell) |
| Pin 65 | I/O β User I/O pin (macrocell) |
| Pin 66 | I/O β User I/O pin (macrocell) |
| Pin 67 | I/O β User I/O pin (macrocell) |
| Pin 68 | I/O β User I/O pin (macrocell) |
| Pin 69 | VCCINT β Internal core supply voltage (5 V) |
| Pin 70 | I/O β User I/O pin (macrocell) |
| Pin 71 | I/O β User I/O pin (macrocell) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin (macrocell) |
| Pin 74 | I/O β User I/O pin (macrocell) |
| Pin 75 | I/O β User I/O pin (macrocell) |
| Pin 76 | I/O β User I/O pin (macrocell) |
| Pin 77 | I/O β User I/O pin (macrocell) |
| Pin 78 | I/O β User I/O pin (macrocell) |
| Pin 79 | I/O β User I/O pin (macrocell) |
| Pin 80 | I/O β User I/O pin (macrocell) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin (macrocell) |
| Pin 83 | I/O β User I/O pin (macrocell) |
| Pin 84 | I/O β User I/O pin (macrocell) |
| Pin 85 | I/O β User I/O pin (macrocell) |
| Pin 86 | I/O β User I/O pin (macrocell) |
| Pin 87 | I/O β User I/O pin (macrocell) |
| Pin 88 | TDO β JTAG Test Data Out |
| Pin 89 | I/O β User I/O pin (macrocell) |
| Pin 90 | I/O β User I/O pin (macrocell) |
| Pin 91 | VCCIO β I/O supply voltage (5 V) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O pin (macrocell) |
| Pin 94 | I/O β User I/O pin (macrocell) |
| Pin 95 | I/O β User I/O pin (macrocell) |
| Pin 96 | I/O β User I/O pin (macrocell) |
| Pin 97 | I/O β User I/O pin (macrocell) |
| Pin 98 | I/O β User I/O pin (macrocell) |
| Pin 99 | I/O β User I/O pin (macrocell) |
| Pin 100 | I/O β User I/O pin (macrocell) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128STC100-6 is suitable for 6 applications: 5 V System Glue Logic and Bus Decoding, PCI Local Bus 33 MHz Interface Logic, Industrial Control and PLC Logic Replacement, Boot ROM Replacement and Power Sequencing, JTAG-Configurable I/O Expansion, Legacy Design Maintenance and Second-Sourcing.
5 V System Glue Logic and Bus Decoding
The EPM7128STC100-6 excels as 5 V bus glue logic, replacing dozens of 74-series TTL/CMOS packages with a single programmable device. Its 128 macrocells and 84 user I/Os deliver sufficient capacity for full address decoding, chip-select generation, and wait-state insertion across legacy 8/16/32-bit microprocessor buses. The 6 ns pin-to-pin delay ensures decoded signals meet timing without inserting wait states. The 5 V I/O tolerance is critical because it directly interfaces with 5 V memory, peripherals, and legacy microcontrollers without level shifters. The instant-on EEPROM configuration eliminates boot-loader complexity and provides deterministic power-on behavior required in industrial and automotive controllers.
Recommended
PCI Local Bus 33 MHz Interface Logic
The EPM7128STC100-6 supports 33 MHz PCI Local Bus Specification Revision 2.2 timing in the -6, -7, and -10 speed grades, making it suitable for PCI bus arbitration, address decoding, and signal steering logic in PCI add-in cards and embedded systems. Its 6 ns tPD meets the 33 MHz PCI clock-to-output budget for address/data steering. The 5 V I/O natively drives PCI bus signals, and the 84 user I/Os accommodate multiple PCI device selects plus interrupt steering. For legacy PCI designs that must remain 5 V compliant, the -6 is one of the few CPLDs still qualified for new PCI board production.
Recommended
Industrial Control and PLC Logic Replacement
In industrial controllers and PLCs, the EPM7128STC100-6 consolidates discrete logic functions such as relay driving, encoder decoding, sensor signal conditioning, and PWM generation into a single reprogrammable device. Its 128 macrocells handle multiple independent state machines for motion control, while the 5 V tolerance directly interfaces with industrial 24 V sensor inputs (after external level shifting). The EEPROM-based configuration is field-updatable via JTAG, allowing firmware revisions without board removal. Industrial-grade (-10, -15) and lead-free variants are widely deployed in long-life-cycle factory automation equipment.
Recommended
Boot ROM Replacement and Power Sequencing
The EPM7128STC100-6 is widely used to replace small parallel boot ROMs/Flash in embedded systems where instant-on behavior is required. Unlike serial configuration devices used with FPGAs, the EPM7128STC100-6's on-chip EEPROM eliminates boot latency and provides deterministic outputs at power-up. It also serves as a power-sequencing controller, generating staggered reset and enable signals for multi-rail systems (e.g., 1.8 V core, 3.3 V I/O, 5 V analog) with millisecond-scale programmable delays. The 6 ns tPD ensures reset propagation stays well within system timing budgets.
Recommended
JTAG-Configurable I/O Expansion
Designers use the EPM7128STC100-6 as a JTAG-driven I/O expander to add configurable digital I/O to microcontrollers or ASICs that lack sufficient pins. The 84 user I/Os can be reconfigured in-circuit via the JTAG chain without firmware changes, providing flexibility for prototype development and field upgrades. The 5 V tolerance is compatible with most legacy MCUs, and the 147.1 MHz internal frequency supports fast bit-banging protocols. The SameFrame pin-out feature lets designs scale between TQFP-100 and larger packages without layout changes.
Recommended
Legacy Design Maintenance and Second-Sourcing
For engineers maintaining legacy 5 V designs originally built around the EPM7128STC100-6, the part family provides robust second-sourcing through multiple speed grades and lead-free variants in the identical 100-pin TQFP footprint. The EPM7128STC100-7, -10, and -6N variants are pin-compatible drop-in replacements, allowing procurement flexibility and lifecycle extension when the original -6 is hard to source or counterfeit risk is a concern. The mature Quartus Prime and legacy MAX+PLUS II toolchains continue to support all variants, ensuring existing IP and bitstreams can be retargeted without redesign.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128STC100-6 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128STC100-7 | EPM7128STC100-10 | EPM7128STC100-6N | EPM7128STC100-15N | EPM7128SQC100-6 |
|---|---|---|---|---|---|---|
| Package | 100-pin TQFP (STC100) | 100-pin TQFP (STC100) - same | 100-pin TQFP (STC100) - same | 100-pin TQFP (STC100) - same | 100-pin TQFP (STC100) - same | 100-pin TQFP (SQC100) - same footprint |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| tPD (Pin-to-Pin Delay) | 6 ns | 7 ns | 10 ns | 6 ns (same) | 15 ns | 6 ns (same) |
| fCNT (Max Internal Frequency) | 147.1 MHz | 125 MHz | 100 MHz | 147.1 MHz (same) | 76 MHz | 147.1 MHz (same) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 84 | 84 | 84 | 84 | 84 | 84 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| RoHS Compliance | Non-RoHS (leaded) | Non-RoHS (leaded) | Non-RoHS (leaded) | RoHS-compliant (Pb-free) | RoHS-compliant (Pb-free) | Non-RoHS (leaded) |
| Approximate Unit Price (qty 1) | $8.95 USD | [DATA_NEEDED] | [DATA_NEEDED] | $9.50 USD (est.) | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest-speed grade in the MAX 7000S family in TQFP-100 (vs EPM7128STC100-10)
- 5 V I/O tolerance - legacy system compatibility (vs Modern MAX II EPM570T100C5N)
- Non-volatile EEPROM configuration - instant-on (vs SRAM-based FPGAs (e.g., Cyclone series))
- Industry-standard JTAG ISP and boundary scan (vs EPM7128STC100-6N (lead-free variant))
Design Notes
The EPM7128STC100-6 requires both VCCINT (5 V core) and VCCIO (5 V I/O) supplies; both must be decoupled with 0.1 uF ceramic capacitors placed within 5 mm of each supply pin, plus a bulk 10-47 uF tantalum or aluminum electrolytic capacitor on each supply rail. Power sequencing between VCCINT and VCCIO is not required - the device tolerates simultaneous or VCCIO-first ramp-up. Use a separate analog ground plane if mixing analog and digital signals, but the MAX 7000S is a fully digital device and does not require a quiet analog supply.
The 100-pin TQFP package has a 1.0 mm lead pitch and 0.5 mm lead width - use a PCB footprint with 0.4 mm pad width and 1.0 mm pitch to ensure reliable solder fillets. The TQFP-100 thermal pad is not present on this package; thermal dissipation is via the leads and a copper pour of at least 100 mm^2 on the top layer is recommended. Use 4-mil (0.1 mm) trace-and-space design rules on inner layers; outer layers can use 6-mil traces for signal routing. Avoid running long parallel traces between JTAG pins and high-speed I/O to prevent coupling.
The EPM7128STC100-6 supports 33 MHz PCI Local Bus timing only when the -6, -7, or -10 speed grade is used with proper board layout - keep PCI clock and control trace lengths matched within 1.27 cm (500 mil) of each other. Series-damping resistors (22-33 ohm) on PCI outputs may be needed to control ringing on long backplane traces. For non-PCI applications, the 6 ns tPD still requires controlled-impedance traces (50 ohm microstrip) for clock signals above 50 MHz. All unused I/O pins should be configured as outputs driving low or as inputs with internal pull-ups to minimize supply current.
Do not connect 3.3 V signals directly to the EPM7128STC100-6's 5 V I/O - the device's input VIH is 2.0 V (TTL-compatible), so 3.3 V signals may be accepted, but VOH will still drive 5 V logic levels and may damage downstream 3.3 V components. Use a level shifter or a 3.3 V-tolerant CPLD variant for mixed-voltage designs. Do not assume the legacy MAX+PLUS II software can synthesize modern SystemVerilog or VHDL-2008 constructs - the Quartus Prime toolchain is recommended for new designs and supports the legacy EPM7128STC100-6 device family through the MAX 7000S device support file. Counterfeit risk is elevated for non-RoHS EPM7128STC100-6 stock purchased from brokers - buy from authorized distributors or verify x-ray decapsulation.
Compliance Information
The legacy EPM7128STC100-6 is non-RoHS (contains lead). The lead-free EPM7128STC100-6N variant is RoHS-compliant. Both versions are not AEC-Q100 qualified for automotive applications.
