EPM7128STC100-7 - MAX 7000S CPLD, 128 Macro, 7.5ns, TQFP-100 | Intel
MPN: EPM7128STC100-7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.75 | $157.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.2 | $8,200.00 |
Drop-in alternatives for EPM7128STC100-7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128STC100-10N
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View Datasheet →EPM7128STC100-15N
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View Datasheet →EPM7128STC100-6N
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View Datasheet →EPM7128STC100-10
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View Datasheet →EPM7128AETC100-7N
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View Datasheet →EPM7128STC100-7 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 84 |
| Propagation Delay (tPD) | 7.5 ns |
| Internal Frequency | 125 MHz |
| Supply Voltage (VCCINT) | 5 V |
| Logic Family | CMOS |
| Programmable Pin Count | 100 |
| Package | 100-Pin TQFP (TQFP-100) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| Configuration Memory | EEPROM (non-volatile) |
EPM7128STC100-7 Pin Configuration
| Pin 1 | I/O — User I/O pin (bidirectional) |
| Pin 2 | I/O — User I/O pin (bidirectional) |
| Pin 3 | I/O — User I/O pin (bidirectional) |
| Pin 4 | I/O — User I/O pin (bidirectional) |
| Pin 5 | I/O — User I/O pin (bidirectional) |
| Pin 6 | I/O — User I/O pin (bidirectional) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O pin (bidirectional) |
| Pin 9 | I/O — User I/O pin (bidirectional) |
| Pin 10 | I/O — User I/O pin (bidirectional) |
| Pin 11 | I/O — User I/O pin (bidirectional) |
| Pin 12 | I/O — User I/O pin (bidirectional) |
| Pin 13 | I/O — User I/O pin (bidirectional) |
| Pin 14 | VCC — 5V supply (core and I/O) |
| Pin 15 | I/O — User I/O pin (bidirectional) |
| Pin 16 | I/O — User I/O pin (bidirectional) |
| Pin 17 | I/O — User I/O pin (bidirectional) |
| Pin 18 | I/O — User I/O pin (bidirectional) |
| Pin 19 | I/O — User I/O pin (bidirectional) |
| Pin 20 | I/O — User I/O pin (bidirectional) |
| Pin 21 | I/O — User I/O pin (bidirectional) |
| Pin 22 | I/O — User I/O pin (bidirectional) |
| Pin 23 | GND — Ground |
| Pin 24 | I/O — User I/O pin (bidirectional) |
| Pin 25 | I/O — User I/O pin (bidirectional) |
| Pin 26 | I/O — User I/O pin (bidirectional) |
| Pin 27 | I/O — User I/O pin (bidirectional) |
| Pin 28 | I/O — User I/O pin (bidirectional) |
| Pin 29 | I/O — User I/O pin (bidirectional) |
| Pin 30 | I/O — User I/O pin (bidirectional) |
| Pin 31 | VCC — 5V supply (core and I/O) |
| Pin 32 | I/O — User I/O pin (bidirectional) |
| Pin 33 | I/O — User I/O pin (bidirectional) |
| Pin 34 | I/O — User I/O pin (bidirectional) |
| Pin 35 | I/O — User I/O pin (bidirectional) |
| Pin 36 | I/O — User I/O pin (bidirectional) |
| Pin 37 | I/O — User I/O pin (bidirectional) |
| Pin 38 | I/O — User I/O pin (bidirectional) |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — User I/O pin (bidirectional) |
| Pin 41 | I/O — User I/O pin (bidirectional) |
| Pin 42 | I/O — User I/O pin (bidirectional) |
| Pin 43 | I/O — User I/O pin (bidirectional) |
| Pin 44 | I/O — User I/O pin (bidirectional) |
| Pin 45 | I/O — User I/O pin (bidirectional) |
| Pin 46 | I/O — User I/O pin (bidirectional) |
| Pin 47 | VCC — 5V supply (core and I/O) |
| Pin 48 | I/O — User I/O pin (bidirectional) |
| Pin 49 | I/O — User I/O pin (bidirectional) |
| Pin 50 | I/O — User I/O pin (bidirectional) |
| Pin 51 | I/O — User I/O pin (bidirectional) |
| Pin 52 | I/O — User I/O pin (bidirectional) |
| Pin 53 | I/O — User I/O pin (bidirectional) |
| Pin 54 | I/O — User I/O pin (bidirectional) |
| Pin 55 | GND — Ground |
| Pin 56 | I/O — User I/O pin (bidirectional) |
| Pin 57 | I/O — User I/O pin (bidirectional) |
| Pin 58 | I/O — User I/O pin (bidirectional) |
| Pin 59 | I/O — User I/O pin (bidirectional) |
| Pin 60 | I/O — User I/O pin (bidirectional) |
| Pin 61 | I/O — User I/O pin (bidirectional) |
| Pin 62 | I/O — User I/O pin (bidirectional) |
| Pin 63 | VCC — 5V supply (core and I/O) |
| Pin 64 | I/O — User I/O pin (bidirectional) |
| Pin 65 | I/O — User I/O pin (bidirectional) |
| Pin 66 | I/O — User I/O pin (bidirectional) |
| Pin 67 | I/O — User I/O pin (bidirectional) |
| Pin 68 | I/O — User I/O pin (bidirectional) |
| Pin 69 | I/O — User I/O pin (bidirectional) |
| Pin 70 | I/O — User I/O pin (bidirectional) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin (bidirectional) |
| Pin 73 | I/O — User I/O pin (bidirectional) |
| Pin 74 | I/O — User I/O pin (bidirectional) |
| Pin 75 | I/O — User I/O pin (bidirectional) |
| Pin 76 | I/O — User I/O pin (bidirectional) |
| Pin 77 | I/O — User I/O pin (bidirectional) |
| Pin 78 | I/O — User I/O pin (bidirectional) |
| Pin 79 | VCC — 5V supply (core and I/O) |
| Pin 80 | I/O — User I/O pin (bidirectional) |
| Pin 81 | I/O — User I/O pin (bidirectional) |
| Pin 82 | I/O — User I/O pin (bidirectional) |
| Pin 83 | I/O — User I/O pin (bidirectional) |
| Pin 84 | I/O — User I/O pin (bidirectional) |
| Pin 85 | I/O — User I/O pin (bidirectional) |
| Pin 86 | I/O — User I/O pin (bidirectional) |
| Pin 87 | GND — Ground |
| Pin 88 | I/O — User I/O pin (bidirectional) |
| Pin 89 | I/O — User I/O pin (bidirectional) |
| Pin 90 | I/O — User I/O pin (bidirectional) |
| Pin 91 | I/O — User I/O pin (bidirectional) |
| Pin 92 | I/O — User I/O pin (bidirectional) |
| Pin 93 | I/O — User I/O pin (bidirectional) |
| Pin 94 | I/O — User I/O pin (bidirectional) |
| Pin 95 | VCC — 5V supply (core and I/O) |
| Pin 96 | TDI — JTAG Test Data In |
| Pin 97 | TMS — JTAG Test Mode Select |
| Pin 98 | TCK — JTAG Test Clock |
| Pin 99 | TDO — JTAG Test Data Out |
| Pin 100 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128STC100-7 is suitable for 6 applications: Microprocessor Address Decoding and Bus Glue Logic, DSP and ASIC Peripheral Expansion, Industrial Control State-Machine Controllers, Legacy 5V I/O Expansion for Microcontrollers, Telecom and Networking Glue Logic, Test and Measurement Front-End Logic.
Microprocessor Address Decoding and Bus Glue Logic
The EPM7128STC100-7 is well-suited to microprocessor address decoding and bus-interface glue logic. Its 128 macrocells and 84 user I/Os can replace dozens of 74-series packages while fitting into one 100-pin TQFP. The 7.5 ns tPD ensures chip-select and interrupt signals propagate before the next memory cycle, and the non-volatile EEPROM boot means the decoder is active at power-on with no boot delay. Pair it with a 5V host MCU such as the 8051 or 68k family; the 5V core voltage matches the host rail directly, eliminating level shifters.
Recommended
DSP and ASIC Peripheral Expansion
In DSP and ASIC systems, the EPM7128STC100-7 provides flexible peripheral expansion, implementing FIFO controllers, custom serial interfaces (UART/SPI/I2C bridges), and timing generators that the host processor cannot efficiently handle in software. The 128 macrocells comfortably fit a multi-channel UART plus DMA handshaking logic. With 84 I/Os and 5V native signalling, it interfaces directly to legacy peripheral ICs without level translation, simplifying PCB layout. The JTAG ISP allows in-field firmware upgrades over the same JTAG chain used for the host DSP.
Recommended
Industrial Control State-Machine Controllers
The EPM7128STC100-7 is widely used in industrial control state machines and discrete-logic replacement in PLCs, motor controllers, and process automation equipment. Its deterministic 7.5 ns tPD and 125 MHz internal frequency guarantee cycle-accurate control of relays, contactors, and PWM signals. The non-volatile EEPROM boot and 5V I/O tolerance match the industrial 24V-interface backplane designs after opto-isolation. Designers appreciate the ability to modify state machines via JTAG ISP without pulling boards from service.
Recommended
Legacy 5V I/O Expansion for Microcontrollers
The EPM7128STC100-7 adds general-purpose 5V I/O expansion to 3.3V microcontrollers. A modern Cortex-M or RISC-V host can offload keypad scanning, LCD control, and LED multiplexing to the CPLD, freeing the MCU to focus on application logic. The 84 user I/Os map directly to 7-segment displays, matrix keypads, and GPIO expanders. Because MAX 7000S supports multi-volt I/O on selected banks, the CPLD can bridge a 3.3V MCU to a 5V peripheral bus with no external translator. The instant-on EEPROM boot enables display and keypad handling at the earliest power-on moment.
Recommended
Telecom and Networking Glue Logic
In telecom and networking line cards, the EPM7128STC100-7 implements custom PHY/MAC glue logic, clock muxes, and interrupt aggregators that do not warrant a full FPGA. The 84 I/Os connect to multi-gigabit transceivers, switch fabric ports, and management EEPROMs with deterministic timing suitable for synchronous buses. The 5V I/O matches legacy TDM buses, and the JTAG chain integration simplifies board-level boundary-scan testing during manufacturing. The non-volatile boot ensures the network element reaches a safe state at power-on before any software runs.
Recommended
Test and Measurement Front-End Logic
In bench-top test and measurement equipment, the EPM7128STC100-7 implements front-panel scan matrix control, trigger conditioning, and counter prescalers that need fast deterministic response. The 7.5 ns tPD keeps trigger latency well below the instrument's measurement uncertainty, and the 84 I/Os scan 7-segment displays, rotary encoders, and 4x4 matrix keypads simultaneously. The 5V I/O is ideal for legacy backplanes, and JTAG ISP allows firmware upgrades without opening the enclosure. Engineers can prototype measurement algorithms in a familiar Quartus environment with no MCU firmware loop.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128STC100-7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128STC100-10N | EPM7128STC100-15N | EPM7128STC100-6N | EPM7128AETC100-7 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000AE |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 7.5 ns | 10 ns (+33%) | 15 ns (+100%) | 6 ns (-20%) | 7 ns (-7%) |
| Core Voltage | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| User I/Os | 84 | 84 | 84 | 84 | 84 |
| Internal Frequency | 125 MHz | 125 MHz | 100 MHz | 147.1 MHz | 192.3 MHz |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Active |
| Price Tier (qty-1, as of 2026-09-13) | $18.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Faster tPD than 10 ns and 15 ns speed grades (vs EPM7128STC100-10N / EPM7128STC100-15N)
- Native 5V core supply versus 3.3V AE family (vs EPM7128AETC100-7)
- Larger TQFP-100 footprint with 84 I/Os versus PLCC-84 with 68 I/Os (vs EPM7128SLC84-7N)
- Lower cost than legacy 7 ns speed grades (vs EPM7128STC100-6N)
Design Notes
The EPM7128STC100-7 requires a clean 5V VCC rail on all VCC pins (1, 14, 31, 47, 63, 79, 95 in the TQFP-100 package). Estimated: at full toggle activity on all 84 I/Os with 25 pF loads at 50 MHz, ICC can reach approximately 300-400 mA. Place one 0.1uF ceramic decoupling capacitor adjacent to every VCC/GND pair, plus a single 10uF tantalum bulk capacitor near the package. Inrush during ISP programming can briefly draw 500 mA - ensure the regulator has adequate headroom.
Place all 7 VCC pins and 7 GND pins on a continuous power plane under the TQFP-100 footprint. Keep the JTAG header (TDI/TDO/TMS/TCK on pins 96-99) routed with 4 dedicated signal traces and a TCK pull-down to ground if not actively driven. Use a 100-ohm series terminator on TDO if the JTAG cable exceeds 100 mm. Maintain at least 5 mm clearance between TQFP-100 traces and adjacent connectors to simplify probe access during in-system programming.
Do not confuse the EPM7128STC100-7 (MAX 7000S, 5V core) with the EPM7128AETC100-7 (MAX 7000AE, 3.3V core); the AE variant requires a different core voltage and JTAG programming setup. Also, the pinout table in the Altera MAX 7000 datasheet includes dedicated global clock pins (GCLK1, GCLK2, GCLK3) and dedicated OE pins (OE1, OE2, OE3) that must be honored; treating them as regular I/Os prevents proper global clock routing. Refer to the pcbsync.com MAX 7000 series guide for the exact TQFP-100 pin assignment.
For high-speed designs above 50 MHz, route all user I/O signals on the top layer directly under the package fanout with controlled impedance (typically 50 ohm single-ended). Use via-stitching around the TQFP-100 ground pad to maintain a low-impedance return path; the exposed die-attach paddle is internally grounded. Avoid running high-slew signals (clocks, fast edges) parallel to JTAG traces for more than 25 mm to prevent crosstalk into the programming chain.
Compliance Information
RoHS/REACH status not stated in verified web data. Commercial temperature grade only (0C to +70C); no AEC-Q100 automotive variant exists in the MAX 7000S family. Refer to the manufacturer datasheet for environmental compliance details.
