EPM7160SLI84-10 - MAX 7000S CPLD, 160 Macrocells, 84-PLCC | Intel
MPN: EPM7160SLI84-10 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM7160SLI84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160SLC84-10
β Drop-Inβ In Stock
$35.77 / Unit
View Datasheet βEPM7160SLC84-10N
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7160SLC84-15
β Drop-Inβ In Stock
$10.8 / Unit
View Datasheet βEPM7160SLC84-6
β Drop-Inβ In Stock
$15.86 / Unit
View Datasheet βEPM7256SLI84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELI84-20
β Drop-Inβ In Stock
$11.1 / Unit
View Datasheet βEPM7160SLI84-10 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000S |
| Family | CPLD - Complex Programmable Logic Device |
| Usable Gates | 3,200 |
| Macrocells | 160 |
| Logic Elements | 160 |
| User I/O Pins | 64 |
| Propagation Delay (tpd) | 10 ns |
| Internal Counter Frequency | 167 MHz |
| Operating Frequency (max) | 100 MHz |
| Supply Voltage | 5.0 V |
| Technology | CMOS, EEPROM-based |
| Package | 84-pin PLCC (LCC-84) |
| Mounting Type | Surface Mount / Through-Hole (socket) |
| Operating Temperature | 0C to +70C (Commercial) |
| Programmability | In-System (JTAG IEEE 1149.1) + EEPROM |
| MultiVolt I/O | Yes (2.5V / 3.3V / 5V) |
| I/O Standards | LVTTL, LVCMOS, TTL, CMOS |
EPM7160SLI84-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 2 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 3 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 4 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 5 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 6 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 7 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 8 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 11 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 12 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 13 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 14 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 15 | TDI β JTAG Test Data In |
| Pin 16 | TMS β JTAG Test Mode Select |
| Pin 17 | TCK β JTAG Test Clock |
| Pin 18 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 19 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 20 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 21 | VCC β 5.0V core supply |
| Pin 22 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 25 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 26 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 27 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 28 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 29 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 30 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 33 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 34 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 35 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 36 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 37 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 38 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 39 | I/O β User I/O pin (macrocell I/O bank 2) |
| Pin 40 | VCC β 5.0V core supply |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 43 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 44 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 45 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 46 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 47 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 48 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 49 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 52 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 53 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 54 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 55 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 56 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 57 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 58 | I/O β User I/O pin (macrocell I/O bank 3) |
| Pin 59 | VCC β 5.0V core supply |
| Pin 60 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 63 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 64 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 65 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 66 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 67 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 68 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 69 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 72 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 73 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 74 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 75 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 76 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 77 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 78 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 79 | I/O β User I/O pin (macrocell I/O bank 4) |
| Pin 80 | VCC β 5.0V core supply |
| Pin 81 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 82 | I/O β User I/O pin (macrocell I/O bank 1) |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | I/O β User I/O pin (macrocell I/O bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SLI84-10 is suitable for 6 applications: 5V Microprocessor Address Decoding, Industrial Glue Logic Replacement, Peripheral Bus Interface Bridging, State Machine and Sequencer Controllers, Legacy System Maintenance and Field Repair, Prototype and Educational Logic Development.
5V Microprocessor Address Decoding
The EPM7160SLI84-10 is ideally suited for address and bus decoding in 5V 80x86, 68k, and PowerPC microprocessor systems. With 160 macrocells and 64 user I/Os, it can decode multi-bank memory maps, generate chip-select signals for peripheral banks, and implement wait-state logic. The 10 ns pin-to-pin delay ensures address-to-chip-select timing fits within a single 33 MHz bus cycle. Designers can use the Quartus II schematic or HDL entry to implement address-decode logic in a single device, replacing multiple 22V10-style PLDs.
Recommended
Industrial Glue Logic Replacement
The EPM7160SLI84-10 consolidates multiple discrete TTL/CMOS glue-logic ICs (gates, latches, multiplexers, flip-flops) into a single programmable device for legacy industrial control systems. The on-chip EEPROM provides instant-on configuration with no boot PROM, critical for deterministic power-up sequencing in factory automation. With 5V MultiVolt I/O, the device interfaces directly to 5V sensors and actuators while driving 3.3V downstream microcontrollers. The 84-PLCC package supports socket-mounting for easy field replacement in deployed systems.
Recommended
Peripheral Bus Interface Bridging
The EPM7160SLI84-10 acts as a programmable bridge between legacy ISA, VME, or proprietary peripheral buses and modern processor interfaces. Its 64 user I/Os handle bidirectional address, data, and control signals across bus standards. The 167 MHz internal counter frequency supports protocol conversion at high bus speeds, while the 10 ns tpd provides margin for clock-domain crossing logic. MultiVolt I/O permits direct connection to both 5V peripheral buses and 3.3V host processors without external transceivers.
Recommended
State Machine and Sequencer Controllers
The EPM7160SLI84-10 implements complex finite state machines and sequencer logic for embedded control applications. With 160 macrocells organized as flip-flop-rich logic blocks, it can hold multi-state FSMs with parallel datapath control. The 100 MHz fMAX supports sequencing at high event rates in test instrumentation and motor control loops. Designers use Quartus II state-machine entry or VHDL/Verilog to compile optimized state machines with deterministic 10 ns transition delays.
Recommended
Legacy System Maintenance and Field Repair
The EPM7160SLI84-10 is in last-time-buy status and is widely used to maintain deployed industrial, military, and telecom systems originally designed in the late 1990s. Its socket-compatible PLCC-84 package allows field replacement without PCB rework. Field service engineers keep spares inventory for systems whose lifecycle exceeds the original CPLD production run. Programming files archived in JTAG or .POF format from original MAX+PLUS II designs can be downloaded to replacement units without redesign.
Recommended
Prototype and Educational Logic Development
The EPM7160SLI84-10 is used in university and engineering lab settings where students learn digital design with CPLDs. Its 160 macrocells provide sufficient logic capacity for course projects such as RISC CPU cores, custom arithmetic units, and bus-protocol controllers. The Quartus II Web Edition software supports free VHDL/Verilog synthesis and JTAG programming. The 84-PLCC package fits standard educational development boards and is rugged enough for repeated student handling.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SLI84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10 | EPM7160SLC84-10N | EPM7160SLC84-15 | EPM7160SLC84-6 | EPM7256SLI84-10 | EPM7160ELI84-20 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC (LCC-84) | 84-pin PLCC (LCC-84) - same | 84-pin PLCC (LCC-84) - same | 84-pin PLCC (LCC-84) - same | 84-pin PLCC (LCC-84) - same | 84-pin PLCC (LCC-84) - same | 84-pin PLCC (LCC-84) - same |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 256 (+60%) | 160 |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 5,000 | 3,200 |
| Propagation Delay (tpd) | 10 ns | 10 ns | 10 ns | 15 ns | 6 ns | 10 ns | 20 ns |
| Internal Counter Frequency | 167 MHz | 167 MHz | 167 MHz | 125 MHz | [DATA_NEEDED] | 167 MHz | [DATA_NEEDED] |
| User I/O | 64 | 64 | 64 | 64 | 64 | 68 | 64 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
Key Differentiators
- Industry-standard 5V MultiVolt I/O with 64 user I/Os (vs EPM7256SLI84-10)
- MAX 7000S second-generation architecture with on-chip EEPROM (vs EPM7160ELI84-20)
- Industrial temperature grade (-40C to +85C) in same package (vs EPM7160SLC84-10)
Design Notes
The EPM7160SLI84-10 operates from a single 5.0 V supply with ICC typically 50-100 mA depending on output loading and logic utilization. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF tantalum bulk capacitor near the package. The MultiVolt I/O feature requires VCCIO to be set per I/O bank; ensure VCCIO matches the driven receiver voltage (2.5V/3.3V/5V). Power sequencing is not required because configuration is stored in on-chip EEPROM.
Use a 4-layer PCB with a dedicated ground plane for the EPM7160SLI84-10 to minimize switching noise on the high-speed JTAG and I/O pins. Route TCK away from high-edge-rate signals and keep JTAG traces under 6 inches to avoid signal-integrity issues. For the 84-PLCC package, provide a recommended land pattern per JEDEC and consider a socket for prototype reworkability. Place a JTAG header (2x5 or 2x10 pin 0.1-inch) near the device for programming access.
Avoid confusing the temperature grade suffix: 'C' means Commercial (0C-70C), 'I' means Industrial (-40C-85C), and 'E' means Extended (-40C-100C). The EPM7160SLI84-10 is rated for commercial temperature only; for industrial applications choose EPM7160SRI84-10. Also note that the -10 speed grade is the standard commercial option; -7 is faster but may have lower availability. Always verify JTAG chain order when multiple devices share the programming bus, as incorrect TDI/TDO chaining will fail programming.
Compliance Information
Compliance data not available in the verified web data for the EPM7160SLI84-10 vintage part; the 'N' suffix variants (e.g., EPM7160SLC84-10N) are lead-free per MAX 7000S family ordering information.
