RTAX2000D-CQ352E - 2M-Gate Rad-Tolerant FPGA CQFP-352 | Microchip
MPN: RTAX2000D-CQ352E ✓ Active| Qty | Unit Price | Extended |
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Drop-in alternatives for RTAX2000D-CQ352E — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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RTAX2000D-CQ352V
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$2560 / Unit
View Datasheet →RTAX2000D-1CQ352V
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$3950 / Unit
View Datasheet →RTAX2000DL-CQ352B
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View Datasheet →RTAX2000DL-1CQ352V
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$2950 / Unit
View Datasheet →RTAX4000D-CQ352E
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View Datasheet →RTAX4000DL-CQ352E
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View Datasheet →RTAX2000D-CQ352E Maximum Ratings & Electrical Characteristics
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Equivalent System Gates | 2000000 gates |
| Logic Cells | 29568 cells |
| CLB Organization | 19712 CLBs |
| Maximum Clock Frequency | 649 MHz |
| Number of Inputs | 166 |
| Number of Outputs | 166 |
| Technology | Digital CMOS, antifuse programmable |
| Package | CQFP-352 (352-terminal ceramic quad flat pack) |
| Mounting Type | Surface Mount |
| Screening | MIL-STD-883 Class (per distributor data) |
| Program Type | One-time programmable (antifuse) |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic |
| System Features | Segmentable clocks, chip-wide highway routing, carry logic |
RTAX2000D-CQ352E cqfp-352 (352-terminal ceramic quad flat pack) Pin Configuration Guide
Complete pinout information for RTAX2000D-CQ352E (cqfp-352 (352-terminal ceramic quad flat pack) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for RTAX2000D-CQ352E.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
RTAX2000D-CQ352E is suitable for 6 applications: Satellite Payload Data Processing, Spacecraft Bus Control and Housekeeping, Telemetry and Telecommand Interfaces, Instrument Sensor Interface Glue Logic, Reconfigurable Computing Modules for LEO Missions, Launch Vehicle and Avionics Support Electronics.
Satellite Payload Data Processing
The RTAX2000D-CQ352E fits payload processing chains that need 2,000,000 system gates and 29,568 logic cells of rad-tolerant capacity with clock rates up to 649 MHz. Its embedded SRAM blocks with built-in FIFO control absorb high-rate sensor or downlink data, while carry logic accelerates DSP datapaths such as FFTs and filters. Because the antifuse configuration cannot be upset on orbit, the design avoids configuration-memory SEU mitigation required by SRAM FPGAs, reducing software overhead. Implemented in the 352-terminal CQFP with 166 I/O, it bridges payload interfaces between high-rate digitizers and telemetry formatters, and its MIL-STD-883 Class screening supports flight qualification campaigns.
Recommended
Spacecraft Bus Control and Housekeeping
Spacecraft bus controllers, mode managers, and power/thermal housekeeping logic benefit from the RTAX2000D-CQ352E's permanent antifuse configuration: once programmed, the boot behavior is deterministic with no configuration PROM that could fail in orbit. The 29,568 logic cells provide ample capacity for redundant controllers, watchdog logic, and interface bridges (UART, MIL-STD-style serial protocols, GPIO expansion) across the 166 available I/O. Segmentable clocks let designers isolate timing domains between the main bus state machine and slower housekeeping polling logic. The CQ352 ceramic package withstands the thermal cycling of LEO orbits, and MIL-STD-883 Class screening aligns with typical bus electronics qualification flows.
Recommended
Telemetry and Telecommand Interfaces
TT&C (telemetry, tracking, and command) chains demand deterministic, upset-resistant logic between the RF/decoder front end and the onboard computer. The RTAX2000D-CQ352E implements framing, error correction (e.g., convolutional or RS coding datapaths using its carry logic), and packet routing within 2M gates at clock speeds up to 649 MHz, while its 166 inputs and outputs connect decoders, encoders, and bus transceivers. Embedded SRAM FIFOs buffer asynchronous rate transitions between the downlink formatter and payload data sources. The antifuse fabric eliminates configuration-memory errors, and the D-suffix ICCA screening at 125 C final test gives documented current limits for power-budget verification in the TT&C subsystem.
Recommended
Instrument Sensor Interface Glue Logic
Science instruments - imagers, spectrometers, and particle detectors - require custom timing generators, ADC framing, and co-addition logic close to the sensor head. The RTAX2000D-CQ352E provides this glue logic with 2,000,000 gates, dedicated carry chains for on-chip accumulation, and 166 bidirectional I/O for clocking and data capture across the CQ352 package. Segmentable clocks allow independent pixel-rate and readout-rate domains, and embedded SRAM/FIFO blocks stage data toward the payload processor. Its radiation-tolerant CMOS process and MIL-STD-883 Class screening target the accumulated dose and single-event environment of the instrument's orbit, while the antifuse one-time programming locks timing relationships that must never drift in flight.
Recommended
Reconfigurable Computing Modules for LEO Missions
Onboard computing modules in LEO missions use the RTAX2000D-CQ352E as the rad-tolerant compute core for image pre-processing, compression, and autonomous decision logic. The 649 MHz maximum clock frequency and Axcelerator-derived hierarchical routing sustain high-throughput pipelines, while the 29,568 logic cells accommodate parallel MAC arrays and control state machines. Chip-wide highway routing distributes global enables and resets with low skew across the die. Because the configuration is antifuse-based, the module survives SEU-prone regions such as the South Atlantic Anomaly without needing scrubbing controllers, simplifying the compute module design and improving availability for time-critical observation scheduling.
Recommended
Launch Vehicle and Avionics Support Electronics
Support electronics for launch vehicles and space avionics - sequencing logic, safe-and-arm interfaces, and redundancy voting circuits - leverage the RTAX2000D-CQ352E's fixed antifuse configuration and MIL-STD-883 Class screening. The device implements triple-modular redundancy voters and synchronizers across its 29,568 logic cells, with 166 I/O sufficient for cross-strapped sensor and command channels in the ceramic CQ352 package. Deterministic boot from antifuse fabric removes configuration-readout vulnerabilities during the vibrational and radiational ascent environment. Segmentable clocks separate safety-critical timing from telemetry functions, and the D-die ICCA screening supports documented current conformance for mission assurance reviews.
Recommended
Recommended Products Summary
Engineering reference data for RTAX2000D-CQ352E — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | RTAX2000D-CQ352V | RTAX2000DL-CQ352B | RTAX4000D-CQ352E | RTAX4000DL-CQ352E |
|---|---|---|---|---|---|
| Package | CQFP-352 | CQFP-352 - same | CQFP-352 - same | CQFP-352 - same | CQFP-352 - same |
| Brand | Microchip Technology (Actel/Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Equivalent System Gates | 2000000 gates | 2000000 gates | 2000000 gates | 4000000 gates | 4000000 gates |
| Logic Cells | 29568 | 29568 | 29568 | [DATA_NEEDED] | [DATA_NEEDED] |
| Maximum Clock Frequency | 649 MHz | 649 MHz | 649 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| Screening Level | E (MIL-STD-883 Class, D-die ICCA screen) | V screening | DL current-screen, B level | E (D die) | E (DL current-screen) |
| Inputs / Outputs | 166 in / 166 out | 166 / 166 | 166 / 166 | [DATA_NEEDED] | [DATA_NEEDED] |
| Program Technology | Antifuse (one-time programmable) | Antifuse | Antifuse | Antifuse | Antifuse |
Key Differentiators
- Screening flexibility within one footprint (vs RTAX2000DL-CQ352B)
- 2x density growth path without respin (vs RTAX4000D-CQ352E)
- Configuration-immune antifuse fabric (vs SRAM-based space FPGAs (e.g., Xilinx Virtex families))
- High system performance for rad-tolerant logic (vs RTAX2000SL-CQ352V)
Design Notes
The RTAX2000D-CQ352E is one-time programmable: a programming error renders the device unusable. Complete functional verification and timing closure on the commercial Axcelerator counterpart (A3PE3000 family) or an RTAX prototyping variant before committing flight devices. The Aldec ACT-H3Ki-CQ352 adaptor provides RTAX CQ352 footprint emulation for this purpose. Also confirm the die suffix (D versus DL) matches your power-budget documentation, since ICCA current screening at 125 C final electrical test differs between the two.
The CQFP-352 ceramic package attaches via solder columns; per the RTAX-S/SL datasheet, only QA electrical and mechanical visual inspection are performed after solder column attachment. Design the land pattern to the manufacturer's CQFP-352 solder-column footprint, verify coplanarity at incoming inspection, and avoid rework - solder-column CQFP joints are not reliably reworked without risk to the column attachment. Allow keep-out clearance around all four sides for the protruding leads and for probe access during board-level test.
Estimated: power budget planning should use the ICCA-screened current limits for the D die and, for tighter budgets, select the DL variant whose ICCA limits are screened at 125 C final electrical test. Derate the 649 MHz maximum clock figure to your actual timing-closure frequency when estimating dynamic power, and validate with Microchip's power estimation tools for the RTAX family. Consult the RTAX-S/SL datasheet power sections for per-bank I/O current limits before finalizing supply rail sizing.
With 166 inputs and 166 outputs in the CQFP-352, group switching banks and assign ground returns to adjacent pins to limit simultaneous-switching noise on the ceramic package. Use the chip-wide highway routing for global resets and enables rather than consuming general routing, and exploit segmentable clocks to isolate timing domains. Simulate flight timing at your closed-loop frequency, not the 649 MHz headline number, since routing utilization at 2M gates heavily influences achievable speed.
Compliance Information
Space-grade hermetic ceramic CQFP package; screened to MIL-STD-883 Class requirements per distributor data. RoHS/REACH declarations not found in provided data - request certificates from Microchip for this space-grade MPN.
