EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera
MPN： EPM7128SQC160-15N ✗ 停產EPM7128SQC160-15N 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with the density of a small FPGA. Within the broader programmable-logic taxonomy, CPLDs sit between discrete PALs (small, simple, fast) and FPGAs (large, register-rich, SRAM-based). The MAX 7000 family was Altera's second-generation CPLD architecture (succeeding the classic MAX 5000/9000) and introduced the multi-matrix interconnect plus ISP (in-system programmability) via JTAG, features that made it the de-facto industry standard for glue logic from the mid-1990s onward.
Key features of the EPM7128SQC160-15N include 128 macrocells arranged in 8 logic array blocks (LABs), 100 user I/O pins, 15ns combinatorial propagation delay, a maximum internal counter frequency of 76.9 MHz, and 5V-tolerant I/O supporting both 3.3V and 5V mixed-voltage systems. The device is non-volatile (EEPROM-based) so the configuration is retained without an external boot PROM, and it supports in-system programming via the JTAG-compatible 4-pin interface. Programmable interconnect allows wide AND-OR logic functions across LABs with predictable timing.
The architecture uses Altera's classic MAX (Multiple Array matriX) routing structure: each LAB contains 16 macrocells that share a programmable interconnect array, and LABs communicate through the PIA (Programmable Interconnect Array). This gives the EPM7128SQC160-15N deterministic, pin-locked timing that does not change with routing density - a property that distinguishes CPLDs from SRAM-based FPGAs where delay varies with placement.
Typical applications include bus-interface bridging (PCI/ISA glue logic), address decoding and chip-select generation, power-up sequencing and reset distribution, motor control peripheral logic, industrial PLC I/O expansion, and replacement of multiple discrete TTL/CMOS logic packages. The wide 5V I/O tolerance is especially valued when interfacing legacy microcontrollers or bus transceivers to modern 3.3V ASICs.
When designing with this device, note that the PQFP-160 footprint has longer lead lengths than modern BGA/QFN packages, which limits high-speed signal edge rates above ~50 MHz. For new designs above 100 MHz I/O, consider migrating to a MAX V, MAX 10, or MAX II CPLD in a smaller QFN package while preserving the MAX 7000 logic architecture.
This page synthesizes distributor pricing, SameFrame-pinout drop-in alternatives, and practical glue-logic design notes not found in the original 1998-vintage datasheet.
直接替換替代品，適用於 EPM7128SQC160-15N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM7128SQC160-15N （相同外形與佔位） — 差異在於 Package, Operating Temperature, Supply Voltage (VCCINT), Logic Array Blocks (LABs), Usable Gates.
EPM7128SQC160-15
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SQC160-10
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SQC160-10N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128SQC100-15
✅ 直接替換✗ 缺貨
$8.2 / 單位
查看資料表 →EPM7128SQC160-15N 最大額定值與電氣特性
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/O Count | 100 |
| Usable Gates | 2.5K |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Frequency | 76.9 MHz |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V mixed |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG-compatible) |
| 封裝 | 160-pin PQFP / BQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount |
| 工作溫度 | 0°C to +70°C (commercial) |
EPM7128SQC160-15N 腳位配置
| 腳位 1 | I/O — User I/O pin (function per design) |
| 腳位 2 | I/O — User I/O pin (function per design) |
| 腳位 3 | I/O — User I/O pin (function per design) |
| 腳位 4 | I/O — User I/O pin (function per design) |
| 腳位 5 | I/O — User I/O pin (function per design) |
| 腳位 6 | I/O — User I/O pin (function per design) |
| 腳位 7 | I/O — User I/O pin (function per design) |
| 腳位 8 | I/O — User I/O pin (function per design) |
| 腳位 9 | I/O — User I/O pin (function per design) |
| 腳位 10 | I/O — User I/O pin (function per design) |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O pin (function per design) |
| 腳位 13 | I/O — User I/O pin (function per design) |
| 腳位 14 | I/O — User I/O pin (function per design) |
| 腳位 15 | I/O — User I/O pin (function per design) |
| 腳位 16 | I/O — User I/O pin (function per design) |
| 腳位 17 | I/O — User I/O pin (function per design) |
| 腳位 18 | I/O — User I/O pin (function per design) |
| 腳位 19 | I/O — User I/O pin (function per design) |
| 腳位 20 | I/O — User I/O pin (function per design) |
| 腳位 21 | GND — Ground |
| 腳位 22 | I/O — User I/O pin (function per design) |
| 腳位 23 | I/O — User I/O pin (function per design) |
| 腳位 24 | I/O — User I/O pin (function per design) |
| 腳位 25 | I/O — User I/O pin (function per design) |
| 腳位 26 | I/O — User I/O pin (function per design) |
| 腳位 27 | I/O — User I/O pin (function per design) |
| 腳位 28 | I/O — User I/O pin (function per design) |
| 腳位 29 | I/O — User I/O pin (function per design) |
| 腳位 30 | I/O — User I/O pin (function per design) |
| 腳位 31 | GND — Ground |
| 腳位 32 | I/O — User I/O pin (function per design) |
| 腳位 33 | I/O — User I/O pin (function per design) |
| 腳位 34 | I/O — User I/O pin (function per design) |
| 腳位 35 | I/O — User I/O pin (function per design) |
| 腳位 36 | I/O — User I/O pin (function per design) |
| 腳位 37 | I/O — User I/O pin (function per design) |
| 腳位 38 | I/O — User I/O pin (function per design) |
| 腳位 39 | I/O — User I/O pin (function per design) |
| 腳位 40 | I/O — User I/O pin (function per design) |
| 腳位 41 | GND — Ground |
| 腳位 42 | I/O — User I/O pin (function per design) |
| 腳位 43 | I/O — User I/O pin (function per design) |
| 腳位 44 | I/O — User I/O pin (function per design) |
| 腳位 45 | I/O — User I/O pin (function per design) |
| 腳位 46 | I/O — User I/O pin (function per design) |
| 腳位 47 | I/O — User I/O pin (function per design) |
| 腳位 48 | I/O — User I/O pin (function per design) |
| 腳位 49 | I/O — User I/O pin (function per design) |
| 腳位 50 | I/O — User I/O pin (function per design) |
| 腳位 51 | GND — Ground |
| 腳位 52 | I/O — User I/O pin (function per design) |
| 腳位 53 | I/O — User I/O pin (function per design) |
| 腳位 54 | I/O — User I/O pin (function per design) |
| 腳位 55 | I/O — User I/O pin (function per design) |
| 腳位 56 | I/O — User I/O pin (function per design) |
| 腳位 57 | I/O — User I/O pin (function per design) |
| 腳位 58 | I/O — User I/O pin (function per design) |
| 腳位 59 | I/O — User I/O pin (function per design) |
| 腳位 60 | I/O — User I/O pin (function per design) |
| 腳位 61 | GND — Ground |
| 腳位 62 | I/O — User I/O pin (function per design) |
| 腳位 63 | I/O — User I/O pin (function per design) |
| 腳位 64 | I/O — User I/O pin (function per design) |
| 腳位 65 | I/O — User I/O pin (function per design) |
| 腳位 66 | I/O — User I/O pin (function per design) |
| 腳位 67 | I/O — User I/O pin (function per design) |
| 腳位 68 | I/O — User I/O pin (function per design) |
| 腳位 69 | I/O — User I/O pin (function per design) |
| 腳位 70 | I/O — User I/O pin (function per design) |
| 腳位 71 | GND — Ground |
| 腳位 72 | I/O — User I/O pin (function per design) |
| 腳位 73 | I/O — User I/O pin (function per design) |
| 腳位 74 | I/O — User I/O pin (function per design) |
| 腳位 75 | I/O — User I/O pin (function per design) |
| 腳位 76 | I/O — User I/O pin (function per design) |
| 腳位 77 | I/O — User I/O pin (function per design) |
| 腳位 78 | I/O — User I/O pin (function per design) |
| 腳位 79 | I/O — User I/O pin (function per design) |
| 腳位 80 | I/O — User I/O pin (function per design) |
| 腳位 81 | GND — Ground |
| 腳位 82 | I/O — User I/O pin (function per design) |
| 腳位 83 | I/O — User I/O pin (function per design) |
| 腳位 84 | I/O — User I/O pin (function per design) |
| 腳位 85 | I/O — User I/O pin (function per design) |
| 腳位 86 | I/O — User I/O pin (function per design) |
| 腳位 87 | I/O — User I/O pin (function per design) |
| 腳位 88 | I/O — User I/O pin (function per design) |
| 腳位 89 | I/O — User I/O pin (function per design) |
| 腳位 90 | I/O — User I/O pin (function per design) |
| 腳位 91 | GND — Ground |
| 腳位 92 | I/O — User I/O pin (function per design) |
| 腳位 93 | I/O — User I/O pin (function per design) |
| 腳位 94 | I/O — User I/O pin (function per design) |
| 腳位 95 | I/O — User I/O pin (function per design) |
| 腳位 96 | I/O — User I/O pin (function per design) |
| 腳位 97 | I/O — User I/O pin (function per design) |
| 腳位 98 | I/O — User I/O pin (function per design) |
| 腳位 99 | I/O — User I/O pin (function per design) |
| 腳位 100 | I/O — User I/O pin (function per design) |
| 腳位 101 | GND — Ground |
| 腳位 102 | I/O — User I/O pin (function per design) |
| 腳位 103 | I/O — User I/O pin (function per design) |
| 腳位 104 | I/O — User I/O pin (function per design) |
| 腳位 105 | I/O — User I/O pin (function per design) |
| 腳位 106 | I/O — User I/O pin (function per design) |
| 腳位 107 | I/O — User I/O pin (function per design) |
| 腳位 108 | I/O — User I/O pin (function per design) |
| 腳位 109 | I/O — User I/O pin (function per design) |
| 腳位 110 | I/O — User I/O pin (function per design) |
| 腳位 111 | GND — Ground |
| 腳位 112 | I/O — User I/O pin (function per design) |
| 腳位 113 | I/O — User I/O pin (function per design) |
| 腳位 114 | I/O — User I/O pin (function per design) |
| 腳位 115 | I/O — User I/O pin (function per design) |
| 腳位 116 | I/O — User I/O pin (function per design) |
| 腳位 117 | I/O — User I/O pin (function per design) |
| 腳位 118 | I/O — User I/O pin (function per design) |
| 腳位 119 | I/O — User I/O pin (function per design) |
| 腳位 120 | I/O — User I/O pin (function per design) |
| 腳位 121 | GND — Ground |
| 腳位 122 | I/O — User I/O pin (function per design) |
| 腳位 123 | I/O — User I/O pin (function per design) |
| 腳位 124 | I/O — User I/O pin (function per design) |
| 腳位 125 | I/O — User I/O pin (function per design) |
| 腳位 126 | I/O — User I/O pin (function per design) |
| 腳位 127 | I/O — User I/O pin (function per design) |
| 腳位 128 | I/O — User I/O pin (function per design) |
| 腳位 129 | I/O — User I/O pin (function per design) |
| 腳位 130 | I/O — User I/O pin (function per design) |
| 腳位 131 | GND — Ground |
| 腳位 132 | I/O — User I/O pin (function per design) |
| 腳位 133 | I/O — User I/O pin (function per design) |
| 腳位 134 | I/O — User I/O pin (function per design) |
| 腳位 135 | I/O — User I/O pin (function per design) |
| 腳位 136 | I/O — User I/O pin (function per design) |
| 腳位 137 | I/O — User I/O pin (function per design) |
| 腳位 138 | I/O — User I/O pin (function per design) |
| 腳位 139 | I/O — User I/O pin (function per design) |
| 腳位 140 | I/O — User I/O pin (function per design) |
| 腳位 141 | GND — Ground |
| 腳位 142 | I/O — User I/O pin (function per design) |
| 腳位 143 | I/O — User I/O pin (function per design) |
| 腳位 144 | I/O — User I/O pin (function per design) |
| 腳位 145 | I/O — User I/O pin (function per design) |
| 腳位 146 | I/O — User I/O pin (function per design) |
| 腳位 147 | I/O — User I/O pin (function per design) |
| 腳位 148 | I/O — User I/O pin (function per design) |
| 腳位 149 | I/O — User I/O pin (function per design) |
| 腳位 150 | I/O — User I/O pin (function per design) |
| 腳位 151 | TDI — JTAG Test Data In (dedicated) |
| 腳位 152 | TMS — JTAG Test Mode Select (dedicated) |
| 腳位 153 | TCK — JTAG Test Clock (dedicated) |
| 腳位 154 | I/O — User I/O pin (function per design) |
| 腳位 155 | I/O — User I/O pin (function per design) |
| 腳位 156 | I/O — User I/O pin (function per design) |
| 腳位 157 | I/O — User I/O pin (function per design) |
| 腳位 158 | I/O — User I/O pin (function per design) |
| 腳位 159 | TDO — JTAG Test Data Out (dedicated) |
| 腳位 160 | VCC — Core + I/O supply (5 V) |
典型應用
EPM7128SQC160-15N 適用於 7 應用s: PCI / ISA Bus Glue Logic, Address Decoding & Chip-Select Generation, Power-Up Sequencing & Reset Distribution, Motor Control Peripheral Logic, Industrial PLC I/O Expansion, Legacy TTL / CMOS Logic Replacement, Embedded System Peripheral Bridging.
PCI / ISA Bus Glue Logic
The EPM7128SQC160-15N fits PCI/ISA bus glue-logic roles because its 128 macrocells provide ample AND-OR decoding capacity for chip-select generation, address decoding, and bus-cycle control. Its 15 ns tPD comfortably meets the 33 MHz PCI clock-to-output timing (minimum 30 ns cycle budget allows ~15 ns combinational delay), and the 100 user I/Os support the wide bus and interrupt/grant signals of legacy PC architectures. The non-volatile EEPROM configuration eliminates boot-PROM overhead - critical for instant-on BIOS extension ROMs and adapter cards. Compared to discrete 74LS/74FTTL gates, a single EPM7128SQC160-15N replaces dozens of packages, reducing PCB area and BOM cost while preserving deterministic, pin-locked timing.
推薦
Address Decoding & Chip-Select Generation
The EPM7128SQC160-15N is widely deployed as an address decoder in microcontroller and embedded systems. Its wide AND-OR product-term architecture can decode large address ranges - up to the full 24- or 32-bit address space - in a single device, producing chip-select strobes for memory banks, peripherals, and I/O expanders. The 15 ns propagation delay ensures chip-selects are valid before the CPU's first memory-access cycle, eliminating wait-state insertion. Non-volatile EEPROM programming means the decoding map is fixed at power-up with no bootloader overhead. Compared to discrete 74HC138/139 decoders, the CPLD approach supports custom, non-power-of-two decode regions and reduces part count.
推薦
Power-Up Sequencing & Reset Distribution
Power-up sequencing in multi-rail systems benefits from the EPM7128SQC160-15N's deterministic timing and instant-on behavior. The MAX 7000S EEPROM configuration is valid within microseconds of VCC ramp, allowing the CPLD to drive early-stage enables such as the core voltage regulator's PG (Power Good) handshakes before the main CPU resets. With 100 I/Os, it can fan out independent reset and enable signals to multiple ASICs, FPGAs, and analog rails, each gated by its own programmable time delay built from internal macrocell counters. The 5V-tolerant I/O and 3.3V/5V mixed-voltage support make it ideal for sequencing mixed-voltage boards. This usage remains common in industrial PLC backplanes and telecom line cards.
推薦
Motor Control Peripheral Logic
Industrial motor drives use the EPM7128SQC160-15N as peripheral glue between a microcontroller/DSP and the power stage. Typical functions include PWM dead-time insertion, fault-input synchronization, encoder quadrature decoding, and gate-driver enable logic - all of which require deterministic, sub-microsecond timing that the 15 ns tPD comfortably provides. The 100 user I/Os interface to multiple Hall-effect sensors, encoder channels, and isolated gate drivers, while the 5V-tolerant I/O directly accepts 5V Hall/encoder signals without level shifters. The non-volatile EEPROM configuration survives factory-programmed motor profiles that must persist across power cycles. The MAX 7000S SameFrame footprint lets designers migrate to higher-density 256-macrocell MAX 7000S parts as control complexity grows.
推薦
Industrial PLC I/O Expansion
PLC backplanes use the EPM7128SQC160-15N as a flexible I/O expansion and isolation interface between the central processor and field-side drivers. Its 100 user I/Os can scan a multi-module backplane, debounce mechanical contacts in hardware (via macrocell flip-flops), and present a clean register-mapped interface to the CPU. The EEPROM-based configuration lets OEMs re-flash I/O maps via JTAG without changing firmware, accelerating line-rebuild. The 5V-tolerant I/O tolerates noisy 24V field-side signals after simple resistive dividers. Industrial customers value the part's long lifecycle, wide operating range, and SameFrame migration path, even though the silicon is NRD.
推薦
Legacy TTL / CMOS Logic Replacement
A classic use of the EPM7128SQC160-15N is consolidating dozens of discrete 74LS/74HC/74FTTL packages into a single programmable device, simplifying PCB layout and BOM. Its 128 macrocells typically replace 20-40 SSI/MSI packages while preserving exact logic function and timing. This reduces PCB layer count, assembly cost, and test time. The 5V I/O is directly compatible with legacy TTL thresholds, eliminating level translation. This use case is especially valuable in aerospace, defense, and industrial OEMs maintaining production of legacy systems where re-spinning a board for a different CPLD family would require re-certification. The EEPROM configuration is also more reliable than soldered-in discrete logic.
推薦
Embedded System Peripheral Bridging
Bridging mismatched peripherals - for example, an 8-bit microcontroller to a 16-bit LCD bus, or a SPI master to a parallel ADC - is a natural fit for the EPM7128SQC160-15N. With 128 macrocells, the CPLD can implement protocol converters, bus-width adapters, and FIFO-like flow-control logic with deterministic timing. The 15 ns tPD easily keeps up with typical 8- and 16-bit microcontroller peripheral speeds (tens of MHz), and the 100 I/Os provide ample headroom for parallel buses. The non-volatile configuration means the bridge starts working at first power-up, even before the main CPU boots. This pattern is common in custom instrumentation and medical-device embedded boards.
推薦
推薦產品摘要
工程參考資料，適用於 EPM7128SQC160-15N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM7128SQC160-15 | EPM7128SQC160-10 | EPM7128SQC160-10N | EPM7128SQC100-15 |
|---|---|---|---|---|---|
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 10 ns | 10 ns | 15 ns |
| Lead-Free (N suffix) | Yes (N-suffix) | No (legacy leaded) | No (legacy leaded) | Yes (N-suffix) | No (legacy leaded) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
主要差異化特點
- Wide 5V-tolerant I/O with 3.3V/5V mixed-voltage support (對比MAX V CPLDs (e.g., 5M160ZE64))
- Non-volatile EEPROM configuration - instant-on at power-up (對比SRAM-based FPGAs (e.g., Cyclone))
- SameFrame pinout across density and package options (對比Discrete 74LS/74F TTL logic)
- Deterministic, pin-locked timing independent of routing density (對比ispMACH 4000 (Lattice))
設計說明
PQFP-160 packages have long lead lengths (~3 mm) and significant lead inductance. Place at least one 0.1 µF decoupling capacitor per VCC pin, within 5 mm of the package body. Use a continuous ground plane on the layer directly beneath the CPLD to control return-current paths and EMI. Avoid routing high-speed signals (>50 MHz) under the PQFP body to limit crosstalk into the device's analog substrate.
Each EPM7128SQC160-15N user I/O can source/sink up to 25 mA DC and supports 5V TTL thresholds. When driving long PCB traces or cables, add a 33 Ω series resistor near the CPLD pin to dampen ringing. Inputs from noisy buses should be filtered with a 100 ns RC network or a Schmitt-trigger input buffer. Do not exceed the absolute maximum DC input voltage of 7V; undershoot below -2V for >100 mA / >20 ns is also prohibited.
Do not confuse the speed-grade suffix: -10 / -10N are faster than -15N. Note that VCC must rise monotonically for EPM7128A / EPM7256A devices only - this constraint does NOT apply to the non-A MAX 7000S EPM7128SQC160-15N. For ISP via JTAG, ensure TCK is not floating during board power-up; tie TCK to GND through a 10 kΩ pull-down. Always re-verify the configuration after reflow because EEPROM retention is sensitive to thermal exposure above 150 °C.
The PQFP-160 package has a thermal resistance (θJA) of approximately 35-40 °C/W on a standard 4-layer PCB. The EPM7128SQC160-15N typically dissipates 0.5-1.5 W depending on toggle frequency and IO loading. Estimate: at full 76.9 MHz toggle with 100 I/Os at 20 pF each, ICC ≈ 150-300 mA and P ≈ 0.75-1.5 W, giving a junction rise of ~30-60 °C above ambient. Ensure ambient remains below 70 °C to keep Tj within the 125 °C commercial limit.
合規資訊
RoHS, REACH, halogen-free, and conflict-minerals status are not explicitly stated in the verified web data; marked unknown. The N suffix indicates lead-free build. AEC-Q100 not applicable - this is a commercial-grade CPLD, not an automotive-qualified part.
