FPGA & CPLD
Products (6,800+)
EPM570ZM144C6N - MAX II CPLD, 570 LEs, 144-MBGA | Intel (Altera)
The Intel (formerly Altera) EPM570ZM144C6N is a non-volatile MAX II family CPLD (Complex Programmable Logic Device) with 570 logic elements (equivalent to 440 macrocells), packaged in a 144-ball Micro FBGA (ZM144, 6x6 mm, 0.5 mm pitch). It is built on a 0.18 µm 6-layer-metal flash process that retains configuration without an external boot PROM and offers up to 76 user I/O pins in this 144-MBGA variant. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of classic PAL/PLA architectures with modern flash-based configuration memory. Within the broader semiconductor taxonomy, a CPLD sits alongside FPGAs in the programmable logic category, but differs by offering coarse-grained logic blocks, predictable pin-to-pin propagation, and zero configuration load time. MAX II devices occupy the low-power, low-cost end of this hierarchy, often serving as glue logic, bus bridges, and power-up state machines rather than high-density data processing. The EPM570 sits at the upper-middle density tier within the MAX II family, above EPM240 and EPM1270's smaller siblings. Key features include a 1.8 V core voltage with MultiVolt I/O support from 1.5 V to 3.3 V, an 8 Kbit user flash memory (UFM) block for non-logic data storage, in-system programmability via JTAG, and a maximum internal operating frequency quoted at 184.1 MHz with typical propagation delays in the low nanosecond range. The device supports vertical migration within the same package across the MAX II family (EPM240/EPM570/EPM1270 share footprints in several FineLine BGA variants), allowing density upgrades without PCB redesign. Typical applications include I/O expansion and bus bridging in industrial controllers, power-up sequencing logic in multi-rail systems, LCD and display interface glue logic, address decoding for microcontrollers lacking address latches, and as a low-cost alternative to small FPGAs in volume consumer products. The on-chip UFM block enables designers to store serial numbers, calibration constants, or boot parameters without an external EEPROM. When designing with this part, ensure the JTAG chain is correctly terminated and that the MultiVolt I/O bank supplies match the connected logic levels. Decoupling follows standard CPLD practice: 0.1 µF ceramic per supply pin plus a single 10 µF bulk capacitor near the package. The non-volatile flash configuration means the device becomes active within microseconds of POR, simplifying system boot sequencing compared to SRAM-based FPGAs. This page synthesizes distributor pricing, drop-in alternative MPNs within the MAX II family, and practical design notes not consolidated in the manufacturer datasheet.
EPM570ZM144C7N - 570 LEs MAX II CPLD, 144-MBGA, 7ns | Intel
The Intel (formerly Altera) EPM570ZM144C7N is a non-volatile, instant-on MAX II CPLD with 570 logic elements (440 macrocells equivalent), housed in a 144-ball FineLine BGA package. Built on a 0.18-micrometer, 6-layer-metal flash process, this device belongs to the MAX II CPLD family and operates with a 7 ns pin-to-pin logic delay (speed grade 7) at commercial temperature (0C to +85C). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL devices and FPGAs in the programmable logic hierarchy: CPLD -> programmable logic -> digital logic IC -> semiconductor. MAX II CPLDs deliver instant-on operation because their configuration is stored in on-chip flash rather than SRAM, eliminating external configuration memory and the associated boot delay. They are typically used for glue logic, bus bridging, I/O expansion, and power-up sequencing in systems that require deterministic, low-power, non-volatile logic without the cost or power of an FPGA. Key features of the EPM570ZM144C7N include 570 logic elements, 440 macrocells equivalent, 116 user I/Os (maximum), 8 Kbits of user flash memory (UFM), an internal oscillator, and JTAG (IEEE 1149.1) programming interface. The device operates from a single 3.3 V, 2.5 V, or 1.8 V core supply (multi-voltage support) and supports I/O bank voltages independent of the core supply, enabling mixed-voltage interfacing. The 144-MBGA package provides 116 usable I/Os with low parasitic inductance, well suited to high-speed signal fan-out and bus interface applications. The architecture consists of Logic Array Blocks (LABs) of 16 macrocells each, interconnected via a MultiTrack interconnect, with each macrocell containing a programmable register with a product-term-based combinatorial logic engine. The on-chip User Flash Memory (UFM) block of 8 Kbits allows user data storage such as serial numbers, calibration constants, or bootloader tables without an external EEPROM. An internal oscillator supports common baud-rate generation and timer functions. Typical applications include I/O expansion and bus bridging in industrial controllers, power-up and power-down sequencing in multi-rail systems, glue logic for microcontrollers and ASICs, LED driving and display multiplexing, and protocol bridging (UART, I2C, SPI) for legacy or distributed architectures. The instant-on non-volatile configuration is particularly valuable in safety-critical and industrial applications where deterministic startup is required. When designing with the EPM570Z (MAX II Z) variant, note that the Z-license enables JTAG-based ISP but the UFM block is not present in all MAX II sub-families - verify the specific feature set against the device handbook. Power consumption is dominated by static Icc; a fully-loaded design with many toggling outputs should be validated against the Icc vs. frequency curves in the datasheet. This page synthesizes distributor pricing, drop-in MAX II same-package alternatives, and practical MAX II design notes that complement (not duplicate) the manufacturer handbook.
EPM570ZM144I8N - 440 Macrocell CPLD MAX II Z 152MHz | Intel
The Intel (formerly Altera) EPM570ZM144I8N is a high-density, non-volatile MAX II Z family Complex Programmable Logic Device (CPLD) delivering 440 macrocells with 116 user I/Os in a 144-pin Micro FBGA (MBGA) package. The device operates from a 1.8 V core supply and supports toggle frequencies up to 152 MHz with a pin-to-pin logic delay of approximately 9.0 ns, manufactured on a 0.18 µm process node. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash-based programmable logic IC that combines the instant-on behavior of a PAL/GAL with the density of a small FPGA. It sits between discrete 74-series glue logic and full FPGAs in the system hierarchy: glue logic -> SPLD -> CPLD -> FPGA -> ASIC. MAX II Z devices use a look-up table (LUT) based logic array plus a non-volatile flash configuration cell, giving them instant-on capability without external boot PROMs and excellent deterministic timing for bus-interface, address-decoding, and I/O-expansion tasks. Key features of the EPM570ZM144I8N include 570 logic elements organized as 57 Logic Array Blocks (LABs) of 10 macrocells each, 8 Kbits of user flash memory (UFM), JTAG (IEEE 1149.1) and Altera built-in ISP via the JTAG interface, MultiVolt core and I/O support allowing mixing of 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfaces, and four enhanced I/O banks. The I8N industrial temperature grade covers -40 °C to +85 °C operation, and the zero-power (Z) flash cell removes the need for a configuration download at every power-up. Architecturally, the EPM570Z is built around a fine-grained Logic Element (LE) array with carry chains for fast arithmetic, an interconnect network with predictable delay paths, and a global control block driving four clock inputs with programmable polarity. The flash-based configuration is in-system programmable (ISP) and re-programmable up to 100 cycles per sector, which is sufficient for board-level prototyping and small production runs. Typical applications include bus-interface bridging (PCI, ISA, VME legacy glue), address decoding and I/O expansion in microcontroller-based systems, power-up sequencing and supervisor logic, LED drive multiplexing, JTAG chain aggregation, and low-density state-machine replacement. Designers also use the EPM570Z as a feature-enhancement companion to an ASIC or MCU that lacks specific peripherals. When designing with the EPM570ZM144I8N, observe Micro FBGA routing rules — pitch is 1.0 mm and the device requires a 4-layer PCB with via-in-pad or micro-via escape patterns to fan out the 144 ball grid. Reserve at least 1 Gnd and 1 Vcc reference ball per quadrant and use the dedicated JTAG TCK/TMS/TDI/TDO pins for boundary-scan test. Quiescent current is approximately 35 mA at 1.8 V; total power scales with toggle rate and I/O loading. This page synthesizes verified distributor pricing, drop-in same-package alternatives, and practical design notes that complement the Altera/Intel MAX II Z datasheet with information gain not available from any single source.
EPM570ZM256C6N - MAX II 570 LE CPLD, 256-MBGA | Altera (Intel)
The Altera (Intel) EPM570ZM256C6N is a MAX II family instant-on, non-volatile Complex Programmable Logic Device (CPLD) housed in a 256-ball FineLine BGA (MBGA) package measuring 11x11 mm. The device delivers 570 Logic Elements (LEs), 440 macrocells, 160 user I/Os, and 8 Kbits of user flash memory, fabricated on a 0.18-micron, 6-layer-metal flash process for low static power and instant-on configurability. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines AND/OR-array macrocell architecture with on-chip flash configuration memory. CPLDs sit between discrete 74-series glue logic and small FPGAs in the broader hierarchy of programmable logic, offering deterministic propagation delays, single-chip instant-on boot, and high I/O count at low unit cost. The MAX II family is widely deployed as "glue logic," bus-interface bridges, and I/O expander replacements for ASIC and ASSP functions in cost-sensitive industrial, consumer, and communications designs. Key features of the EPM570ZM256C6N include 5.5 ns pin-to-pin logic delay (commercial speed grade -6), MultiVolt core supporting 1.8 V, 2.5 V, 3.3 V I/O standards, in-system programmability via JTAG, and operation across 0C to +85C commercial temperature. Internal core voltage is 1.71 V to 1.89 V (1.8 V typical), while I/O banks accept 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V inputs with 5.0 V-tolerant I/Os. The device also integrates 8 Kbits of user flash that designers can partition between configuration and general-purpose non-volatile storage. Architecture combines a high-performance, low-power CMOS process with the non-volatile Flash memory block, eliminating external configuration PROM and offering live-at-power-up behavior. The 160 user I/Os in a 256-MBGA footprint enable dense board integration where TQFP-144 or QFP-100 packages cannot deliver sufficient I/O count. Designers benefit from deterministic timing suited to control-plane and bus-interface applications rather than DSP or high-speed datapath workloads. Typical applications include I/O expansion and bus bridging for microcontrollers, glue logic replacement in industrial control boards, LED display control, multi-rail power-sequencing networks, telecommunications line-card interface glue, and consumer-electronics peripheral hubs. The wide I/O voltage range allows direct interfacing to legacy 5 V peripherals alongside modern 1.8 V SoCs. When designing with the EPM570ZM256C6N, remember that the MBGA package requires X-ray or rework-station inspection for prototypes and BGA-qualified PCB assembly lines for production. Provide decoupling of 0.1 microfarad and 10 microfarad capacitors near each VCCIO bank, and ensure JTAG chain access for in-system programming. Use Quartus II Web Edition (or Quartus Prime Lite) for design entry, synthesis, and place-and-route. This page synthesizes distributor pricing, drop-in alternatives from the MAX II vertical-migration family, and practical design notes not found in the manufacturer datasheet alone.
EPM570ZM256C7N - 570 LE MAX II Z CPLD, 256-ball MBGA | Altera
The Altera (now Intel) EPM570ZM256C7N is a MAX II Z family zero-power CPLD that delivers 570 Logic Elements (LEs) and 76 user I/Os in a 256-ball Micro BGA package, fabricated on a 0.18 µm CMOS process. It supports a core supply of 1.71 V to 1.89 V with on-chip voltage regulation, and operates at commercial temperature grade 0 °C to +85 °C. The device provides 440 macro cells and an internal maximum operating frequency of 123.5 MHz, making it well-suited for glue-logic, I/O expansion, and bus-bridging roles in cost-sensitive systems. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic IC that combines multiple PAL-like macro cell blocks connected by a programmable interconnect matrix. Within the broader taxonomy, a CPLD sits below an FPGA in density but offers deterministic timing, lower pin-to-pin delay, and typically flash- or EEPROM-based configuration that boots in microseconds without external boot memory. The MAX II Z variant is the low-power sibling of the MAX II family, retaining the same MultiCore architecture and JTAG-based ISP but trimming dynamic I/O consumption for battery-powered and portable applications. Key features include 8 Kbits of user flash memory, 5.0 ns pin-to-pin logic delay, MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V mixed-voltage interfacing, JTAG 1149.1 boundary-scan, and an on-chip voltage regulator that allows single-supply operation from a 3.3 V rail. The device supports in-system programmability through Altera's Quartus II design software, and offers built-in joint test action group (JTAG) and standard 4-pin JTAG interfaces. Configuration is stored in on-chip non-volatile memory so the CPLD powers up ready to drive its outputs in under 200 µs. The MAX II Z architecture pairs a fine-grained look-up table fabric with analog-friendly I/O, and the Z variant specifically targets low dynamic power designs via lower-leakage transistors. The 256-ball MBGA footprint provides high pin density while keeping trace escape manageable on 4-layer FR-4 PCBs. Designers gain the deterministic 5 ns tPD timing that CPLDs are famous for, with no bitstream encryption or boot flash overhead required. Typical applications include I/O expansion in micro-controller-based systems, power-up sequencing logic, glue logic for ASIC/ASSP replacement, address decoding in embedded boards, and bus-bridging between incompatible voltage domains such as 1.8 V FPGA banks and 3.3 V peripheral buses. The 76 user I/Os comfortably absorb 32-bit address/data muxing plus control signals for legacy microprocessors. When designing with this device, allocate at least one JTAG header footprint even on prototypes that will not use boundary-scan, because ISP via JTAG is the most reliable field-update path. Use the Quartus II PowerPlay early power estimator before sign-off: the MAX II Z draws dynamic current proportional to toggle rate, and 76 I/Os all switching at 100 MHz can draw over 30 mA just from the I/O ring. This page synthesizes distributor pricing, same-brand drop-in alternatives from the Altera MAX II family, and practical MAX II design notes not collected in the original datasheet front matter.
EPM570ZM256I8N - MAX II 440 Macrocell CPLD, 256-MBGA | Intel
The Intel (formerly Altera) EPM570ZM256I8N is a non-volatile, instant-on MAX II family Complex Programmable Logic Device (CPLD) with 440 macrocells (570 logic elements), 118.3 MHz maximum internal frequency, and 1.71 V to 1.89 V core supply, housed in a 256-ball Micro FBGA (11 mm x 11 mm) package. The device integrates 8 Kbits of user flash memory for non-volatile configuration, eliminating the need for an external boot PROM and enabling instant-on behavior within microseconds of power-up. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays with a central interconnect matrix. CPLDs sit between small discrete logic gates (74-series) and larger FPGAs in the programmable logic hierarchy. Within that hierarchy, the MAX II family is positioned as the lowest-power, lowest-cost instant-on tier from Intel/Altera, optimized for glue logic, I/O expansion, bus bridging, and power-sequencing tasks rather than DSP-intensive workloads. The 'Z' suffix denotes the zero-power (ultra-low static current) variant, which uses a 1.8 V internal core supply and is intended for battery- and thermally-constrained designs. Key features include in-system programmability via IEEE 1149.1 JTAG, MultiVolt I/O supporting 1.5 V / 1.8 V / 2.5 V / 3.3 V interfaces on the same die, four global clock networks with eight clocks per logic array block, and a 1.6 Kbit user flash memory block. The 256-MBGA package exposes 212 user I/O pins, supporting high-density I/O expansion in a compact 11 mm x 11 mm footprint. Internally, the EPM570Z uses a 0.18 micrometer, 6-layer-metal flash process and a non-volatile configuration cell, which keeps the device permanently configured without external boot storage. Each Logic Array Block (LAB) contains 16 macrocells, and the central interconnect matrix routes signals across LABs with predictable, deterministic timing that simplifies static-timing closure compared with SRAM-based FPGAs. Typical applications include I/O expansion for microcontrollers, voltage-level translation between mismatched logic domains, power-supply sequencing and supervisory logic, glue logic replacement for discrete 74-series gates, bus-interface bridging (for example, SPI-to-Parallel or I2C-to-GPIO expansion), and LED driving or keypad scanning in industrial and consumer products. Designers also use the EPM570Z as a companion CPLD to an FPGA, offloading boot configuration, clock conditioning, and reset distribution. When designing with this device, budget for the 1.71 V to 1.89 V core supply rail (typically derived from a 3.3 V LDO) and respect the JTAG chain requirements if multiple devices share the same TMS/TCK lines. The MultiVolt I/O banks allow direct connection to 3.3 V, 2.5 V, 1.8 V, or 1.5 V domains without external level shifters, but unused I/O pins should be configured as outputs driving low or tri-stated with weak pull-up to minimize in-rush current. This page synthesizes distributor pricing, drop-in alternative MPNs from the same MAX II Z family, and practical design notes not collected in the manufacturer datasheet alone.
EPM7032LC44-15 - MAX 7000 CPLD, 32 Macrocells, 15ns | Altera
The Altera EPM7032LC44-15 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, delivering 600 usable gates and 32 macrocells in a 44-pin PLCC package with 15 ns pin-to-pin logic delay. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a global interconnect fabric. CPLDs belong to the broader family of programmable logic devices, sitting alongside FPGAs in the digital IC hierarchy: programmable logic -> programmable logic device -> CPLD/FPGA -> logic IC -> integrated circuit. MAX 7000 devices use a second-generation MAX architecture with 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, enabling designers to program, verify, and re-program the device on the board without removing it. Key features of the EPM7032LC44-15 include 32 macrocells, 36 user I/O pins, 600 gates of logic capacity, 15 ns tPD (pin-to-pin delay), and a maximum internal operating frequency of 76.9 MHz. The device operates from a single 5.0 V supply (with VCCIO supporting 5.0 V or 3.3 V outputs) and is housed in a 44-pin PLCC package suitable for through-hole mounting and socket-based prototyping. The MAX architecture uses a classic EEPROM-based non-volatile technology, providing instant-on behavior at power-up with no external configuration memory required. The 15 ns speed grade makes the LC44-15 suitable for control logic, address decoding, bus interfacing, and glue-logic integration where deterministic propagation delay and high I/O count are required. The PLCC-44 footprint is widely supported by low-cost sockets, simplifying field upgrades and legacy-system retrofits. Typical applications include address decoding and bus interfacing in industrial control systems, glue-logic replacement in legacy 5V designs, I/O expansion for microcontrollers, and state-machine implementation in test & measurement equipment. Designers select the -15 speed grade when balancing timing margin against cost in non-critical control paths. When designing with this device, ensure the VCC and VCCIO rails match the system logic levels. PLCC-44 sockets should be used for prototyping to allow easy device swap during development. Note that MAX 7000 devices have been classified by Altera/Intel as mature legacy products, so designers should verify long-term availability before new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for evaluating the EPM7032LC44-15 against modern CPLD options.
EPM7064SLC44-10N - MAX 7000 64-Macro 36 I/O 10ns CPLD | Altera
The Altera (now Intel) EPM7064SLC44-10N is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, featuring 64 macro cells, 36 user I/Os, a 10 ns pin-to-pin propagation delay, and a 44-pin PLCC package. Built on Altera's second-generation Multiple Array MatriX (MAX) architecture, the device delivers 1,250 usable gates and supports in-system programmability (ISP) via the IEEE-Standard 1149.1 (JTAG) interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macro-cell logic blocks on a single die, connected through a programmable interconnect matrix. CPLDs sit in the hierarchy between simple PLDs (PALs/GALs) and FPGAs, offering deterministic, near-zero-power standby, instant-on configuration, and predictable timing — making them ideal for glue logic, bus interfacing, and control applications where FPGAs would be over-spec and PALs would lack capacity. Key features include 5V CMOS core operation, four dedicated input pins that also serve as global clock/clear/Output Enable resources, programmable macro-cell flip-flops with individual clear, preset, clock, and enable control, and an extended IEEE-Standard 1149.1 boundary-scan test interface. Each user I/O can be configured per-pin for 3.3V or 5V PCI-compliant drive strength. The non-volatile EEPROM configuration cell means the device powers up instantly with no external boot PROM required. Architecturally, the EPM7064SLC44-10N partitions its 64 macro cells into four Logic Array Blocks (LABs), each containing 16 macro cells, with a programmable interconnect array (PIA) that routes any signal to any destination. The 10 ns tPD (with the -10 speed grade suffix) supports counter frequencies up to 125 MHz, while higher-density MAX 7000A/S/AE variants in the same family scale to 256 macro cells and 5 ns timing. Typical applications include bus decoding and address mapping in legacy 8051/68k designs, glue-logic integration for DSP/microprocessor systems, peripheral control (UART, SCSI, ISA bridge), state-machine implementation, and PCI bus interface glue. The wide 5V tolerance and 36 I/Os also suit industrial motor-control and instrumentation front ends. When designing with this device, observe the 5V ±5% supply requirement, place a 0.1 µF decoupling capacitor close to each VCC/GND pair on the PLCC-44 footprint, and configure unused I/Os as outputs driving low to minimize power consumption. The JTAG chain should be bypassed with TCK held low during normal operation if boundary-scan is unused.
EPM7096LC68-15 - MAX 7000 CPLD, 96 Macrocells, 15ns | Altera
The Altera EPM7096LC68-15 is a member of the classic MAX 7000 family of high-performance, EEPROM-based Complex Programmable Logic Devices (CPLDs), delivering 96 macrocells in a 68-pin PLCC package with a 15 ns pin-to-pin logic delay. Built on a second-generation MAX architecture, this device provides 5.0V in-system programmability (ISP) through its built-in IEEE Std. 1149.1 JTAG interface, enabling rapid prototyping and field upgrades without removing the part from the board. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that sits between simple SPLDs and large FPGAs in the programmable logic hierarchy. It contains multiple logic array blocks (LABs) interconnected by a programmable switch matrix, retaining its configuration in on-chip EEPROM without needing a separate boot memory. CPLDs are widely used for glue logic, bus interfacing, address decoding, state machines, and power-up control because of their deterministic timing, instant-on behavior, and robust non-volatile storage. Key features of the EPM7096LC68-15 include 96 macrocells, 4 logic array blocks (LABs), and 52 user I/O pins for flexible signal routing. The device operates from a 4.75 V to 5.25 V supply, supports the standard 5V TTL interface levels, and offers a 15 ns maximum propagation delay that suits moderate-speed control logic. Its high-performance EEPROM technology delivers 100 erase/program cycles per macrocell and supports in-system programming through JTAG or via Altera's ByteBlaster/ByteBlasterMV download cables. The MAX 7000 architecture separates combinational and registered logic, with each macrocell containing a programmable AND/OR array and a configurable flip-flop. This design gives predictable timing paths and makes the EPM7096LC68-15 particularly attractive for asynchronous and registered state-machine designs. The device is also highly tolerant of 5V mixed-signal environments, which is why it remains common in legacy industrial, telecommunications, and test equipment designs. Typical applications include bus interfacing and protocol bridging, address decoding for microprocessors, state-machine controllers, glue logic replacement for discrete 74-series TTL, and I/O expansion. Designers also use the EPM7096LC68-15 for power-up sequencing logic because its non-volatile EEPROM boots in a deterministic state without an external configuration device. When designing with this CPLD, account for the 5V supply requirement and provide proper decoupling on every VCC pin. The PLCC-68 package is socket-compatible with several EPM7128 variants, allowing a path to higher macrocell density without reworking the PCB footprint. This page synthesizes distributor inventory, drop-in alternatives, and practical design notes not found in the bare manufacturer datasheet, making it a faster reference for engineers evaluating, sourcing, or replacing the EPM7096LC68-15.
EPM7096LC68-7 - 96-Macrocell MAX 7000 CPLD, 7.5ns | Intel
The Intel EPM7096LC68-7 is a high-density, EEPROM-based Complex Programmable Logic Device (CPLD) from the legacy MAX 7000 family, packaged in a 68-pin J-Lead PLCC (LC68). The part integrates 96 macrocells organized into 4 Logic Array Blocks (LABs) with 52 user I/O pins, and offers a worst-case pin-to-pin propagation delay of 7.5 ns. Operating from a 5.0 V supply, this device targets glue-logic, bus-interface bridging, and state-machine consolidation in industrial, telecom, and embedded control designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the broader programmable logic hierarchy between simple SPLDs (like GAL/PAL) and high-capacity FPGAs. CPLDs use EEPROM or flash cells to retain configuration, provide deterministic timing with predictable pin-to-pin delays, and typically contain hundreds of macrocells grouped into LABs interconnected by a programmable interconnect matrix (PIA). They are commonly chosen for applications needing instant-on behavior, robust I/O driving capability, and small-form-factor logic integration at low power. Within the programmable logic taxonomy, the MAX 7000 family sits as one of the longest-lived mainstream 5 V EEPROM CPLD lines introduced by Altera (now Intel). Key features of the EPM7096LC68-7 include 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, a maximum toggle frequency that supports common bus-interface speeds, six dedicated global clock pins, and a programmable power-saving mode that reduces quiescent current on unused macrocells. Each macrocell contains a programmable AND/OR array with a flip-flop, providing both combinational and registered logic in a single architectural unit. The LC68 (PLCC-68 J-lead) package is socket-compatible across the MAX 7000 series, enabling board reuse between density variants. Architecturally, the MAX 7000 uses a second-generation MAX architecture with enhanced interconnect routing and per-macrocell product-term allocation. The four LABs share a Programmable Interconnect Array (PIA) that routes any LAB output to any other LAB input, removing routing bottlenecks common to older PLD families. Combined with the 52 I/O pins, the device delivers sufficient logic density for 16-/32-bit bus decoding, address-latch multiplexing, and peripheral control blocks in legacy 5 V systems. Typical applications include 5 V ISA bus decoding, industrial PLC I/O expansion, peripheral glue logic in telecom line cards, address/data multiplexing for microprocessors without integrated peripherals, and pin-compatible board upgrades from smaller MAX 7000 devices (EPM7032, EPM7064, EPM7128). The part is widely used for new designs targeting legacy 5 V rails and for long-lifecycle industrial equipment maintenance where firmware-updateable logic simplifies field upgrades. When designing with this part, allow at least one 0.1 uF decoupling capacitor per VCC/GND pair, place the JTAG TMS/TCK/TDO/TDI chain with proper pull-ups, and verify the device programming file (POF/JEDEC) targets the correct speed grade (-7 = 7.5 ns tPD). Note that EPM7096LC68-7 is generally considered a legacy/NRND device; engineers should confirm long-term availability before new design-in.
EPM7096LC84-10 - 96-Macrocell MAX 7000 CPLD, 10ns, 84-PLCC | Intel
The Intel (formerly Altera) EPM7096LC84-10 is a 96-macrocell, 84-pin PLCC member of the MAX 7000 family of high-performance, EEPROM-based Complex Programmable Logic Devices (CPLDs). Built on the second-generation MAX architecture, this device provides 4 Logic Array Blocks (LABs), 96 macrocells, and 36 usable I/O pins, with a pin-to-pin propagation delay (tPD) of 10 ns for the -10 speed grade. The 'L' suffix indicates a low-power CMOS process variant, and 'C' indicates the commercial 0C to +70C operating range. A Complex Programmable Logic Device (CPLD) is a non-volatile, reprogrammable digital integrated circuit that sits hierarchically between simple SPLDs/GALs and full FPGAs. Within the broader taxonomy, CPLDs fall under programmable logic devices (PLDs), which sit under digital logic ICs, which in turn belong to the integrated circuit (semiconductor) family. CPLDs are valued for their deterministic timing, instant-on EEPROM configuration, and predictable I/O behavior, making them well suited to glue-logic, bus-interface, and control-plane tasks in mixed-signal systems. The EPM7096LC84-10 features 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It supports MultiVolt I/O for interfacing with 2.5-V, 3.3-V, and 5.0-V logic on the same die, and provides programmable macrocell flip-flops with selectable D, T, JK, or SR operation. The shared programmable interconnect array (PIA) routes signals between LABs, and each macrocell includes a product-term-based logic array, a programmable register, and a tri-state output buffer for bidirectional I/O. Typical applications of the EPM7096LC84-10 include address decoding and bus-interface glue logic in 5-V microcontrollers and DSP systems, peripheral control for printers and legacy industrial controllers, state-machine-driven I/O expansion, JTAG-boundary-scan test access, and replacement of multiple discrete 74LS/74HC TTL gates to reduce board area. Because the MAX 7000 uses EEPROM cells, designs retain their configuration through power cycles with no external boot PROM. When designing with this device, ensure that VCC stays within the 4.75 V to 5.25 V commercial range, that JTAG signals TDI/TMS/TCK/TDO are pulled to a defined logic level when not in use, and that I/O rise/fall times are accounted for in timing closure - the shared PIA structure means worst-case tPD is identical for any internal path. For new designs, evaluate MAX II or MAX V modern low-power equivalents, which consume less quiescent current and offer smaller packages while maintaining 5-V tolerant I/O. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone - use it alongside the official MAX 7000 datasheet from Intel.
EPM7096LC84-15 - 96 Macrocell, 15ns CPLD MAX 7000 | Intel / Altera
The Intel / Altera (formerly Altera) EPM7096LC84-15 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, featuring 96 macrocells, 1,800 usable gates, and a 15 ns pin-to-pin propagation delay, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It supports 5.0V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, operates from a 4.75V to 5.25V internal supply, and is rated for the commercial 0C to 70C temperature range. The device integrates four Logic Array Blocks (LABs) connected via a programmable interconnect array (PIA), giving designers 68 usable I/O pins with 5V-tolerant inputs. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip, connected by a central interconnect matrix. In the broader taxonomy, CPLDs sit between simple SPLDs (like PALs/GALs) and high-density FPGAs, offering deterministic timing, instant-on non-volatile configuration, and modest logic densities (hundreds to a few thousand macrocells). CPLDs are widely used as glue logic, interface bridges, and high-speed control state machines where FPGAs would be over-spec or cost-prohibitive. The EPM7096LC84-15's key differentiating specifications include 76.9 MHz maximum operating frequency, 10 ns logic-array-block propagation delay, 36 user-available I/O pins per LAB, and built-in JTAG boundary-scan support compliant with IEEE 1149.1. The second-generation MAX architecture combines EEPROM cells with CMOS logic, providing 100% tested programming yield, 100 erase/program cycles endurance, and data retention exceeding 10 years. Architecturally, the device uses a CMOS EEPROM process with a 5V core supply, dual-sense-amplifier configurable macrocells, and a global interconnect array with predictable routing delay independent of logic placement. This deterministic timing behavior is a hallmark of CPLDs and is often cited as the reason designers choose MAX 7000 over a small FPGA for control-path glue logic. Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microcontroller to 32-bit bus), high-speed address decoding, state-machine based motor and actuator control, peripheral expansion for legacy designs, and JTAG-controlled glue logic in telecom and industrial backplanes. When designing with this part, note that the 5V VCC must rise monotonically during power-up to ensure proper configuration. Designers should also budget 100 erase/program cycle endurance and avoid continuous in-system reprogramming in field-deployed systems. This page synthesizes distributor pricing, drop-in alternatives within the MAX 7000 family, and practical design considerations not found in a single manufacturer datasheet, giving engineers and procurement teams a consolidated view for sourcing and design-in decisions.
EPM7096LC84-7 - 96-Macrocell MAX 7000 CPLD, 7.5ns, PLCC-84 | Intel
The Intel (formerly Altera) EPM7096LC84-7 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, packaged in an 84-pin Plastic Leaded Chip Carrier (PLCC-84) and offering 96 macrocells with 64 user I/O pins and a 7.5 ns pin-to-pin logic delay. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits hierarchically between simple SPLDs/PALs and larger FPGAs in the programmable logic taxonomy: SPLD -> CPLD -> FPGA -> programmable logic -> digital IC. CPLDs are characterized by deterministic timing, instant-on behavior (no boot load), and on-chip non-volatile configuration memory, which makes them ideal for glue-logic, bus interfacing, and control applications where predictable timing and zero-boot-delay operation are required. Key features of the EPM7096LC84-7 include 96 macrocells organized in 4 Logic Array Blocks (LABs), 64 user I/O pins, a 7.5 ns tPD (pin-to-pin logic delay) corresponding to the speed grade -7, and 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. The device operates from a single 5.0 V supply (VCCINT/VCCIO combined for the LC family) and supports commercial temperature ranges. Pin-compatibility across the MAX 7000 family allows migration between EPM7064, EPM7096, and higher densities within the same 84-pin PLCC footprint. The MAX 7000 architecture is built on EEPROM non-volatile cells with a second-generation MAX architecture, providing five-pin programmable logic delays, programmable flip-flops with individual clear, preset, clock, and clock-enable controls, and a programmable interconnect array (PIA) that routes signals between LABs. This gives deterministic, simulation-matched timing for asynchronous state machines and address decoding. Typical applications include bus address decoding, peripheral glue logic, interface bridging between microcontrollers and legacy peripherals, asynchronous state machines, and board-level reset/power-sequencing controllers in industrial, telecom, and embedded computing systems. The wide 5V tolerance and instant-on behavior are particularly valued in 5V legacy industrial backplanes. When designing with this part, ensure the JTAG chain (TCK, TMS, TDI, TDO) is correctly terminated and that the I/O banks are powered simultaneously to avoid latch-up. The 7.5 ns speed grade is the slowest in the MAX 7000 family at this density - if your design requires faster decode paths, consider the EPM7096LC84-10 or EPM7096LC84-15 speed grades (drop-in, faster). This page synthesizes distributor pricing, drop-in same-footprint alternatives (including faster speed grades from the Site MPN list), and practical design notes for glue-logic and 5V-system migration not collected on any single distributor page.
EPM7096LI68-15 - 96-Macrocell MAX 7000 CPLD, 15ns, PLCC-68
The Altera (Intel) EPM7096LI68-15 is a high-density, EEPROM-based CMOS CPLD from the second-generation MAX 7000 family, providing 96 macrocells organized into 4 logic array blocks (LABs) and offering 52 user I/O pins in a 68-pin PLCC (J-lead) package with industrial temperature grade (-40C to +85C) and a 15ns pin-to-pin propagation delay. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL devices with much higher macrocell density and deterministic timing. CPLDs occupy the middle tier of programmable logic hierarchy - below FPGAs in raw density but above simple SPLDs/PALs - and are commonly classified within the broader category of programmable logic devices (PLDs) and digital semiconductors. The MAX 7000 family uses a classic EEPROM-based architecture, meaning configuration is retained without external memory and the device is in-system programmable (ISP) through a built-in IEEE 1149.1 JTAG interface. Key features of the EPM7096LI68-15 include 96 macrocells, 4 logic array blocks, 52 I/O pins, 15ns combinatorial propagation delay, 5.0V in-system programmability via JTAG, open-drain output option, and built-in JTAG boundary-scan test (BST) circuitry. Each macrocell provides a programmable register with dedicated product-term logic, supporting classic sum-of-products glue-logic applications. The device operates from a single 5V supply and supports both 3.3V and 5.0V I/O standards when used with the appropriate configuration. From a technical depth perspective, the MAX 7000 architecture uses a global interconnect that routes every LAB signal to every other LAB through a single fast connective path. Each LAB contains 16 macrocells and an I/O block. The 'L' suffix indicates the low-power variant and the 'I' suffix denotes industrial temperature grade. The -15 speed grade sets tPD (pin-to-pin) at 15ns, suitable for 33 MHz-66 MHz state-machine and decoder-style glue logic. Typical applications include bus interface bridging, address decoding, state-machine control, peripheral glue logic in microcontroller/ASIC systems, and legacy industrial control replacement. The JTAG ISP capability makes board-level upgrades and field reprogramming practical without removing the device from the circuit. When designing with the EPM7096LI68-15, observe PLCC-68 PCB layout guidelines including proper land pattern per JEDEC MS-018, decoupling capacitor placement near VCC pins, and JTAG chain integration if multiple devices share the same boundary-scan test port. Note that this part is now in legacy/end-of-life status - check Intel FPGA product lifecycle notices before new designs. This page synthesizes distributor inventory, same-family pin-compatible alternatives, JTAG programming guidance, and glue-logic design notes not consolidated in the original Altera datasheet - offering a single reference for engineers maintaining installed-base systems.
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
The Altera EPM7096QC100-10 is a 96-macrocell high-performance CMOS CPLD from the MAX 7000 family, featuring 4 Logic Array Blocks, 76 user I/O pins, and a 10ns pin-to-pin propagation delay, housed in a 100-pin Plastic Quad Flat Pack (PQFP-100) package. It is an EEPROM-based programmable logic device built on Altera's second-generation MAX architecture, with 5.0V in-system programmability (ISP) available through the built-in IEEE Std. 1149.1 JTAG interface on MAX 7000S variants, and operates from a single 5V supply (4.75V–5.25V) over the commercial 0°C to 70°C range. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on characteristics of PAL/GAL architectures with higher macrocell density and deterministic timing. Within the broader taxonomy, the CPLD belongs to programmable logic devices, sits alongside FPGAs as the two main branches of digital programmable logic, and ultimately falls under the semiconductor and integrated circuit hierarchy. The MAX 7000 series was Altera's mainstream 5V CPLD family widely adopted for bus interface glue logic, address decoding, state-machine control, and peripheral bridging before 3.3V FPGAs became dominant. Key specifications include 96 macrocells, 4 Logic Array Blocks, 76 available I/O pins, 10ns tPD (pin-to-pin delay), 100 MHz maximum operating frequency, and 5V VCC. The device supports JTAG boundary-scan test per IEEE 1149.1 and is PCI-compliant in the -10 speed grade. The PQFP-100 (Plastic Quad Flat Pack, 20×14 mm, 0.65mm pitch) gives a robust through-hole-compatible footprint and is one of the most widely supported legacy CPLD packages on long-lifecycle industrial designs. Typical applications include ISA/PCI bus decoding, peripheral glue logic, address decoding, state-machine control, and reconfigurable I/O expansion in industrial control, telecom, and embedded systems. When designing with this part, note that the MAX 7000 (non-S) variant uses a parallel programming interface; for ISP via JTAG, verify the exact device suffix against the datasheet. The PQFP-100 footprint requires a fine-pitch PCB land pattern; ensure adequate thermal relief for the exposed die pad and follow JEDEC J-STD-020 MSL handling for any programming or rework steps.
EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera
The Altera (Intel) EPM7096QC100-7 is a member of the classic MAX 7000 family of Complex Programmable Logic Devices (CPLDs) featuring 96 macrocells, 76 user I/Os, and a 7.5 ns pin-to-pin propagation delay, housed in a 100-pin Plastic Quad Flat Pack (PQFP-100) measuring 20x14 mm. It operates from a single 5 V supply and is built on EEPROM-based logic fabric that is in-system programmable through the Altera ByteBlaster or JTAG interfaces. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip with a central interconnect. It sits in the programmable-logic taxonomy below FPGAs in density and above discrete 22V10-style PALs in integration. The MAX 7000 family was historically the most widely deployed 5 V CPLD family and remains in long-life-cycle industrial and military programs because of its deterministic timing and 100% pin-to-pin compatibility across speed grades. The EPM7096QC100-7 delivers 7.5 ns tPD, 125 MHz fMAX, and 76 I/O pins suitable for bus interfacing, address decoding, and state-machine glue logic. It supports in-system programmability (ISP) via JTAG, has user I/O with 5 V tolerance, and offers programmable pull-up resistors, open-drain outputs, and JTAG boundary-scan support. The device provides four dedicated inputs and one global clear, plus pin-compatible migration paths to other speed grades. Architecturally, the MAX 7000 fabric combines Logic Array Blocks (LABs), each with 16 macrocells fed by a programmable AND/OR plane, with a Programmable Interconnect Array (PIA). The EEPROM cell technology ensures zero standby power and instant-on operation, removing the boot-PROM needed by SRAM-based FPGAs. Macrocells include a product-term expander and a programmable flip-flop for registered logic. Typical applications include legacy glue-logic replacement, 5 V system address decoding, bus interface bridges (e.g., ISA, PCI), industrial control boards, and military/avionics upgrades where the MAX 7000 has long been qualified. The EPM7096QC100-7 is also used as a configuration clock generator and power-sequencer in mixed-logic designs. When designing with this device, note that the 7.5 ns speed grade is the second-fastest in the family; a slower 10 ns variant (EPM7096QC100-10) is pin-compatible for cost-sensitive or less timing-critical paths. Always verify signal integrity and I/O bank compatibility when migrating from older MAX 7000 designs to MAX II or MAX V families, as those are 3.3 V core devices. This page synthesizes distributor pricing, lifecycle context, drop-in compatible speed grades, and practical glue-logic design notes that go beyond the raw MAX 7000 datasheet, helping engineers shorten sourcing time and avoid PCB rework.
EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera
The Altera EPM7096QI100-15 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, providing 96 macrocells, 76 user I/O pins, and a 15 ns pin-to-pin propagation delay in a 100-pin BQFP (Plastic Quad Flat Pack) surface-mount package. The device integrates 1,800 usable gates across 4 Logic Array Blocks (LABs) and operates from a single 4.5 V to 5.5 V supply with 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL devices with much higher density. CPLDs sit in the broader taxonomy of programmable logic devices alongside FPGAs, but offer deterministic timing, instant-on operation, and single-chip non-volatile configuration - making them ideal for glue logic, bus interfacing, and state-machine control. The MAX 7000 series is Altera's (now Intel) classic second-generation EEPROM-based CPLD line, optimized for 5 V systems. Key features of the EPM7096QI100-15 include 96 macrocells organized into 4 LABs, 76 user I/O, a 15 ns maximum pin-to-pin delay (tPD), and a global clock network with multiple product-term clock options. Each macrocell provides a programmable register with configurable D, T, JK, or SR flip-flop operation, plus product-term or array-clock selection. The JTAG-compliant ISP interface allows field re-programming without removing the device from the board, a major advantage over one-time-programmable (OTP) competitors in legacy 5 V designs. The EPM7096QI100-15 uses a second-generation MAX architecture featuring a programmable AND/OR/lookup-array fabric with fast input-to-output combinational paths. The -15 speed grade targets applications where 15 ns tPD is sufficient, while the commercial operating range of 0C to +70C makes it suitable for indoor industrial and commercial equipment. SameFrame pin-out migration allows reuse of the same PCB layout for other MAX 7000 device densities and packages. Typical applications include bus decoding and address mapping in 5 V microcontroller systems, peripheral interfacing (UART, FIFO, memory controllers), state-machine control, and legacy glue-logic replacement for discrete 74-series TTL. The wide 5 V tolerance makes the EPM7096QI100-15 a direct drop-in for systems that already use 74LS/74HC logic. When designing with this device, ensure all I/O voltages match VCC (5 V) and provide a clean decoupling network of 0.1 uF and 10 uF capacitors near the supply pins. The JTAG chain must be correctly ordered if multiple devices share the same boundary-scan bus, and unused I/O should be configured as outputs driving ground to minimize power consumption. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not consolidated on a single manufacturer or distributor page, giving engineers a one-stop reference for EPM7096QI100-15 selection and replacement decisions.
EPM7128AEFC100-5 - MAX 7000A CPLD, 128MC, 5ns, 100-FBGA | Altera
The Altera (now Intel) EPM7128AEFC100-5 is a member of the MAX 7000A family of high-density, high-performance CMOS Complex Programmable Logic Devices (CPLDs), delivering 2,500 usable gates and 128 macrocells in a 100-ball FineLine BGA (FBGA) package with 84 user I/Os. It features a 5ns pin-to-pin propagation delay and a 192.3 MHz internal frequency, supporting 3.3V core operation. According to the manufacturer datasheet, this device is fabricated on a second-generation MAX architecture with EEPROM-based configuration memory, providing in-system programmability (ISP) via JTAG. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocells with a central interconnect matrix. It sits in the programmable logic hierarchy above simple PLDs (SPLDs) and below FPGAs, offering deterministic timing, instant-on operation, and high-drive I/O. MAX 7000A devices specifically target glue logic, bus interfacing, and state-machine replacement where predictable propagation delay and non-volatile bitstream storage are critical. Key features include 100% interconnectivity between macrocells and I/O pins, programmable power management with macrocell-level enable bits, and JTAG boundary-scan support compliant with IEEE 1149.1. The 5ns speed grade places it among the fastest MAX 7000A devices, suitable for high-speed bus decoding and synchronous logic. Each macrocell contains a programmable register that can be configured as D, T, JK, or SR flip-flop with individually controllable clock, reset, and preset signals. The MAX 7000A architecture uses a Logic Array Block (LAB) structure of 16 macrocells per LAB, with a Programmable Interconnect Array (PIA) routing signals between LABs. The 100-FBGA package provides a compact 11x11 mm footprint suitable for space-constrained designs. Multiple speed grades (-5, -7, -10) allow designers to balance timing margin against cost across the same pin-compatible footprint. Typical applications include PCI bus interface glue logic, address decoding for microprocessor systems, high-speed state machines, and bus arbitration in telecommunications equipment. The wide operating voltage range also supports industrial 5V-tolerant I/O via dedicated 5V-tolerant pins. Compared to FPGA alternatives, the EPM7128AEFC100-5 offers instant-on behavior with no external configuration memory required, simplifying board design and reducing BOM cost. When designing with this device, ensure adequate power supply decoupling (typically 0.1uF and 10uF capacitors near each VCC pin) and follow Altera's JTAG programming guidelines for ISP. Designers should also consider the timing model carefully - propagation delay specifications assume specific output loading and operating conditions that must be replicated in the target system. This page synthesizes distributor pricing, drop-in same-brand alternatives, and design considerations not found in the manufacturer datasheet.
EPM7128AELC84-10N - MAX 7000A CPLD, 128 Macro, 10ns, 84-PLCC | Intel
The Intel (formerly Altera) EPM7128AELC84-10N is a high-density, in-system programmable CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000A family, delivering 128 macro cells, 2,500 usable gates, and a 10 ns pin-to-pin propagation delay. Housed in an 84-pin Plastic Leaded Chip Carrier (PLCC, J-Lead) package, the part is specified across the commercial 0C to +70C operating range and operates from a 3.3 V core supply. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantaneously-on programmable logic device that integrates multiple PAL/GAL-like logic blocks (called macro cells) on a single die with a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs and below FPGAs: they offer deterministic timing, low standby power, and unlimited in-system reprogrammability via JTAG, making them ideal for glue logic, bus interfacing, and power-up state control. Key features include 68 user I/O pins, an enhanced in-system programmability (ISP) interface supporting JTAG-based IEEE 1149.1 boundary scan, built-in PCI-compliant output drivers, programmable security bits, and a multiVolt I/O interface that allows mixing of 2.5 V, 3.3 V, and 5 V signals on the same device. The 3.3 V operation reduces power consumption by approximately 50% compared to the original 5 V MAX 7000 family while retaining the same MAX architecture. The device is fabricated on a 0.30 µm CMOS EEPROM process, providing non-volatile storage of the configuration so that the part functions immediately at power-up with no external boot PROM. The 10 ns speed grade (suffix -10) supports internal flip-flop toggle rates up to 147.1 MHz (fCNT) and global clock frequencies suitable for state-machine and address-decoding applications in the 70-100 MHz range. Typical applications include peripheral bus interface bridging (e.g., ISA-to-PCI glue logic), address decoding and chip-select generation for microprocessors/DSPs, peripheral controllers in industrial automation, and legacy system refresh designs where deterministic timing is mandatory. The EPM7128AELC84-10N is pin-compatible with the MAX 7000 family, allowing SameFrame migrations. Designers should ensure that VCC rises monotonically during power-up and that the JTAG TCK line is terminated when unused. Pin 1 is reserved for device ground reference; consult the MAX 7000A datasheet family specification before laying out high-speed I/O. This page synthesizes distributor pricing, drop-in pin-compatible alternatives in the same 84-PLCC footprint, and design notes not found in the manufacturer datasheet - information gain beyond raw spec repetition.
EPM7128AET1100-7 - 128-Macrocell MAX 7000A CPLD | Intel
The Intel (Altera) EPM7128AET1100-7 is a 128-macrocell, high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000A family, housed in a 100-pin TQFP package and rated for industrial temperature operation. It delivers 5.0V core logic with in-system programmability via the IEEE Std. 1149.1 (JTAG) interface, and combines classic MAX-architecture fast propagation delay with non-volatile EEPROM configuration cells that retain logic after power-down. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that bridges the gap between discrete 74-series glue logic and larger FPGAs. It contains multiple PAL-like logic array blocks (LABs) interconnected by a programmable switch matrix (PIA), all backed by EEPROM or flash configuration memory. In the system hierarchy, the EPM7128AET1100-7 sits between simple gate-array PLDs (PAL/GAL) and SRAM-based FPGAs, and is commonly classified under programmable logic / logic ICs within the broader semiconductor taxonomy. Key features include 128 macrocells, 2,500 usable gates, 84 user I/O pins, and 5ns pin-to-pin logic delay (the -7 speed grade). The device supports 5.0V VCCIO with 3.3V or 5V I/O tolerance, integrates four dedicated inputs for global clock/clear, and provides per-macrocell programmable power reduction. JTAG-compliant in-system programming and boundary-scan test capability allow board-level programming without removing the device. Architecturally, the EPM7128AET1100-7 uses Altera's second-generation MAX 7000A EEPROM-based logic with a 100% CMOS process and a continuous, interconnect-rich PIA (Programmable Interconnect Array). Each macrocell contains a programmable AND/OR array with flip-flop, allowing both combinatorial and registered logic, while dedicated carry chains accelerate arithmetic functions. The non-volatile EEPROM cells enable instant-on behaviour at power-up. Typical applications include legacy industrial control boards, address decoding and bus interfacing for microprocessors, glue-logic replacement on 5V rails, peripheral controllers in telecom and test equipment, and 5V-tolerant I/O expansion for newer 3.3V ASICs/FPGAs. Designers choose this part when stable 5V operation and instant-on non-volatile configuration are required. When designing with the EPM7128AET1100-7, provide a clean 5.0V supply with a 0.1 uF decoupling capacitor within 5mm of each VCC pin. Use Quartus II (or MAX+PLUS II for legacy designs) for fitting and programming; JTAG chain ordering must follow the BSDL file pin order. Observe the 100-pin TQFP thermal envelope at sustained high toggle rates. This page synthesizes distributor pricing, parametric equivalents, and practical design notes for the EPM7128AET1100-7 not found in the standalone datasheet, including lead-time context and same-package drop-in alternatives for second-sourcing.
EPM7128AETC100-10 - MAX 7000A CPLD 128MC 10ns 100TQFP | Intel
The Intel (formerly Altera) EPM7128AETC100-10 is a 3.3 V, high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000A family, built on a second-generation Multiple Array MatriX (MAX) architecture. It provides 128 macrocells, 84 user I/Os, and a pin-to-pin logic delay of 10 ns, all housed in a 100-pin Thin Quad Flat Pack (TQFP) package with 2.5K usable gates. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architectures with the density of small FPGAs. Within the broader programmable logic hierarchy, CPLDs sit between simple SPLDs and FPGAs, offering deterministic timing, low power, and in-system programmability via EEPROM or flash cells. The MAX 7000A family targets glue-logic, bus-interface, and state-machine replacement roles where deterministic propagation delay and high drive strength matter more than raw logic density. Key features include 128 macrocells organized into 8 Logic Array Blocks (LABs), 100% factory-tested operation across commercial and industrial temperature ranges, an in-system programmable (ISP) EEPROM process for fast revision changes, and JTAG-compatible IEEE 1149.1 boundary-scan test support. The device operates from a 3.3 V core supply with 5.0 V-tolerant I/O, easing migration from legacy 5 V MAX 7000S designs. Pin-compatible footprint with the 5.0 V MAX 7000S family allows drop-in upgrades in many boards. Architecturally, each macrocell contains a programmable AND/OR array plus a flipflop, with a product-term allocator that distributes up to 32 product terms per macrocell. The EPM7128AETC100-10 achieves a typical internal register-to-register toggle frequency above 150 MHz and a maximum pin-to-pin delay (tPD) of 10 ns, making it suitable for high-speed address decoding and bus arbitration. Typical applications include high-speed address decoding, peripheral glue logic, bus-width adaptation (e.g., 8-bit to 16-bit multiplexing), state-machine implementation, and digital control in industrial, telecom, and embedded systems. It is widely used in legacy designs as a replacement for discrete TTL/CMOS gate arrays. A design tip: route global clocks to dedicated GCLK pins to minimize skew, and use the JTAG chain for both ISP and boundary-scan test. Pin compatibility with MAX 7000S devices such as the EPM7128SQC100 simplifies migration from 5 V to 3.3 V systems. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
The Intel (formerly Altera) EPM7128AETC100-10N is a high-performance 3.3V EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000AE family, providing 128 macrocells, 2500 usable gates, and 84 user I/Os in a 100-pin TQFP package. Built on a second-generation Multiple Array MatriX (MAX) architecture with enhanced internal interconnect, the device supports in-system programmability via IEEE Std. 1149.1 (JTAG) and delivers 10ns pin-to-pin logic delays, making it compatible with 33 MHz PCI Local Bus Specification Revision 2.2 timing in -10 speed grades. A CPLD is a non-volatile, instant-on programmable logic device that combines the deterministic timing of PAL/PLA architectures with the density of small FPGAs, sitting between discrete glue logic and full FPGAs in the system hierarchy. The MAX 7000AE series belongs to the broader programmable logic family, which scales from these 32-to-512-macrocell CPLDs up to modern high-density FPGAs; CPLDs are preferred when deterministic propagation delay, single-chip non-volatile boot, and simple JTAG-based ISP are required without the need for an external configuration memory. Key features include 128 macrocells with 16 logic array blocks, 84 user I/O pins, 3.3V core operation with 5.0V tolerant I/O, and an extended commercial temperature range. Each macrocell contains a programmable AND/OR array with a configurable register that can be bypassed for combinational logic or retained for sequential state machines. The device also includes four JTAG-compliant pins (TDI, TDO, TMS, TCK) supporting boundary-scan test and in-system programming. The MAX architecture implements a global interconnect fabric that routes signals between Logic Array Blocks (LABs) with predictable timing, eliminating the routing-delay variability seen in SRAM-based FPGAs. The non-volatile EEPROM cells retain the programmed logic across power cycles, providing instant-on behavior at sub-microsecond times, which is critical in industrial control and PCI bus glue applications where the host processor expects deterministic configuration before reset deassertion. Typical applications include PCI bus interface glue logic, glue logic for microprocessor and DSP systems, bus decoding and address mapping, state-machine controllers, and 5V-to-3.3V translation bridges. Industrial and telecom equipment designs frequently pair the EPM7128AE with host processors to implement custom peripherals, bus arbitration, and timing-sensitive I/O expansion. When designing with this device, note that the 'N' suffix denotes lead-free / Pb-free assembly. Designers migrating from older 5V MAX 7000S parts must verify input-threshold compatibility because the AE core operates at 3.3V while outputs are 5V tolerant only with external pull-up. Always consult the MAX 7000AE Programmable Logic Device Family Data Sheet for timing model details. This page synthesizes distributor pricing, parametric alternatives, and practical design notes not found in the manufacturer datasheet.
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
The Intel (formerly Altera) EPM7128AETC100-5N is a high-density, high-performance 3.3V Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000A family, delivering 128 macrocells, 84 user I/Os, and a 5 ns pin-to-pin logic delay in a 100-pin TQFP package. It provides up to 2,500 usable gates and operates with a core VCC of 3.3V and a VCCIO bank that can be set to 3.3V or 2.5V for mixed-voltage interfacing. What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-on programmable logic device that bridges the gap between small PAL/GAL devices and larger FPGAs. It sits in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast deterministic timing, instant-on behavior from on-chip EEPROM/Flash, and lower unit cost for glue-logic applications. The MAX 7000A architecture uses an Enhanced EEPROM process with the Altera second-generation MAX interconnect, providing predictable timing paths and 100% routability. Key features of the EPM7128AETC100-5N include a maximum operating frequency of approximately 192.3 MHz, four I/O banks supporting 5.0V tolerant inputs when VCCIO is at 3.3V, in-system programmability via JTAG (IEEE Std. 1149.1), and MultiVolt I/O for interfacing with 5.0V, 3.3V, and 2.5V logic. The 100-pin TQFP package offers a compact surface-mount footprint suited to industrial control and communications glue-logic designs. Architecturally, the device integrates 128 macrocells, each composed of a programmable AND/OR/expander array and a configurable flip-flop with independent programmable clock, enable, clear, and preset control. The I/O structure includes 3.3V PCI-compliant drivers when VCCIO is tied to 3.3V, and open-drain output options for bus interface applications. The JTAG boundary-scan test circuitry supports IEEE 1149.1 boundary-scan testing and in-system configuration. Typical applications of the EPM7128AETC100-5N span industrial glue logic, address decoding for microprocessors and DSPs, bus interfacing and voltage translation between 5V and 3.3V domains, peripheral control in embedded systems, and state-machine-driven control logic. Designers choose the EPM7128A when they need fast deterministic timing, instant-on non-volatile configuration, and 5V-tolerant I/O in a moderate-density package. A key design consideration is power sequencing: the Altera datasheet requires VCC to rise monotonically for the EPM7128A family to avoid spurious configuration events. Designers should also observe the 5.0V input tolerance window (VCCIO = 3.3V) and choose 3.3V or 2.5V output drive levels based on the downstream logic family. This page synthesizes distributor pricing, drop-in alternatives from the MAX 7000A family and cross-brand pin-compatible CPLDs, and practical design notes not assembled on the manufacturer datasheet.
EPM7128AETC100-7N - MAX 7000A CPLD, 128 MC, 7.5ns, 100-TQFP | Altera
The Altera (Intel) EPM7128AETC100-7N is a high-density CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000A family, featuring 128 macro cells, 2,500 usable gates, and 84 user I/Os in a 100-pin TQFP package. It operates from a 3.3 V core supply with a propagation delay of approximately 7.5 ns (tpd) and internal counter frequencies reaching 129.9 MHz, making it suitable for glue-logic, bus interfacing, and state-machine replacement in industrial, telecom, and embedded designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits hierarchically between simple PLDs (PAL/GAL) and FPGAs in the digital logic hierarchy. Unlike SRAM-based FPGAs that require a separate boot PROM, MAX 7000A CPLDs store their configuration in on-chip EEPROM, providing instant-on behavior at power-up and deterministic fixed propagation delays. The MAX 7000A family extends the classic MAX 7000 architecture with 3.3 V operation, in-system programmability via JTAG, and pin compatibility with 5.0 V MAX 7000S devices, enabling drop-in upgrades for legacy 5 V boards. Key features of the EPM7128AETC100-7N include 128 macro cells organized into four Logic Array Blocks (LABs), 84 bidirectional I/O pins with programmable pull-up resistors during in-system programming, IEEE 1149.1 JTAG boundary-scan support, and an extended commercial temperature range. The device supports I/O standards such as 3.3 V LVTTL/LVCMOS and is built on a 0.30 µm EEPROM process that has shipped in volume for over two decades, making it a workhorse for long-life-cycle programs. Architecturally, each macro cell combines a programmable AND/OR array with a configurable register that can operate as D, T, JK, or SR flip-flop. The interconnect is a continuous FastTrack switch matrix that delivers predictable 7.5 ns pin-to-pin delays regardless of routing complexity, simplifying static timing closure. Per-pin output enable and open-drain/3-state options are programmable through the Quartus development toolchain. Typical applications include bus decoding and address mapping for legacy microprocessors, peripheral glue logic between ASICs and microcontrollers, configurable peripheral replacement, industrial control state machines, and 5 V-to-3.3 V system bridging where pin-compatible MAX 7000S designs are migrated to lower-voltage operation. When designing with this part, note that the 'C' in the part number denotes commercial temperature range (0 C to +70 C) and the '-7' speed grade indicates the 7.5 ns tpd bin; for industrial temperature grade, choose the EPM7128AETI100-7N variant instead. This page consolidates distributor pricing, drop-in alternatives, and design notes beyond the manufacturer datasheet to help engineers evaluate the EPM7128AETC100-7N against modern CPLD options and end-of-life considerations.