FPGA & CPLD
Products (6,800+)
EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel
The Intel EPM9560RI240-20N is a high-density, 5.0-V in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells and 191 user I/Os in a 240-pin BGA-style power-enhanced package. It is built on a third-generation Multiple Array MatriX (MAX) architecture that combines the density of FPGAs with the predictability and non-volatility of classic PLDs, and is fabricated with a CMOS EEPROM process that supports 5.0-V in-system programmability through the IEEE 1149.1 JTAG interface. The device delivers an internal frequency up to 145 MHz with a pin-to-pin propagation delay of 11.4 ns, making it suitable for high-performance glue logic, bus interfacing, and state-machine heavy designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses on-chip EEPROM or flash memory to store the configuration. CPLDs sit in the programmable logic hierarchy between simple PLDs (PALs/GALs) and FPGAs: they offer deterministic timing (fixed propagation delay), instant-on operation (no external boot memory), high drive strength, and a Logic Array Block (LAB) structure connected by a programmable interconnect matrix (PIA). The MAX architecture extends classic CPLD concepts with finer-grained logic elements (macrocells), more flexible I/O, and higher usable density, and the 9000 series is positioned as the high-density tier of that family tree. Key features of the EPM9560RI240-20N include 560 dedicated macrocells (12 Logic Array Blocks), a maximum internal operating frequency of 145 MHz, 11.4 ns propagation delay through the PIA, multiVolt I/O supporting 5.0-V and 3.3-V mixed-voltage interfaces, and a 5.0-V core supply. The die supports user-configurable I/O standards, in-system programmability via JTAG, and is supported by the legacy Altera MAX+PLUS II and Quartus II design environments. Device power is estimated using Altera's PowerPlay power estimation methodology integrated into those tools. The MAX architecture uses each macrocell to implement a sum-of-products combinatorial function plus an optional flip-flop, with fast feedback paths to the PIA. Global routing is deterministic, which means designers can compute worst-case timing paths analytically - useful for asynchronous bus bridges, interrupt controllers, and other latency-critical glue logic. The 5.0-V tolerant I/O and strong drive capability allow direct interface to TTL/CMOS buses without external transceivers. Typical applications include high-performance bus interfacing (PCI, VME, ISA bridges), address decoding and wait-state generation in microprocessor systems, state-machine controllers for industrial and telecom equipment, glue logic for ASIC/FPGA-based designs, and high-pin-count glue logic on VME/cPCI backplanes. The 191 user I/O pins enable direct fan-out to wide memory buses and peripheral banks without additional buffering. When designing with this device, allocate global clocks carefully - the MAX 9000 has a finite number of global clock pins and LAB-local clock resources. Use the MAX+PLUS II fitter report or Quartus compilation report to verify pin assignments and resource utilization, and respect the 5.0-V VCCIO requirements if mixing with 3.3-V peripherals through level-shifting I/O standards. Decoupling bulk 0.1 uF and 10 uF capacitors should be placed as close as possible to every VCC/VCCIO pin to meet in-system programming noise margins. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, including the same-family EPM9560 speed/pinout variants that share the same 240-pin package footprint.
EPM9560RI304 - MAX 9000 CPLD 560 Macrocell 304-Pin RQFP | Altera
The Altera EPM9560RI304 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells with a 20 ns pin-to-pin propagation delay, housed in a 304-pin BFQFP/RQFP package. It is a 5.0 V EEPROM-based programmable logic device built on third-generation Multiple Array MatriX (MAX) architecture with in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on characteristics of a PAL/GAL. CPLDs sit between simple programmable logic devices and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic semiconductor. The MAX 9000 family uses EEPROM configuration cells, so the device retains its configuration without an external boot PROM and is operational immediately after power-up. The EPM9560RI304 provides 560 macrocells, 12,000 usable gates, and 216 maximum user I/O pins, making it suitable for glue logic consolidation, bus interface bridging, and state-machine implementations that exceed the capacity of smaller MAX 7000 devices. The 20 ns propagation delay supports system clock rates in the 50 MHz class for combinatorial paths, while the 304-pin RQFP package provides the I/O count needed for wide bus interfaces. The MAX 9000 architecture is based on Logic Array Blocks (LABs) interconnected by a fast Programmable Interconnect Array (PIA), delivering deterministic, predictable timing without the place-and-route timing closure iterations typical of SRAM-based FPGAs. The 5.0 V core and I/O simplify interfacing to legacy 5 V TTL/CMOS logic, which is a key advantage in industrial and telecom equipment retrofits. Typical applications include industrial control backplanes, telecom line-card glue logic, legacy system maintenance, test equipment, and military/aerospace programs where 5 V logic and non-volatile configuration are mandatory. The industrial temperature grade (-40C to +85C) supports deployment in factory-floor and outdoor equipment. When designing with the EPM9560RI304, note that the device is configured via the JTAG interface and requires a 5.0 V supply with careful decoupling on every VCC pin. Because the part is a legacy MAX 9000 device, designers should confirm lifecycle status and consider MAX II or MAX V migration for new designs. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers maintaining or sourcing the EPM9560RI304.
EPM9560RI304-15 - 560-Macrocell MAX 9000 CPLD | Intel/Altera | 15ns
The Altera (now Intel) EPM9560RI304-15 is a high-performance CMOS EEPROM-based programmable logic device (PLD) built on the third-generation Multiple Array MatriX (MAX) architecture, housed in a 304-pin RQFP/HFQFP package. It integrates 560 macrocells, 772 flip-flops, and 212 user I/Os, with a propagation delay of 11.4 ns and a maximum internal clock frequency of 145 MHz, making it one of the highest-density members of the MAX 9000 family. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable integrated circuit that combines the deterministic timing of classic PLDs with much higher logic density, suitable for wide glue-logic, bus-interface, and state-machine functions. The MAX 9000 family sits in the hierarchy of programmable logic devices (PLD) -> CPLD -> programmable logic -> semiconductor, and is fabricated on a 5.0-V EEPROM process that supports in-system programmability (ISP) via JTAG. Key features of the EPM9560RI304-15 include 212 user I/Os configurable for 3.3 V or 5 V operation, a 4.5 V to 5.5 V supply range, an industrial temperature grade, and a propagation delay of 11.4 ns corresponding to the -15 speed grade. The Logic Array Blocks (LABs) and FastTrack interconnect deliver predictable, deterministic pin-to-pin timing, which is critical for asynchronous bus arbitration, address decoding, and clock-generation logic. The device is implemented in 0.5 µm CMOS EEPROM technology with on-chip charge pumps for in-system programming, eliminating the need for external boot memory. The MAX architecture uses a uniform interconnect that lets every macrocell drive every I/O pin, simplifying place-and-route while preserving fixed, application-independent timing. Typical applications include 32-bit and 64-bit bus decoding, peripheral glue logic in telecom and industrial controllers, address mapping and chip-select generation, and high-density state machines. The 304-pin package provides ample I/O for parallel interfaces, while the 560-macrocell capacity supports logic equivalent to several thousand gates. When designing with this part, ensure that the JTAG chain is correctly terminated (TCK pulled low, TMS pulled high at reset) and that I/O banks are powered within the 3.3 V or 5 V rail specifications. Decoupling of each VCC pin with 0.1 µF ceramics placed within 5 mm of the pin is essential for reliable ISP operation. This page consolidates distributor pricing, drop-in same-package variants, and practical design notes that complement the manufacturer datasheet.
EPM9560RI304-15N - 560-Macrocell MAX 9000 CPLD, 15ns, RQ304 | Altera
The Altera EPM9560RI304-15N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 560 macrocells and 772 flip-flops in a 304-pin RQFP package. It features a maximum internal frequency of 145 MHz, a propagation delay of 15 ns through the worst-case interconnect, and supports configurable I/O operation at 3.3 V or 5.0 V. The device is implemented in 5.0-V in-system programmable EEPROM technology built on the third-generation Multiple Array MatriX (MAX) architecture. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that sits between small-scale discrete logic (74-series gates) and large FPGAs in the programmable logic hierarchy. CPLDs use a classic AND-OR programmable plane feeding a fixed number of macrocells, giving them deterministic, fast, pin-to-pin propagation delays and instant-on behavior from non-volatile EEPROM configuration memory. They are commonly used for glue logic, bus interface bridging, address decoding, and state-machine control where predictable timing matters more than raw logic density. Key features of the EPM9560RI304-15N include 16 Logic Array Blocks (LABs) interconnected by the Programmable Interconnect Array (PIA), 216 user I/O pins, JTAG-based IEEE 1532 in-system programmability, and pin-compatibility across the MAX 9000 family. The RQFP-304 (also referenced as HFQFP-304 in distributor data) provides a 1.27 mm gull-wing pitch for surface-mount assembly. Per the Altera MAX 9000 datasheet, the device supports multi-volt I/O and operates across the commercial 0 C to 70 C range. Architecturally, the EPM9560RI304-15N combines the predictable timing of EEPROM-based macrocells with the density and routability of a structured interconnect, making it well suited to mid-complexity logic replacement (hundreds to a few thousand gates) and peripheral expansion. The 15 ns speed grade is the mid-tier timing bin, balanced between pin-to-pin delay and static power consumption. Designers use MAX 9000 CPLDs for I/O expansion, bus decoding, address mapping, and as glue logic between microprocessors, microcontrollers, and FPGAs. Typical applications include legacy peripheral replacement, glue logic in industrial controllers, bus address decoding for PowerPC/MIPS/ARM boards, JTAG-controlled I/O expansion, and rapid prototyping of state machines. The combination of non-volatile instant-on configuration, JTAG programming, and deterministic timing also makes it attractive in safety-related industrial equipment where predictable behavior at power-on is required. When designing with the EPM9560RI304-15N, ensure the supply voltage and I/O bank voltages match the JTAG chain order and other boundary-scan devices. Decoupling follows standard high-pin-count CMOS practice: 0.1 uF ceramic bypass on every VCC/VCCIO pin pair and a single bulk 10-47 uF tantalum or ceramic near the package. Because the device is 5-V core with multi-volt I/O, level translation is handled on-chip but input over-voltage on 3.3 V banks must be respected. The Altera MAX+PLUS II or Quartus MAX device support file is required for synthesis. This page synthesizes distributor pricing, MAX 9000 family pin-compatible alternatives, and practical CPLD design guidance not collected in a single datasheet excerpt.
EPM9560RI304-20 - 560 Macrocell MAX 9000 CPLD, 20ns, RQFP-304 | Intel
The Intel (Altera) EPM9560RI304-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 560 macrocells in a 304-pin RQFP (Plastic Quad Flat Pack) package with a 20 ns pin-to-pin propagation delay. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, providing 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip with a programmable interconnect fabric. It sits in the programmable logic hierarchy below FPGAs (in density) but above simple SPLDs (in integration), belonging to the broader semiconductor category of programmable logic devices. CPLDs are favored for glue-logic, bus interfacing, and state-machine implementation because they offer deterministic timing, instant-on (no configuration load time), and non-volatile storage of the bitstream. Key features of the EPM9560RI304-20 include 560 macrocells, 16 logic array blocks (LABs), a maximum of 212 user I/O pins, programmable interconnect, and 5 V in-system programmability via JTAG (IEEE 1149.1). The MAX 9000 family supports the IEEE 1149.1 boundary-scan standard for board-level testability. The device is fabricated on a 5.0 V CMOS EEPROM process, allowing the configuration to be retained without external memory. The 304-pin RQFP package provides a high I/O count for bus-intensive applications. The MAX architecture uses Logic Array Blocks (LABs) of 16 macrocells each, with a global programmable interconnect array (PIA) routing signals between LABs and I/O pins. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, supporting both combinatorial and registered logic. The EEPROM cell technology enables 100+ in-system reprogramming cycles, allowing field upgrades without removing the device from the board. Typical applications include high-speed glue logic, bus interfacing (PCI, ISA, VME), state-machine controllers, peripheral interface bridges, and digital signal conditioning. The 5 V tolerant I/Os make it suitable for industrial and legacy telecom systems where 3.3 V logic is not required. The instant-on behavior (no boot PROM needed) is ideal for safety-critical and deterministic-latency applications. When designing with the EPM9560RI304-20, observe the maximum I/O pin count of 212 and ensure the JTAG chain follows the IEEE 1149.1 topology for board-level testability. Power supply decoupling requires 0.1 uF ceramic capacitors placed close to each VCC pin. The device operates from a single 5.0 V supply, simplifying power-tree design compared to multi-rail FPGAs. This page synthesizes distributor pricing, drop-in MAX 9000 alternatives, and design guidance not found in the standalone manufacturer datasheet, helping engineers select and source the EPM9560RI304-20 with confidence.
EPM9560RI304-20C - 560-Macrocell MAX 9000 CPLD, 5V, 304-Pin RQFP | Altera
The Altera EPM9560RI304-20C is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 560 macrocells, 212 user I/O pins, and a 100 MHz maximum internal clock frequency in a 304-pin RQFP (Plastic Quad Flat Pack) surface-mount package. It provides 12,000 usable gates with 23.6 ns pin-to-pin propagation delay, operates from a single 5.0 V supply, and supports in-system programmability via the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays on a single die, connected by a programmable interconnect matrix (the Multiple Array MatriX, or MAX, architecture used here). Unlike FPGAs, which use RAM-based lookup tables and require external boot memory, CPLDs retain their configuration in on-chip EEPROM and provide deterministic, glitch-free propagation delays. MAX 9000 sits in Altera's taxonomy as a high-density 5V legacy CPLD, between MAX 7000 (mid-density 5V) and FLEX 10K (early SRAM-based FPGA). Key features include third-generation MAX architecture for predictable timing, 5.0 V in-system programmability through JTAG (IEEE 1149.1), 16 logic array blocks, 36 macrocells per LAB, fast parallel expansion across multiple devices, and pin-compatible speed grades (-20, -15, -10) within the EPM9560 family. The 304-pin RQFP provides the maximum I/O count (212) for the EPM9560 die, allowing it to replace multiple discrete logic ICs in glue-logic, bus-interface, and state-machine roles. The EPM9560RI304-20C uses CMOS EEPROM process technology with a multi-array matrix interconnect that distributes signals across 16 LABs in a predictable, deterministic-timing fabric. Designers can synthesize state machines, decoders, and bus interfaces using Altera/Intel Quartus II (legacy MAX+PLUS II) software, then program the device in-system through the JTAG pins without removing it from the board. This makes it well-suited for long-life industrial equipment where field upgrades are rare but reliability is critical. Typical applications include industrial control glue logic, telecommunications bus interfaces, ASIC prototyping, peripheral controllers, and legacy 5V system designs. It is also used as a bus arbiter or address decoder where deterministic 23.6 ns propagation delay and 5V tolerance are required. When designing with the EPM9560RI304-20C, ensure the JTAG chain (TCK, TMS, TDI, TDO) is properly terminated and that unused I/O pins are left floating or grounded per the MAX 9000 datasheet to minimize inrush during ISP. Note that newer 3.3V-only designs should migrate to MAX II or MAX V families instead. This page synthesizes distributor pricing, in-package same-family drop-in alternatives, and practical JTAG/5V design notes that are not assembled in any single manufacturer or distributor page.
EPM9560RI304-20N - 560-Macrocell MAX 9000 CPLD, 20ns, 5V | Intel
The Intel (Altera) EPM9560RI304-20N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 560 macrocells, 12,000 usable gates, and a 20 ns pin-to-pin propagation delay in a 304-pin RQFP (Plastic Quad Flat Pack) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, it integrates multiple Logic Array Blocks (LABs) interconnected by the programmable FastTrack interconnect, with each macrocell containing a programmable AND/OR array plus a configurable flip-flop for sequential or combinational logic implementation. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that retains configuration without external memory and offers deterministic, near-zero propagation delay suitable for glue logic, bus interfacing, address decoding, and state-machine replacement. Within the broader programmable logic hierarchy, CPLDs sit between simple SPLDs (PAL/GAL) and high-density FPGAs, offering predictable timing, instant-on operation, and high I/O counts that FPGAs in the same cost class cannot match. Key features include 5.0 V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, 304 user I/O pins, 212 inputs with fast input logic, a 100 MHz internal performance grade, and CMOS-compatible I/O. The EPM9560RI304-20N variant carries the -20 speed grade (20 ns tPD), making it the slowest but most cost-optimized option in the EPM9560RI304 family versus the -15 and -10 grades. Architecturally, the device partitions logic across LABs of 16 macrocells each, with each macrocell supporting product-term allocation, D/T/JK flip-flop configuration, and global/array clock selection. The FastTrack continuous routing array provides uniform, predictable interconnect delay regardless of placement - a hallmark advantage of CPLDs versus FPGAs. Typical applications include high-speed bus decoding, peripheral interfacing, glue logic in telecom and industrial control boards, address/data multiplexing, and replacement of multiple discrete SSI/MSI logic packages. Designers also use the EPM9560RI304-20N for system-level power-on reset sequencing and interrupt prioritization in legacy 5 V designs. When designing with this part, note that the 304-pin RQFP package requires a generous PCB land pattern and careful thermal management. Quartus II (legacy) or MAX+PLUS II software is required for design entry, fitting, and programming via the JTAG port. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical 5 V design notes not found in the manufacturer datasheet alone.
EPM9560RZ208-15 - MAX 9000 EPLD, 560 Logic Elements | Altera
The Altera (Intel) EPM9560RZ208-15 is a member of the MAX 9000 EPLD family, providing 560 macrocells (approximately 12,000 usable gates) in a 208-pin PowerQuad QFP (RQFP) package with -15 speed grade (15 ns pin-to-pin delay). It is built on a 0.35 µm CMOS EEPROM process that delivers non-volatile, in-system programmable logic for high-density glue-logic, bus-interface, and state-machine consolidation designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with multi-macrocell arrays, in-system programmability via IEEE 1149.1 JTAG, and predictable timing. In the broader taxonomy, an EPLD is a sub-class of CPLD (Complex Programmable Logic Device), which itself sits between discrete PLDs and high-density FPGAs. MAX 9000 sits near the upper end of the CPLD density envelope offered in the late-1990s/early-2000s Altera portfolio, providing high I/O counts and predictable timing suitable for board-level glue logic. Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, 5V tolerant I/O on selected variants, in-system programmability (ISP) through JTAG, and a maximum toggle frequency of 100 MHz. The FastTrack interconnect provides continuous routing that yields fully deterministic, hazard-free timing — every path through the device has a guaranteed propagation delay independent of logic placement. Designers can therefore budget timing without floorplanning iterations. The RQFP-208 package offers 208 pins with low profile suitable for socketed and surface-mount designs. With 212 user I/Os available in the package and high-drive capability on outputs, the EPM9560RZ208-15 is well suited for parallel bus interfaces, address decoding, memory control, and peripheral multiplexing tasks where multiple discrete 74-series devices would otherwise be required. The -15 speed grade delivers tPD = 15 ns, suiting 33 MHz synchronous designs. Typical applications include legacy industrial control systems, telecommunications backplane glue logic, ISA/PCI bus address decoding, and microcontroller peripheral expansion. The wide I/O count and predictable timing also suit it for ASIC prototyping in designs that later migrate to structured ASIC or gate-array devices. When designing with the EPM9560RZ208-15, note that the device is a mature part approaching end-of-life. Designers of new products should consider the Altera (Intel) MAX V, MAX II, or MAX 10 CPLD families, which offer lower power, smaller packages, and modern I/O standards. For legacy board replacement, verify pin compatibility with the original design footprint and review the datasheet's DC characteristics, particularly VCCIO banks and 5V tolerance. This page synthesizes distributor pricing, drop-in alternatives from the MAX 9000 family, and practical design notes not consolidated in the manufacturer datasheet — giving sourcing engineers a single reference for both qualification and substitution decisions.
EPM9560SRC208-7 - MAX 9000 EPLD, 12k Gates, 208-Pin SQFP | Altera
The Altera EPM9560SRC208-7 is a member of the MAX 9000 family of high-density Erasable Programmable Logic Devices (EPLDs) providing 12,000 usable gates in a 208-pin SQFP (Surface-mount Quad Flat Pack) package. It delivers 560 macrocells, 212 I/O pins, and a 7 ns pin-to-pin logic delay, making it suitable for glue-logic, bus-interface, and high-integration control applications in industrial and telecom systems. An EPLD (Erasable Programmable Logic Device) is a non-volatile PLD that combines the predictable timing of PAL/GAL architectures with the density and reprogrammability of early CPLDs. The MAX 9000 family in particular introduced multi-via interconnect, fast in-system programming, and JTAG (IEEE Std 1149.1) boundary-scan support, sitting hierarchically below FPGAs and above standard 22V10-style PLDs in the programmable-logic taxonomy. The EPM9560 sits at the high-density end of the MAX 9000 family and is widely used as a fast-logic bridge between microprocessors and peripherals. Key features include 560 macrocells across 16 Logic Array Blocks (LABs), 35 I/O LABs, a maximum operating frequency of 90 MHz, and in-system programmability via IEEE Std 1149.1 JTAG. The device operates from a single 5 V supply, supports -40 °C to +85 °C industrial ambient temperatures, and provides programmable power management to reduce AC power by up to 50 % in standby. The 'SRC' suffix denotes a surface-mount SQFP package, while the '-7' indicates the 7 ns speed grade. Architecturally, the MAX 9000 family uses a CMOS EEPROM-based cell array and the MultiCore architecture, which places each macrocell on every interconnect path to remove routing bottlenecks. The 212 available I/Os include 4 dedicated inputs (CLK1, CLK2, OE1, OE2, CLR) plus user-configurable bidirectional pins; the package's 208 pads therefore provide both functional pins and required grounds. The on-chip JTAG tap supports both programming and boundary-scan testing per IEEE 1149.1. Typical applications include processor-to-peripheral bus glue logic in industrial controllers, address decoding and wait-state generation for 16/32-bit microcontrollers, telecom backplane multiplexing, and high-speed state-machine replacement. Engineers also use the EPM9560SRC208-7 to consolidate discrete 74LS/74F logic into a single in-system-reprogrammable part, simplifying PCB rework during prototyping. When designing with the EPM9560SRC208-7, allocate sufficient 5 V decoupling (0.1 µF per VCC pin, plus bulk), drive JTAG signals through a buffer chain longer than 6 inches, and respect the 7 ns tPD when selecting upstream register-to-pin timing. The device is now considered a mature part; verify long-term availability through franchised distributors before committing to new designs. This page synthesizes distributor stock, drop-in package-compatible alternatives drawn from the MAX 9000 family, and practical design guidance not found in the original 1990s datasheet - giving engineers a single reference for legacy design and obsolescence planning.
EPM9560SRC240-15 - MAX 9000 CPLD, 560 Gates, 240-Pin | Intel / Altera
The Intel / Altera EPM9560SRC240-15 is a member of the MAX 9000 family of Complex Programmable Logic Devices (CPLDs) housed in a 240-pin Surface-Mount RQFP package. It provides 560 usable gates, 16 logic array blocks, and a 15 ns maximum pin-to-pin logic delay, making it suitable for high-density glue-logic, bus-interface, and state-machine designs that were typical in late-1990s and early-2000s telecom and industrial systems. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that combines multiple PAL/GAL-like macrocells on a single die with an interconnect fabric. The MAX 9000 family sits in the broader taxonomy: programmable logic device (PLD) -> CPLD -> EPLD/CPLD -> high-density programmable logic. CPLDs are characterized by deterministic timing, predictable I/O placement, and zero-configuration EEPROM or EPROM cells, distinguishing them from SRAM-based FPGAs which require a separate boot PROM. Key specifications of the EPM9560SRC240-15 include 560 usable gates, 16 Logic Array Blocks (LABs), 212 macrocells, and a maximum operating frequency (fMAX) consistent with the 15 ns tPD speed grade. The device operates from a single 5 V supply and is offered in the 240-pin surface-mount RQFP (S-prefix) package, with the RC240 variants being the pin-compatible ceramic PGA/quad equivalents in the same family. Architecturally, the EPM9560 uses Altera's classic MAX (Multiple Array matriX) architecture with a global interconnect that routes signals between LABs. Each LAB contains 16 macrocells with individual product-term allocation, and the device is in-system programmable (ISP) via a JTAG/IEEE 1149.1 boundary-scan interface. The -15 speed grade denotes 15 ns maximum pin-to-pin delay, making it suitable for 66 MHz-class system bus applications. Typical applications include 5V glue-logic consolidation, address decoding and bus-interface bridging, peripheral controller replacement (replacing dozens of 74LS/74F TTL devices), industrial control state machines, and telecom backplane glue logic. The instant-on, non-volatile nature of MAX 9000 makes it preferable to SRAM FPGAs in deterministic-startup applications such as military/aerospace and industrial control. When designing with the EPM9560SRC240-15, note that the device is a legacy mature part. Lead-time and lifecycle status must be verified before new designs, as the part is approaching or has entered NRND/EOL status with major distributors. The S-prefix denotes the surface-mount RQFP variant, while the RC-prefix denotes the pin-compatible ceramic-quad variant. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet. The EPM9560SRC240-15 belongs to the EPM9560 family, with speed grades -10, -12, -15, and -20 and package options including RQFP-208, RQFP-240, and PGA-280.
EPM9560TC208-20 - MAX 9000 CPLD, 560 Macrocells, TQFP-208 | Altera
The Altera EPM9560TC208-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells with a 20 ns propagation delay in a 208-pin TQFP (TC208) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, this device delivers 12,000 usable gates with in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface, eliminating the need for a separate programmer. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays on a single die with a programmable interconnect matrix. CPLDs sit in the broader taxonomy of programmable logic devices (PLDs) alongside FPGAs, but are typically used for glue logic, bus interfacing, state-machine control, and fast deterministic I/O rather than large parallel data processing. The MAX 9000 architecture extends the MAX 5000/7000 lineage with enhanced macrocell density, JTAG-ISP support, and 5V-tolerant I/O, making EPM9560 devices appropriate for industrial, telecom, and embedded control subsystems. Key features of the EPM9560TC208-20 include 560 macrocells, 12,000 usable gates, 149 user I/O pins (per family datasheet), and a 20 ns pin-to-pin propagation delay (commercial grade, -20 speed grade). The device operates from a 5V core supply with MultiVolt I/O supporting 3.3V and 5V interface levels. Programmable interconnect is achieved through the continuous FastTrack interconnect array, and non-volatile EEPROM cells store configuration without external memory. The TQFP-208 package (JEDEC S-PQFP-G208) provides a 0.5 mm pitch surface-mount footprint compatible with standard PCB assembly and reflow processes. The EPM9560TC208-20 is supported by Altera MAX+PLUS II and Quartus development tools, which provide VHDL/Verilog synthesis, timing simulation, and JTAG programming via the ByteBlaster or MasterBlaster download cables. Configuration is loaded through the built-in JTAG port, supporting both in-system programming during board bring-up and field firmware updates. Typical applications include industrial control glue logic, telecom bus interfacing, address decoding for microprocessor systems, PCI bus interface bridging, and state-machine controllers in embedded designs. Designers should budget adequate ground and 5V decoupling near the package, observe JTAG chain integrity for ISP, and verify that the chosen I/O standard matches downstream ASIC/FPGA logic levels before final routing.
EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
The Altera EPM9560WC208 is a 560-macrocell electrically erasable programmable logic device (EE PLD) from the MAX 9000 family, packaged in a 208-pin ceramic quad flat pack (CQFP-208) with 0.50 mm terminal pitch. It operates from 3.3 V or 5 V rails, supports a maximum clock frequency of approximately 117.6 MHz, and provides up to 149 user-configurable I/O lines for high-density glue-logic and state-machine integration. The device uses a CMOS EE process that retains configuration in non-volatile cells, allowing instant-on behaviour without an external boot PROM. The MAX 9000 family is a high-density complex programmable logic device (CPLD) lineage positioned between classic PAL/GAL arrays and modern FPGAs. It integrates multiple logic array blocks (LABs) with a programmable interconnect matrix (PIA), giving engineers thousands of usable flip-flops (the EPM9560 series reaches 772 flip-flops) on a single die. Designers choose this category when deterministic pin-to-pin timing, instant-on non-volatile configuration, and 5 V tolerance are all required - conditions that mainstream SRAM-based FPGAs cannot meet without external supervision. Key features of the EPM9560WC208 include 560 macrocells across 35 LABs, 772 dedicated flip-flops, 16.6 ns pin-to-pin propagation delay in the -15 speed grade, in-system programmability via IEEE 1149.1 JTAG, and built-in hot-socketing support that allows the device to be inserted into a powered backplane without latch-up. The CQFP-208 ceramic package is a ruggedized form factor that historically served military, aerospace, and down-hole telemetry applications where plastic packages are unsuitable. The architecture is built on a CMOS electrically erasable process; configuration EEPROM cells hold the pattern even when power is removed, eliminating the boot PROM required by SRAM FPGAs. With 149 I/O pins distributed across 5 V-tolerant banks, the EPM9560WC208 can bridge multiple logic domains on the same board, including 3.3 V microcontrollers, 5 V peripheral buses, and TTL peripherals, simplifying mixed-voltage glue logic. Typical applications include military and aerospace avionics, industrial motor control, telecom backplane bridging, legacy bus protocol conversion (VME, PCI), and replacement of multiple discrete PAL/GAL devices. Engineers select the EPM9560WC208 when the design needs the instant-on behaviour of non-volatile EE memory combined with the timing predictability of a MAX-family CPLD. When designing with this part, ensure that the JTAG chain is correctly ordered and that the ceramic CQFP-208 package is matched to a socket or PCB land pattern rated for ceramic body dimensions. Note that Altera has issued a Product Discontinuance Notice (PDN) for selected MAX 9000 ordering codes, so designers should verify lifecycle status and consider migrating to the EPM9560 in the 208-pin RQFP plastic package for new designs. This page synthesizes distributor availability, drop-in alternatives, lifecycle status, and practical design notes not found in the manufacturer datasheet.
EPM9560WC208-15 - 560-Macrocell EE PLD, 117.6 MHz | Altera
The Altera EPM9560WC208-15 is a member of the MAX 9000 family of electrically-erasable programmable logic devices (EE PLDs) from the legacy Altera MAX architecture, delivering 560 macrocells, 35 Logic Array Blocks (LABs), and 772 flip-flops in a 208-pin Ceramic Quad Flat Pack (CQFP-208) package with 0.50 mm terminal pitch. It features a maximum clock frequency of 117.6 MHz and a propagation delay of 16.6 ns (commercial speed grade -15), supplied in a CMOS process supporting 3.3 V or 5.0 V configurable I/O operation. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the user after manufacture, sitting in the broader hierarchy: PLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. The MAX 9000 series pioneered high-density EE PLDs using EEPROM configuration cells, allowing in-system reprogrammability without an external configuration memory. This places the EPM9560 in a distinct class between simple PAL/GAL devices and full FPGAs, offering predictable timing, deterministic pin-to-pin delays, and high usable-gate counts. Key differentiating specifications include 560 macrocells (the largest in the MAX 9000 family), 149 usable user I/O pins (3.3 V/5 V tolerant), 35 LABs providing structured logic fabric, and 117.6 MHz maximum internal frequency. The 208-pin CQFP package provides hermetic ceramic packaging suited for harsh thermal and mechanical environments, with a 0.50 mm pitch suitable for surface mounting on standard PCB land patterns. Programming is performed via the JTAG-compliant IEEE Std 1149.1 boundary-scan interface using the Altera MAX+PLUS II or Quartus development toolchains. Typical applications include industrial control logic, telecom interface glue logic, MIL/Aerospace systems requiring hermetic ceramic packaging, military-grade replacement of discrete TTL/CMOS logic, and legacy 5 V system glue logic. The wide 3.3 V/5 V I/O compatibility simplifies migration from 5 V ASICs to programmable equivalents without level shifters. When designing with the EPM9560WC208-15, account for the ceramic CQFP package thermal behavior, which is markedly better than plastic QFP packages and well-suited for extended-temperature applications. Use the MAX+PLUS II baseline and fitter to verify pin assignments and timing closure before committing to the layout. Note that Altera has formally discontinued the 208-pin CQFP package and recommends the form-fit-function equivalent 208-pin RQFP variants for new designs.
EPM9560WC208-15C - 560-Macrocell EE PLD | Altera MAX 9000
The Altera EPM9560WC208-15C is a high-density Electrically Erasable Programmable Logic Device (EE PLD) from the MAX 9000 series, featuring 560 macrocells in a 208-pin Ceramic Quad Flat Pack (CQFP-208) with 0.50 mm terminal pitch. The device operates from a 3.3 V or 5 V supply, delivers a maximum clock frequency of 117.6 MHz, and offers a pin-to-pin propagation delay of 16.6 ns in the -15 speed grade. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on logic fabric that combines multiple Programmable Logic Array (PLA)-style blocks with a centralized interconnect matrix. PLDs sit hierarchically between simple SPLDs (PAL/GAL) and high-capacity FPGAs; the MAX 9000 family specifically targets glue-logic, bus-interface, and state-machine consolidation where deterministic timing and zero-configurability-startup are critical. Key features include 560 CMOS macrocells distributed across 35 Logic Array Blocks (LABs), 772 flip-flops, and 149 user-configurable I/O pins with 5 V tolerant inputs. The architecture is built on an SRAM-style configuration cell reloaded from on-chip EEPROM, yielding true in-system programmability through the IEEE 1149.1 JTAG interface. A typical internal counter frequency of 117.6 MHz enables fast sequencer design, while the 16.6 ns tPD supports 60 MHz synchronous glue logic. The device is implemented in a 0.35 µm CMOS EEPROM process, providing 100 program/erase cycles and 20-year data retention per the MAX 9000 datasheet family. The I/O structure uses 3.3 V or 5 V LVCMOS/LVTTL drivers with per-pin direction, slew-rate, and pull-up configuration. MultiVolt I/O allows direct interfacing between 5 V and 3.3 V buses without external level shifters, simplifying mixed-voltage board design. Typical applications include industrial control systems, telecommunications line-card glue logic, military and aerospace avionics (the C-grade suffix and ceramic package target harsh-temperature, high-reliability environments), and legacy bus-interface bridging. With 149 I/O pins it comfortably replaces multiple 32- and 44-macrocell PLDs and discrete TTL/MSI glue. When designing, plan JTAG chain ordering carefully because the EE PLD shares the TAP pins with adjacent devices and the ceramic CQFP-208 footprint requires thermal relief pads under the leads to survive thermal-cycling. Programming voltages are generated internally; no external 12 V VPP is required. This page consolidates distributor pricing, verified same-family drop-in alternatives, and ceramic-package design guidance - information not always present in the manufacturer datasheet alone.
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
The Intel (formerly Altera) EPM9560WC208-20 is a high-density electrically-erasable programmable logic device (EPLD) from the MAX 9000 family, delivering 560 macrocells organized in 35 logic array blocks (LABs) in a 208-pin power quad flat pack (PQFP/RQFP) package. The device is a CMOS, in-system-programmable complex PLD with a maximum propagation delay of approximately 23.6 ns (the “-20” speed grade) and supports operation with both 3.3 V and 5 V I/O signaling for flexible mixed-voltage system design. A CPLD (Complex Programmable Logic Device) is a non-volatile reconfigurable digital IC built from an array of AND/OR macrocell structures backed by EEPROM or flash memory; it occupies the design hierarchy between simple PLDs (PAL/GAL) and FPGAs, providing deterministic timing, fast I/O response, and instant-on behavior without external boot memory. Within Altera’s MAX 9000 family the EPM9560 sits at the top of the 9000 series density range, with 149 usable I/O pins and a programmable interconnect that makes it well suited to bus decoding, address mapping, glue-logic and state-machine replacement in industrial and telecom systems. Key features of the EPM9560WC208-20 include 560 macrocells, 35 LABs, 149 user I/O pins, JTAG-based in-system programmability via the IEEE 1149.1 boundary-scan test (BST) interface, dual 3.3 V/5 V I/O capability, and a programmable register/feedback architecture. The “W” suffix designates the power PQFP package with enhanced thermal characteristics for high-density designs, and the “-20” designator indicates a 23.6 ns pin-to-pin logic delay suitable for systems clocked up to roughly 40 MHz on combinational paths. Architecturally the device uses an EEPROM-based macrocell with individually programmable product-term steering, D/T/JK flip-flops, and a global interconnect matrix that delivers predictable, deterministic timing independent of routing density. This makes timing closure straightforward for address decoding, interrupt steering, and synchronous state-machine designs where FPGAs would add unnecessary silicon cost and configuration overhead. Typical applications include high-density bus and address decoding in microprocessor/microcontroller systems, peripheral interface glue logic (e.g., PCI/ISA bus bridges), state-machine and sequencer replacement, industrial control logic, telecom backplane glue logic, and JTAG-driven system monitoring. The 149 I/O pins allow large pin-count designs to be consolidated into a single PLD. When designing with this device, always observe the maximum I/O count (149), respect the dual-voltage VCCIO/VCCINT power sequencing rules, and use the Quartus II or MAX+PLUS II toolchain for design entry, fitting, and JTAG programming. Decoupling caps (0.1 microfarad ceramic in parallel with 10 microfarad bulk) should be placed within 1 cm of each supply pin to maintain signal integrity during in-system programming cycles. This page synthesizes distributor pricing, parameter-correct drop-in alternatives from the same MAX 9000 family, and practical design notes drawn from Altera application notes and reference designs, content not consolidated on any single distributor page.
EPM9560WC208-20C - 560-Macrocell EE PLD, 20ns, CQFP-208 | Altera
The Altera EPM9560WC208-20C is a 560-macrocell Electrically Erasable Programmable Logic Device (EE PLD) from the MAX 9000 family, housed in a 208-pin Ceramic Quad Flat Pack (CQFP-208) package and rated at a 20 ns pin-to-pin propagation delay. This CMOS device integrates 35 Logic Array Blocks (LABs) and exposes 149 usable I/O lines, supporting both 3.3 V and 5 V signaling for flexible system interfacing. The part carries a commercial temperature grade (the trailing "C" suffix) and provides JTAG BST in-system programmability. What is a Programmable Logic Device (PLD)? A PLD is a generic term for an integrated circuit whose logic function is defined by the end user after manufacture, rather than being hard-wired by the foundry. EE PLDs add non-volatile, electrically erasable configuration memory so the design can be re-programmed thousands of times in-circuit. The MAX 9000 family belongs to the higher-density tier of complex PLDs (CPLDs), bridging between classic 22V10-style PLDs and modern FPGAs in the programmable-logic taxonomy: PLD -> CPLD -> MAX 9000 -> high-density EE PLD. Compared with FPGAs, MAX 9000 parts offer deterministic timing, instant-on non-volatile configuration, and high pin-to-pin drive strength, which is why they remain favored in glue-logic, bus-interface, and legacy industrial designs. Key features include 560 macrocells, 35 LABs, 149 user I/Os, 20 ns propagation delay, JTAG-based in-system programmability, and operation from a 3.3 V or 5 V supply. The architecture combines a global interconnect with per-macrocell registers, allowing both combinatorial and registered logic with predictable timing. Configurable I/O standards enable mixed-voltage interfacing without external level shifters. Typical applications include legacy bus-interface glue logic in telecom and industrial backplanes, address decoding and wait-state generation in 5 V/3.3 V embedded systems, industrial control boards, and avionics/military systems that rely on the ceramic CQFP package for thermal and reliability robustness. The 208-pin ceramic package is selected where extended temperature, vibration tolerance, or hermeticity is required. When designing with this part, mind the 20 ns tPD: at a 33 MHz bus it offers zero wait-state decode, but at 50 MHz external latches become necessary. Decoupling should follow Altera's MAX 9000 reference design with one 0.1 uF ceramic per VCC/GND pair plus a 10 uF tantalum bulk cap. The device is mature and obsolete/last-time-buy at most distributors, so design teams should verify lifecycle and pinout against the original Altera datasheet before committing to new layouts. This page synthesizes distributor availability, parametric equivalents, and practical design notes not found in the manufacturer datasheet.
EPM9560WI208-20 - 560-Cell CPLD, 23.6ns, CQFP-208 | Intel / Altera
The Intel / Altera EPM9560WI208-20 is a high-density 560-cell Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin Ceramic Quad Flat Pack (CQFP208) package with gull-wing leads. It provides 23.6ns pin-to-pin logic delay, 560 macrocells, 16 logic array blocks, and up to 212 user I/O pins for complex glue-logic, bus-interface, and state-machine designs. The device is built on a 0.35-micron CMOS EEPROM process and is rated for industrial temperature operation. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix. In the broader taxonomy it sits under programmable logic -> PLD -> CPLD -> MAX 9000 series -> high-density glue logic. CPLDs are commonly deployed as deterministic, low-latency controllers alongside microprocessors, FPGAs, and ASICs, providing boot configuration, address decoding, bus arbitration, and custom I/O expansion with predictable timing and instant-on behavior from on-chip EEPROM. Key features of the EPM9560WI208-20 include 560 macrocells, 16 logic array blocks (LABs), 212 maximum user I/O pins, 23.6ns worst-case pin-to-pin propagation delay (tPD), a JTAG-based IEEE 1149.1 boundary-scan interface, and in-system programmability via JTAG. The internal EEPROM configuration cells allow instant-on operation at power-up without external boot memory, and the device is supported by the Altera MAX+PLUS II and Quartus design tools. The MAX 9000 architecture splits the device into LABs connected by a programmable interconnect array (PIA). Each macrocell contains a programmable-AND/OR array, a flip-flop, and product-term steering, which gives the part deterministic 23.6ns timing across all paths. The 560-cell capacity places this device in the upper tier of the MAX 9000 family, suitable for designs that exceed the density of the MAX 7000 family but do not require an FPGA. Typical applications include military and aerospace avionics, industrial process control, telecommunication line cards, and legacy bus-bridge designs. The ceramic CQFP-208 package is preferred in harsh-environment and high-reliability systems where plastic packages are not acceptable, including down-hole, military, and aerospace programs. When designing with the EPM9560WI208-20, note that the -20 speed grade reflects 23.6ns tPD; faster -15 and -10 grades are available in the same MAX 9000 family for tighter timing budgets. Because this part is in the Ceramic QFP package with gull-wing leads, PCB layout must accommodate the larger pad geometry and inspect for lead coplanarity during assembly. This page synthesizes distributor pricing, drop-in same-family alternatives, application guidance, and comparison data not aggregated in a single location on the Altera / Intel datasheet.
GAL22V10D-15LPNI - 15ns 10-Macrocell E2CMOS PLD DIP-24 | Lattice
The Lattice Semiconductor GAL22V10D-15LPNI is a high-performance, electrically erasable CMOS Programmable Logic Device (PLD) in the industry-standard 22V10 architecture, packaged in a 24-pin PDIP (300-mil, through-hole DIP). It features 10 Output Logic Macrocells (OLMCs), a 15 ns maximum propagation delay, and an internal timing margin equivalent to roughly 83.3 MHz f_max, making it the highest-performance member of the GAL22V10 family. A PLD (Programmable Logic Device) is a digital integrated circuit whose logic function and interconnects are defined by the user after manufacture. Within the IC taxonomy, PLDs sit between fixed-function logic gates and full FPGAs: a PLD implements combinational and registered logic via a programmable AND/OR array with dedicated output macrocells, whereas an FPGA uses distributed look-up tables, block RAM and soft cores. The "22V10" naming convention means 22 inputs (12 dedicated + 10 feedback) feeding 10 macrocells with variable drive polarity — this generic footprint is supported across multiple vendors, including Lattice, Atmel/Microchip and AMD, giving designers drop-in second sources. Key features of the GAL22V10D-15LPNI include 10 ns / 15 ns propagation delay grades, electrically erasable (E2CMOS) technology allowing 100+ reprogram cycles, in-system programmable architecture, a built-in security bit to lock the pattern, and low CMOS standby current with TTL-compatible I/O. The device is functionally and parametric compatible with standard bipolar and CMOS 22V10 devices, including the classic PAL22V10. The GAL22V10D combines a high-performance CMOS process with Electrically Erasable (E2) floating gate technology. The 10 OLMCs are individually configurable as registered, combinatorial, or I/O with selectable output polarity, and feedback paths allow buried state machines. Unlike UV-erasable EPROM-based 22V10s, the E2CMOS cell can be erased electrically in-circuit, which simplifies prototyping and field upgrades. Typical applications include address decoding and glue logic for microprocessor systems, state-machine and sequencer controllers, bus arbitration logic, peripheral interface adapters, and industrial control replacements of legacy bipolar PALs. Through-hole PDIP packaging suits legacy boards, test fixtures, and aerospace/industrial designs where DIP is preferred over surface mount. When designing, remember the GAL22V10D-15LPNI requires a single 5 V supply (VCC = 4.75 V to 5.25 V) and the JEDEC-standard 22V10 fuse map. Use a Lattice-approved programmer (e.g., ispGAL22V10-compatible) to load the pattern; the security bit, once programmed, prevents readback of the device. This page synthesizes distributor stock data, parametric alternatives, and practical design guidance not aggregated on any single manufacturer or distributor page, giving engineers a single reference for sourcing and second-sourcing the GAL22V10D-15LPNI.
ICE40HX4K-TQ144 - 3520-LUT 1.2V FPGA | Lattice Semiconductor
The Lattice Semiconductor ICE40HX4K-TQ144 is an ultra-low-power HX-series field-programmable gate array (FPGA) with 3,520 logic cells, 107 I/Os, 81,920 bits of configuration memory, and a 144-pin TQFP package. It operates from a 1.2 V core supply according to the supplied distributor data. The device targets compact, low-power programmable logic systems where FPGA flexibility is needed without the power and board complexity of a larger high-performance FPGA. A field-programmable gate array is a configurable digital semiconductor that contains programmable logic blocks, routing resources, input/output blocks, and configuration memory. In the hierarchy, an FPGA is a programmable logic device, a digital IC, and a semiconductor. Unlike a fixed-function microcontroller or application-specific integrated circuit, an FPGA can be programmed after manufacture to implement parallel data paths, control logic, serial interfaces, and hardware signal processing. The ICE40HX4K provides 3,520 logic cells and 81,920 bits of configuration memory, as identified by DigiKey and Mouser search results. Its 107 I/Os provide substantial connectivity for external memory, sensors, communications, control signals, and general-purpose digital interfaces. The HX family is positioned by Lattice as a low-power, high-performance FPGA family, making the part suitable for embedded control, communication, instrumentation, and education platforms where low static power and fast programmable logic are important. The 144-pin TQFP package exposes the FPGA in a conventional surface-mount form factor suitable for automated assembly and multilayer PCB designs. The verified source snippets identify the package as 144-pin TQFP or 144-LQFP terminology; designers should confirm the exact mechanical drawing and pin names against the manufacturer datasheet before releasing a PCB footprint. The supplied data does not specify speed grade, temperature range, power consumption, pin names, memory architecture beyond configuration capacity, or I/O voltage limits. Typical uses include custom interface controllers, low-power sensor aggregation, digital signal conditioning, communications adapters, test fixtures, and FPGA-based education or prototyping boards. For a new design, use the manufacturer’s configuration toolchain and verify pin assignments, supported I/O standards, clocking resources, power rails, decoupling requirements, and programming interface compatibility. Because the supplied evidence confirms the family and capacity but not a complete electrical characterization, unsupported values should not be inferred from generic iCE40 family claims.
ISPLSI - Lattice In-System Programmable Logic Family | CPLD
The Lattice Semiconductor ISPLSI family is a series of high-density, in-system programmable CMOS Complex Programmable Logic Devices (CPLDs) introduced in the early 1990s. The flagship ispLSI 1016 device delivers 2000 PLD gates with 96 registers, 32 universal I/O pins, 4 dedicated inputs, and 3 dedicated clock inputs in a 44-pin package. The family spans multiple sub-series including ispLSI 1000, 2000, 2000E, 2000VE, 3000, 5000V, 8000, and 8000V with gate counts from 1K to 45K and macrocell counts from 32 to 480. A CPLD (Complex Programmable Logic Device) is a type of programmable logic that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect network. In the broader taxonomy, CPLDs sit alongside FPGAs in the programmable logic category, but use non-volatile EEPROM or flash configuration memory and a deterministic AND-OR logic fabric. Unlike SRAM-based FPGAs, most ispLSI devices retain their configuration without external boot memory, enabling instant-on operation - an important advantage for glue logic, bus interfacing, and power-up deterministic state machine applications. The ispLSI family pioneered 5V in-system programmability (ISP) via a 4-wire JTAG-like interface, allowing devices to be re-programmed on a populated PCB without removing the chip. This eliminated the expensive UV-erase window and programmer sockets required by earlier EPLDs. The Global Routing Pool (GRP) provides complete, deterministic 100% connectivity between all logic blocks and I/O pins with predictable timing - critical for replacing discrete 74-series glue logic in industrial and telecom designs. The ispLSI 2000E sub-family extends the architecture to 32 to 128 macrocells with 1K to 4K gates, while the ispLSI 5000V series scales to 256 macrocells with 12K gates. The ispLSI 8000V reaches 480 macrocells and 45K gates. All members share the same Lattice development flow using ispLEVER or ispDesignEXPERT software. Typical applications include peripheral bus interfacing, address decoding, state-machine replacement of discrete logic, and TTL/CMOS logic consolidation. When designing with ispLSI devices, ensure the JTAG ISP pins (TMS, TCK, TDI, TDO) are accessible for in-system programming. Use Lattice's recommended decoupling (typically 0.1uF per VCC pin) and follow the GRP routing guidelines for predictable timing. Most ispLSI devices are now classified as mature or discontinued by Lattice, so designers should evaluate ispMACH 4000 or MachXO2/XO3 as modern replacements for new designs.
ISPLSI 1032-60LT - 128-Macrocell 5V CPLD, 60MHz, TQFP-100 | Lattice
The Lattice Semiconductor ISPLSI 1032-60LT is a high-density in-system programmable Complex Programmable Logic Device (CPLD) from the ispLSI 1000 family, delivering 6000 PLD gates, 128 macrocells, and 192 registers in a 100-pin TQFP surface-mount package. It operates from a single 4.75 V to 5.25 V supply and provides a maximum propagation delay of 20 ns (60 MHz fMAX). According to the Lattice ispLSI 1032 datasheet, the device integrates 64 universal I/O pins, eight dedicated input pins, four dedicated clock input pins, and a Global Routing Pool (GRP) that distributes signals across the chip with predictable, fixed delay. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple SPLDs/PLAs and large FPGAs in the programmable-logic taxonomy (CPLD -> PLD -> programmable logic -> digital semiconductor). It uses a small-block, sum-of-products architecture with macrocells, making it ideal for implementing wide combinational and registered logic, glue logic, bus decoding, state machines, and address decoding. Unlike SRAM FPGAs, the ispLSI 1032 is non-volatile and in-system programmable via a standard 5-pin JTAG chain, so designs can be updated on production hardware without removing the device. Key features of the ISPLSI 1032-60LT include 32 logic elements (each containing 16 macrocells with associated I/O), 6000 gates of usable logic, 4 dedicated clock inputs feeding four global clock buffers, asynchronous clear and preset per register, JTAG/IEEE 1149.1 boundary-scan test support, and 5 V CMOS I/O with TTL-compatible thresholds. The GRP provides a deterministic, fixed interconnect delay regardless of placement, simplifying timing closure for registered and combinatorial logic. Typical applications include wide address decoding, bus interface glue logic, state-machine controllers, peripheral interface latching, fast counters, frequency and pulse-width measurement, and any design requiring non-volatile, deterministic-timing 5 V glue logic in industrial control, telecom backplane, and embedded processor bus systems. When designing with this device, ensure the 5 V supply is within the 4.75 V to 5.25 V range and that all I/O banks are referenced to a single 5 V rail. Decouple VCC with 0.1 uF and 10 uF capacitors close to the pins. Note that Lattice's own ispMACH 4000V is the recommended modern replacement family for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ISPLSI1016E-125LT44 - 2K Gates, 64 Macrocells, 125 MHz CPLD | Lattice
The Lattice Semiconductor ISPLSI1016E-125LT44 is a 5 V in-system programmable high-density Complex Programmable Logic Device (CPLD) from the ispLSI 1000E family, delivering 2K usable gates, 64 macrocells, and 96 registers in a 44-pin TQFP (LT44) package. It achieves a pin-to-pin propagation delay (tPD) of 7.5 ns and a maximum operating frequency (fMAX) of 125 MHz, making it suitable for high-speed glue logic and bus-interface bridging in industrial and legacy embedded systems. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays with a central interconnect fabric. CPLDs sit alongside FPGAs in the programmable logic hierarchy, but are distinguished by their deterministic timing, instant-on non-volatile configuration (typically E2CMOS), and lower logic density. The ISPLSI 1000E family belongs to Lattice's first-generation ispMACH-era devices, designed for fast I/O decoding, state-machine replacement, and peripheral interfacing in 5 V systems. Key features of the ISPLSI1016E-125LT44 include 32 universal I/O pins, four dedicated input pins, three dedicated clock input pins, and one global output-enable input routed through a Global Routing Pool (GRP) that provides complete interconnectivity between all logic elements. The device supports 5 V in-system programmability (ISP) via IEEE 1149.1 boundary-scan, enabling firmware upgrades without removing the part from the board. Programmable interconnect and macrocell registers allow designers to replace multiple discrete TTL/CMOS packages with a single non-volatile device. The ispLSI 1016E architecture partitions logic into four Generic Logic Blocks (GLBs), each containing 16 macrocells, a 32-bit product-term array, and dedicated clock/reset/preset control. The GRP delivers 100% connectivity between GLBs and I/O cells with predictable, fixed delays that simplify static timing closure. An on-chip diagnostic TAP allows read-back of programmed state for in-system verification, a feature rare among 5 V CPLDs of this generation. Typical applications include industrial control glue logic, ISA/PCI bus address decoding, peripheral interfacing (UART, FIFO, bus controllers), 5 V legacy system upgrades, and state-machine replacement on 3.3 V-5 V mixed boards. Its 5 V tolerance and industrial temperature grade make it a long-life component for factory automation, instrumentation, and telecom backplane designs where newer 3.3 V-only CPLDs cannot be used directly. When designing with this part, note that the LT44 (TQFP-44) footprint differs from the 44-pin PLCC variant (LJ44). Verify pinout compatibility before PCB rework. Decoupling caps (0.1 uF plus 10 uF bulk) should be placed within 5 mm of each VCC pin, and unused I/O pins must be configured as outputs with defined logic levels to minimize quiescent current. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers source and integrate legacy ispLSI parts confidently.
LC4032B-5T44C - 32-Macrocell 400MHz CPLD | Lattice
The Lattice Semiconductor LC4032B-5T44C is a 3.3V, 2.5V, or 1.8V in-system-programmable SuperFAST high-density PLD with 32 macrocells, a maximum operating frequency of 400MHz, and a propagation delay of 2.5ns. It is supplied in a 48-pin TQFP package, making it suitable for compact systems that require reconfigurable glue logic, interface control, clock distribution, and protocol bridging. A complex programmable logic device, or CPLD, is a programmable logic device that combines nonvolatile configuration storage with a structured array of macrocells. In the hierarchy of programmable logic devices, a CPLD sits above simple programmable logic arrays and provides deterministic timing, repeated in-system programming, and logic capacity suitable for consolidating multiple small fixed-logic functions. The LC4032B family supports 32 macrocells and up to 80 product terms per output, according to the supplied manufacturer-family search result. The principal performance features are a 400MHz maximum operating frequency, 2.5ns propagation delay, support for as many as four global clock pins, and programmable clock-polarity control. The device can operate with 3.3V, 2.5V, or 1.8V supply rails, allowing integration into systems with mixed voltage requirements. Its in-system-programmable architecture supports configuration updates without removing the device from a circuit. The LC4032B implementation uses an electrically erasable programmable nonvolatile memory architecture for persistent configuration, avoiding external configuration PROM. Global clock resources support high-speed synchronous logic, while distributed product-term logic provides flexible combinational and registered functions. These resources are relevant in control-plane designs where a small FPGA may be excessive but fixed logic would be costly to revise. Typical uses include bus-interface decoding, display and keypad control, industrial control modules, peripheral glue logic, data acquisition systems, communications equipment, and FPGA or processor companion logic. The 48-pin TQFP provides a practical balance between routing access, thermal performance, and board-space requirements. Designers should verify the exact pin assignments, supported I/O standards, AC timing values, and configuration requirements against the manufacturer datasheet before layout. Decoupling, ground-plane continuity, clock routing, and unused-pin treatment are particularly important in high-speed CPLD designs, even when the logic function appears simple. This page combines verified device identity, family-level performance information, sourcing links, practical design guidance, and qualified comparison context that is not consolidated on a standard distributor listing.
LC4032B-5T44I - 32 Macrocell 5 ns CPLD | Lattice
The Lattice Semiconductor LC4032B-5T44I is an in-system-programmable complex programmable logic device with 32 macrocells, a 5 ns speed grade, and a 44-TQFP package. The verified distributor description identifies it as a SuperFAST high-density PLD supporting 3.3 V, 2.5 V, and 1.8 V operation. It combines programmable logic, nonvolatile configuration storage, and deterministic I/O in one device, making it suitable for compact control, interface, and signal-generation systems. The -5 suffix denotes the stated 5 ns speed grade, while -T44I identifies the 44-pin industrial-temperature ordering configuration. A CPLD is a user-programmable digital logic device that stores a logic configuration in nonvolatile memory. In the semiconductor hierarchy, a CPLD belongs to programmable logic devices and uses interconnected macrocells to implement Boolean and sequential functions. Compared with a software-driven processor, an LC4032B implementation can execute fixed logic immediately after configuration, while compared with a small FPGA it is organized around a simpler macrocell architecture suited to compact glue logic. The verified LC4032B data identifies 32 macrocells, 5 ns timing, and a 44-TQFP package as the principal selection parameters. The family description also supports 3.3 V, 2.5 V, and 1.8 V operating environments. In-system programmability permits a design to be configured or updated through its programming path without removing the package from production equipment, provided the board meets the device's stated electrical and pin requirements. Typical uses include industrial control interfaces, peripheral bus decoding, data acquisition front ends, programmable instrument logic, communication-interface conditioning, and embedded control functions. Its fixed nonvolatile configuration supports repeatable startup behavior because no firmware-driven configuration sequence is required for established logic. Design work should begin with the manufacturer datasheet because macrocell capacity, dedicated pins, supported I/O standards, timing, power behavior, and programming requirements are not completely characterized by the provided search results. Confirm that every external signal, supply rail, pull state, and programming connection matches the exact datasheet before releasing a PCB. This page consolidates the verified distributor identification, available source links, package details, and engineering-selection context. It also distinguishes confirmed facts from missing specifications so procurement and design teams can assess fit without relying on unsupported inferred values.