SN65LVDS105PWRG4 vs SN65LVDS105PWR Perbandingan
Perbandingan bersamaan detil SN65LVDS105PWRG4 dari Texas Instruments dan SN65LVDS105PWR dari Texas Instruments. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ Akhir HidupPerbandingan Spesifikasi
| Parameter Umum | SN65LVDS105PWRG4 | SN65LVDS105PWR |
|---|---|---|
| Merek | Texas Instruments | Texas Instruments |
| Kategori | Clock & Timing | Clock & Timing |
| Status Lingkungan Hidup | Akhir Hidup | Aktif |
| Fungsi | 1 LVTTL to 4 LVDS clock fanout buffer / repeater | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Configuration | 1 x 1:4 Channel | — |
| Input Type | LVTTL | LVTTL (single-ended) |
| Tipe Output | LVDS (4 differential pairs) | LVDS (differential), 4 pairs |
| Max Data Rate | 400 Mbps | — |
| Supply Voltage Range | 3 V to 3.6 V | — |
| Typical Propagation Delay | 2.2 ns | — |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load | — |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) | — |
| Bus-Terminal ESD Rating | Exceeds 12 kV | — |
| Paket | TSSOP-16 (PW), 5 mm x 6.4 mm | 16-TSSOP (PW) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) | — |
| Kategori | Interface - Signal Buffers, Repeaters, Splitters | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Status RoHS | [DATA_NEEDED: RoHS status] | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Status Lingkungan Hidup | Discontinued at Digi-Key | — |
| Laju Data | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Tegangan Pemuat | — | 3 V to 3.6 V (typical 3.3 V) |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Kanal | — | 1 x 1:4 |
| Technology | — | LVDS differential signaling |
| Arus Memerintah | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |