SN65LVDS105PWRG4 vs SN65LVDS105PWR Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng SN65LVDS105PWRG4 sa pamamagitan ng Texas Instruments at SN65LVDS105PWR sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ Tapus ng BuhayTexas Instruments
SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWR ✓ NakahandaPagsanggunian na paghahambing
| Parametro | SN65LVDS105PWRG4 | SN65LVDS105PWR |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | Clock & Timing | Clock & Timing |
| Katayuan ng Lifecycle | Tapus ng Buhay | Aktibo |
| Fungsi | 1 LVTTL to 4 LVDS clock fanout buffer / repeater | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Configuration | 1 x 1:4 Channel | — |
| Input Type | LVTTL | LVTTL (single-ended) |
| Type ng Output | LVDS (4 differential pairs) | LVDS (differential), 4 pairs |
| Max Data Rate | 400 Mbps | — |
| Supply Voltage Range | 3 V to 3.6 V | — |
| Typical Propagation Delay | 2.2 ns | — |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load | — |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) | — |
| Bus-Terminal ESD Rating | Exceeds 12 kV | — |
| Packhaging | TSSOP-16 (PW), 5 mm x 6.4 mm | 16-TSSOP (PW) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) | — |
| Kategorya | Interface - Signal Buffers, Repeaters, Splitters | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Katayuan ng Lifecycle | Discontinued at Digi-Key | — |
| Rate ng Data | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Volte ng Pagbibigay | — | 3 V to 3.6 V (typical 3.3 V) |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Mga Channels | — | 1 x 1:4 |
| Technology | — | LVDS differential signaling |
| Kuru-kuryente ng Kapayapaan | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |