SN65LVDS105PWRG4 vs SN65LVDS105PWR Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci SN65LVDS105PWRG4 disebabkan oleh Texas Instruments dan SN65LVDS105PWR disebabkan oleh Texas Instruments. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ Akhir HayatPengandingan Spesifikasi
| Parametr | SN65LVDS105PWRG4 | SN65LVDS105PWR |
|---|---|---|
| Merek | Texas Instruments | Texas Instruments |
| Kategori | Clock & Timing | Clock & Timing |
| Status Lingkungan Hidup | Akhir Hidup | Aktif |
| Fungsi | 1 LVTTL to 4 LVDS clock fanout buffer / repeater | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Configuration | 1 x 1:4 Channel | — |
| Input Type | LVTTL | LVTTL (single-ended) |
| Jenis Output | LVDS (4 differential pairs) | LVDS (differential), 4 pairs |
| Max Data Rate | 400 Mbps | — |
| Supply Voltage Range | 3 V to 3.6 V | — |
| Typical Propagation Delay | 2.2 ns | — |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load | — |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) | — |
| Bus-Terminal ESD Rating | Exceeds 12 kV | — |
| Kemasan | TSSOP-16 (PW), 5 mm x 6.4 mm | 16-TSSOP (PW) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) | — |
| Kategori | Interface - Signal Buffers, Repeaters, Splitters | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Status RoHS | [DATA_NEEDED: RoHS status] | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Status Lingkungan Hidup | Discontinued at Digi-Key | — |
| Kadar Data | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Tegangan Pemberi Arus | — | 3 V to 3.6 V (typical 3.3 V) |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Salur | — | 1 x 1:4 |
| Technology | — | LVDS differential signaling |
| Arus Dalam Tentera | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |