10AS057K3F35E2LG - 570K LE Arria 10 SX SoC FPGA | Intel
MPN: 10AS057K3F35E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3650 | $36,500.00 |
| 100 | $3420 | $342,000.00 |
| 500 | $3190 | $1,595,000.00 |
| 1,000 | $2950 | $2,950,000.00 |
Drop-in alternatives for 10AS057K3F35E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35E2LG
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View Datasheet →10AS057K3F35E2SG
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View Datasheet →10AS057K3F35E2SG
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View Datasheet →10AS066K3F35E2LG
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View Datasheet →10AS048K3F35E2LG
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View Datasheet →10AS057K4F35E2LG
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10AS057K3F35E2LG Maximum Ratings & Electrical Characteristics
| Device Family | Arria 10 SX |
| Product Type | System-on-Chip (SoC) FPGA |
| Logic Elements | 570,000 |
| Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Processor Clock | 1.5 GHz |
| Process Node | 20 nm |
| Core Voltage | 0.9 V |
| User I/O Count | 396 |
| Package | 1152-pin FCBGA, F35 (35x35 mm) |
| Speed Grade | K3 |
| Device Designation | E2 |
| Mounting Type | Surface Mount (BGA) |
| Terminal Pitch | 1.0 mm |
| RoHS Status | Compliant |
| Hard Processor System | Yes - ARM Cortex-A9 MPCore |
10AS057K3F35E2LG 1152-pin fcbga, f35 (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS057K3F35E2LG (1152-pin fcbga, f35 (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K3F35E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K3F35E2LG is suitable for 6 applications: Wireless Base-Station Digital Front-End, Medical Imaging Accelerator, Broadcast Video Processing, Industrial Motor Control, Test & Measurement Instrumentation, Aerospace Avionics & UAV Payloads.
Wireless Base-Station Digital Front-End
The 10AS057K3F35E2LG's 570K logic elements and integrated multi-gigabit transceivers deliver the DSP throughput required for CPRI/OBSAI fronthaul and baseband processing. Its dual ARM Cortex-A9 cores handle Layer-2/3 protocol stacks and timing-critical Ethernet bridging while the FPGA fabric implements crest-factor reduction, digital pre-distortion, and FFT/iFFT pipelines. The 396 user I/Os provide ample connectivity for radio cards, antenna interfaces, and backhaul links, while the 20 nm process keeps power dissipation manageable in thermally constrained radio units. A single SoC replaces an external processor + FPGA + glue logic, reducing BOM cost and PCB area. Reference designs in the Altera/Intel Baseband Function Library accelerate development.
Recommended
Medical Imaging Accelerator
The 10AS057K3F35E2LG is well suited to medical imaging accelerators (ultrasound beamforming, CT reconstruction, MRI gradient control) because the FPGA fabric delivers the parallel arithmetic needed for FFT, FIR filtering, and back-projection while the HPS runs the patient UI, network stack, and DICOM transfer. The integrated ARM Cortex-A9 MPCore with NEON accelerates image preprocessing and JPEG2000 compression at line rate. The 1.5 GHz HPS clock supports responsive multi-tasking under a Linux medical stack. The F35 1152-ball FCBGA gives enough I/O for high-channel-count ultrasound probes and high-resolution video outputs, while the 20 nm node keeps power within thermal envelopes for cart-mounted systems.
Recommended
Broadcast Video Processing
The 10AS057K3F35E2LG's 570K logic elements and high-speed transceivers make it a strong fit for broadcast video routers, multiviewers, and SDI-to-IP gateways. The FPGA fabric handles uncompressed 12G-SDI cross-points, HDR/WCG conversion, and audio embedding at multi-channel scale, while the HPS runs control software and Ember+ / NMOS IS-04/05 networking. The 396 user I/Os accommodate many SDI ports, reference timing inputs, and 10/25 GbE SFP cages, reducing the need for external crosspoint chips. SmartVID power management keeps a 4U router frame within thermal limits. The 20 nm process provides timing closure headroom for 12G-SDI at the K3 speed grade.
Recommended
Industrial Motor Control
For multi-axis servo drives and industrial robots, the 10AS057K3F35E2LG pairs the dual ARM Cortex-A9 cores for EtherCAT / PROFINET master stacks with FPGA logic implementing field-oriented control, SVPWM, and current-loop computation at microsecond rates. Its 396 user I/Os accept multiple encoder inputs (EnDat, BiSS, SSI), Hall sensors, and PWM outputs, reducing the need for external decoder ASICs. The 1.5 GHz HPS supports real-time Linux with PREEMPT_RT for deterministic control loops. The F35 FCBGA's high I/O count and high-speed transceivers enable daisy-chained multi-axis communication and integrated functional safety logic per IEC 61508 SIL-2/3 paths.
Recommended
Test & Measurement Instrumentation
The 10AS057K3F35E2LG integrates an FPGA fabric and ARM Cortex-A9 cores in a single package, ideal for mixed-signal instruments and protocol analyzers. The FPGA implements real-time DSP for ADC/DAC data paths, FFT-based spectrum analysis, and protocol-aware triggering, while the HPS handles UI rendering, USB/LAN connectivity, and SCPI command parsing at multi-MHz rates. Its multi-gigabit transceivers support 10 GbE streaming capture for protocol analyzers, and the 396 user I/Os accommodate many LVDS or LVCMOS channels. The 20 nm process helps meet aggressive channel-count targets without exceeding rack-unit thermal budgets, while the F35 package footprint is shared across the Arria 10 family.
Recommended
Aerospace Avionics & UAV Payloads
The 10AS057K3F35E2LG's ARM Cortex-A9 cores plus FPGA fabric enable compact avionics subsystems for UAVs and flight-control computers, where weight, power, and footprint are critical. The HPS runs inertial navigation, mission management, and C2 link encryption while the FPGA implements sensor-fusion DSP, MIL-STD-1553 / ARINC 429 interfaces, and discrete I/O expansion. The 396 user I/Os allow direct connection to multiple IMUs, GPS receivers, and payload sensors without external bus expanders. The 20 nm process provides high reliability under vibration, and the industrial temperature grade supports avionics bay environments. The F35 FCBGA package simplifies mechanical integration into sealed enclosures.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K3F35E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35E2LG | 10AS057K3F35E2SG | 10AS066K3F35E2LG | 10AS048K3F35E2LG | 10AS057K4F35E2LG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-pin FCBGA, F35 (35x35 mm) | 1152-pin FCBGA, F35 (35x35 mm) - same | 1152-pin FCBGA, F35 (35x35 mm) - same | 1152-pin FCBGA, F35 (35x35 mm) - same | 1152-pin FCBGA, F35 (35x35 mm) - same | 1152-pin FCBGA, F35 (35x35 mm) - same |
| Device Family | Arria 10 SX | Arria 10 SX - same | Arria 10 SX - same | Arria 10 SX - same | Arria 10 SX - same | Arria 10 SX - same |
| Logic Elements | 570,000 | 570,000 | 570,000 | 660,000 | 480,000 | 570,000 |
| Speed Grade | K3 | K2 (slower) | K3 - same | K3 - same | K3 - same | K4 (faster) |
| Processor Cores | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore |
| Maximum Processor Clock | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Process Node | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| User I/O Count | 396 | 396 | 396 | 396 | 396 | 396 |
Key Differentiators
- K3 speed grade within the same die/package, no PCB rework required (vs 10AS057K2F35E2LG)
- Higher 570K LE density within the F35 footprint (vs 10AS048K3F35E2LG)
- Cost-down vs 660K LE while preserving all peripheral mix (vs 10AS066K3F35E2LG)
- Integrated dual ARM Cortex-A9 HPS eliminates external processor (vs Discrete FPGA + external ARM SoC)
Design Notes
The Arria 10 SX requires multiple independent voltage rails: a 0.9 V core supply (SmartVID), 1.1 V/1.2 V for transceivers, 1.8 V/2.5 V/3.3 V for I/O banks, and a dedicated HPS rail. Use a PMBus-controlled PMIC such as the Intel Enpirion EM11/EM12 family to meet SmartVID sequencing requirements. Place decoupling capacitors as close as possible to each rail pin per the pin connection guidelines, and ensure the SmartVID interface is properly tied to the PMIC for adaptive voltage scaling.
The 1152-ball F35 FCBGA dissipates significant power under full fabric + HPS load, so a multi-layer PCB with a continuous ground plane and thermal vias under the BGA is mandatory. Estimate: a fully utilized 570K-LE design at high toggle rate typically consumes 15-20 W from the FPGA core plus 2-5 W from the HPS; without a heatsink or top-side cooling, junction temperature can exceed 100 C in still air. Use the Intel PowerPlay Early Power Estimator (EPE) and Thermal Calculator for your specific utilization before finalizing thermal design.
The 35x35 mm F35 package has 1.0 mm ball pitch; per the verified web data, all 1152 balls are populated. Use microvia stack-ups (any-layer HDI recommended) with via-in-pad for signal escape, controlled-impedance routing for transceiver lanes (100 ohm differential), and matched-length tuning on HPS memory interface traces to DDR3/DDR4. Reference the Arria 10 SX device handbook pin connection guidelines for per-bank supply, reference voltage, and decoupling requirements; never leave unused transceiver channels floating - tie to GND through 6.8 kohm pull-downs.
Common Arria 10 SX design mistakes: (1) forgetting to power the HPS independently from the FPGA fabric - both rails must ramp in the correct sequence per SmartVID; (2) using the wrong JTAG chain configuration when the HPS debug port is included - include both FPGA and HPS in the scan chain; (3) under-estimating configuration memory capacity for bitstream compression - enable Arria 10 bitstream compression to fit large designs in cheaper EPCQ devices; (4) neglecting the MSL-3 moisture sensitivity for F35 FCBGA - bake before reflow if the sealed bag is opened beyond the floor-life tracker.
Compliance Information
RoHS and lead-free compliance per the verified DigiKey product listing. Not AEC-Q100 qualified - this part targets industrial, medical, broadcast, and avionics applications where AEC-Q100 is not required. Halogen-free status was not present in the verified data and is recorded as unknown.
