10AS066K3F35E2LG - Arria 10 SX 660K LE SoC FPGA 1152-FBGA | Intel
MPN: 10AS066K3F35E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2710 | $27,100.00 |
| 100 | $2580 | $258,000.00 |
| 500 | $2450 | $1,225,000.00 |
| 1,000 | $2310 | $2,310,000.00 |
Drop-in alternatives for 10AS066K3F35E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS066K3F35E2SG
✅ Drop-In✓ In Stock
$2950 / Unit
View Datasheet →10AS066K3F35I2LG
✅ Drop-In✓ In Stock
$3712.06 / Unit
View Datasheet →10AS066K3F35E1HG
✅ Drop-In📋 Reference alternative (not in catalog)
10AS066K2F35E2LG
✅ Drop-In✓ In Stock
$3360 / Unit
View Datasheet →10AS066K2F35E2SG
✅ Drop-In✓ In Stock
$2890 / Unit
View Datasheet →10AS066K2F35I2SG
✅ Drop-In✓ In Stock
$5750 / Unit
View Datasheet →10AS066K2F35I2LG
✅ Drop-In✓ In Stock
$5650.15 / Unit
View Datasheet →10AS066K3F35E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Process Technology | 20 nm |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| Core Voltage | 0.9 V |
| Speed Grade | -E2 |
| Package | 1152-ball FCBGA, 35 mm x 35 mm |
| Package Code | F35 |
| User I/Os | 396 |
| Memory Cells (per snippet) | 660,000 cells (LE equivalent) |
| On-chip Memory | 256 KB (per FindIC snippet) |
| Configuration Scheme | FPP, AS supported |
| Temperature Grade | Industrial |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant (per FindIC listing) |
10AS066K3F35E2LG f35 Pin Configuration Guide
Complete pinout information for 10AS066K3F35E2LG (f35 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K3F35E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K3F35E2LG is suitable for 6 applications: Software-Defined Radio (SDR) Baseband, Military Radar Signal Processing, Medical Imaging (Ultrasound / CT Front-End), Industrial Machine Vision, High-Performance Test & Measurement, 5G / Wireless Baseband Processing.
Software-Defined Radio (SDR) Baseband
The 10AS066K3F35E2LG is well-suited to SDR baseband processing because its dual-core ARM Cortex-A9 HPS running up to 1.5 GHz handles protocol stacks, control-plane processing, and Linux/RTOS execution, while the 660K-LE FPGA fabric delivers parallel DSP for FFTs, channelization, and modulation/demodulation at sample rates beyond the reach of general-purpose DSPs. Arria 10 SX transceivers support multi-gigabit links to JESD204B/C data converters and RF front ends, enabling a single-chip implementation of multi-channel SDR platforms. Compared with a discrete CPU + FPGA solution, the SoC integration reduces board area, inter-chip latency, and BOM cost.
Recommended
Military Radar Signal Processing
In phased-array radar systems, the 10AS066K3F35E2LG's 660K logic elements provide massive parallel compute for pulse compression, MTI filtering, and digital beamforming across hundreds of antenna elements. The hardened ARM Cortex-A9 subsystem executes tracker and control-plane algorithms in real time. Multi-gigabit transceivers stream digitized antenna data to/from ADC/DAC devices, while industrial temperature grade supports ruggedized deployments. Per Arria 10 SX product literature, this density tier balances DSP throughput and power for medium-range surveillance and fire-control radar.
Recommended
Medical Imaging (Ultrasound / CT Front-End)
The 10AS066K3F35E2LG supports multi-channel beamforming in ultrasound and CT imaging systems. The 660K-LE FPGA fabric processes 64-128 channels of digitized RF in parallel for delay-and-sum beamforming, while the ARM Cortex-A9 HPS handles user interface, image reconstruction, and DICOM networking. On-chip memory and DDR4 controller support high-bandwidth data movement without external memory bottlenecks. The 20 nm process and integrated SoC reduce power and footprint versus older dual-FPGA ultrasound architectures, enabling portable diagnostic cart designs.
Recommended
Industrial Machine Vision
For high-speed industrial inspection lines, the 10AS066K3F35E2LG ingests multi-gigabit pixel streams from Camera Link, CoaXPress, or GigE Vision cameras through its transceivers, performs real-time image processing (filtering, segmentation, defect detection) in the FPGA fabric, and uses the ARM Cortex-A9 subsystem for line-control communication, HMI, and rejection decisions. The 396 user I/Os allow direct connection to encoders, lighting controllers, and PLCs without bridge logic. Industrial temperature grade and long-term Intel product support suit 24/7 factory-floor operation.
Recommended
High-Performance Test & Measurement
The 10AS066K3F35E2LG powers next-generation oscilloscopes, protocol analyzers, and BERT platforms where the FPGA fabric handles real-time waveform processing, eye-diagram rendering, and trigger logic at multi-GS/s rates. The integrated ARM HPS runs the instrument's GUI, measurement firmware, and remote-control interfaces (LXI, USBTMC). Tight FPGA-to-HPS coupling minimizes data-movement latency for segmented capture and deep-memory triggers. The 20 nm Arria 10 process gives deterministic timing margin required for measurement-grade instruments.
Recommended
5G / Wireless Baseband Processing
In small-cell and macro baseband units, the 10AS066K3F35E2LG implements PHY-layer functions (channel coding, MIMO detection, FFT/iFFT) in the FPGA fabric while the dual ARM Cortex-A9 cores run MAC scheduling and OAM stacks under Linux. Multiple CPRI or eCPRI fronthaul links are supported via the integrated transceivers, and the DDR4 controller handles high-bandwidth data movement between PHY buffers and upper layers. SoC integration reduces the bill of materials and power versus discrete ASSP + FPGA designs.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K3F35E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K3F35E2SG | 10AS066K3F35I2LG | 10AS066K3F35E1HG | 10AS066K2F35E2LG | 10AS066K2F35E2SG |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA F35 (35x35 mm) | 1152-FBGA F35 (35x35 mm) - same | 1152-FBGA F35 (35x35 mm) - same | 1152-FBGA F35 (35x35 mm) - same | 1152-FBGA F35 (35x35 mm) - same | 1152-FBGA F35 (35x35 mm) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 |
| Speed Grade | -E2 | -E2 | -I2 (industrial) | -E1 (faster) | -E2 | -E2 |
| Feature Tier | K3 (max transceiver / hardened IP) | K3 | K3 | K3 | K2 (reduced) | K2 (reduced) |
| Ball Finish | Pb-free (G suffix) | SnPb (S suffix) | Pb-free (G suffix) | Pb-free (G suffix) | Pb-free (G suffix) | SnPb (S suffix) |
| Temperature Grade | Industrial (E suffix) | Industrial | Industrial | Extended industrial | Industrial | Industrial |
| Approx Unit Price (qty 1, USD) | 2850.00 | Similar (legacy SnPb) | Similar | Higher (~10-15% premium for -E1) | Lower (~10-20% K2 discount) | Lower (~10-20% K2 discount) |
Key Differentiators
- Maximum K3-tier hardened IP and transceiver count in the 660K-LE density (vs 10AS066K2F35E2LG)
- Mid-tier -E2 speed grade balances timing margin and cost (vs 10AS066K3F35E1HG)
- Pb-free (RoHS-compliant) ball finish for new designs (vs 10AS066K3F35E2SG)
Design Notes
The 10AS066K3F35E2LG requires multiple supply rails (core 0.9 V, HPS core, HPS I/O, FPGA I/O banks, transceiver, and auxiliary) with strict power-up and power-down sequencing. Per Altera's Arria 10 pin connection guidelines, use an Intel-recommended power management IC such as the Enpirion EM11Z or equivalent multi-rail controller with PG signals tied back to CONF_DONE. Sequencing violations can cause inrush currents above the FPGA's tolerance and risk long-term reliability degradation.
Estimated: At full fabric utilization (~80%) and ~250K logic elements toggling at 250 MHz, the FPGA core can dissipate 8-12 W; the HPS at 1.5 GHz adds another 3-5 W; transceivers at full lane utilization add 1-2 W. The 1152-FBGA F35 package has a typical theta_JA around 8-10 C/W with proper 12-layer PCB and thermal vias under the heat slug. A heatsink with 1-2 C/W thermal resistance and 200 LFM airflow is recommended for industrial-grade deployment; use Arria 10 thermal models in Quartus PowerPlay for accurate per-design estimation.
The 1152-FBGA F35 footprint (35 mm x 35 mm, 1.0 mm ball pitch) requires an HDI PCB stack-up with laser-drilled microvias and at least 8 layers for signal integrity. Match length on DDR4 channels per the Arria 10 EMIF specification. Provide a full ground plane under the BGA with stitched ground vias on the thermal ball array for thermal dissipation. Reference the Arria 10 SoC Development Kit PCB layout files as a starting point.
Do not omit the configuration flash memory or attempt to use a different MSL level than the package specifies - BGA packages are moisture sensitive and require controlled storage and reflow profiles per IPC/JEDEC J-STD-020. Per Intel documentation, leaving MSEL pins in the wrong state during power-up will prevent configuration. Always validate the HPS boot ROM source (SD/eMMC/QSPI) using the Intel SoC EDS bootloader configuration tool before silicon bring-up.
Compliance Information
RoHS and lead-free confirmed by 'G' suffix per Altera/Intel package naming convention. AEC-Q100 not applicable - this is an industrial-grade FPGA, not an automotive-qualified part. For automotive designs consider Cyclone V or Arria 10 Auto variants instead.
