10AS057K3F35I2LG - Arria 10 SX SoC FPGA 570K LE | Intel
MPN: 10AS057K3F35I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4200 | $4,200.00 |
| 10 | $3950 | $39,500.00 |
| 100 | $3700 | $370,000.00 |
| 500 | $3450 | $1,725,000.00 |
| 1,000 | $3200 | $3,200,000.00 |
Drop-in alternatives for 10AS057K3F35I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K3F35E2LG
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View Datasheet →10AS057K3F35I2SG
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View Datasheet →10AS057K2F35I2LG
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View Datasheet →10AS057K3F35E2SG
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View Datasheet →10AS048K3F35I2LG
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View Datasheet →10AS057K2F35I2SG
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View Datasheet →10AS057K3F35I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Device Variant | 10AS057 |
| Logic Elements | 570,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | 1.5 GHz |
| Speed Grade | -3 |
| Package | 1152-ball FC-FBGA, 35x35 mm |
| Package Code | F35 |
| Operating Temperature | -40C to +100C (Industrial) |
| Temperature Grade | I (Industrial) |
| Mounting Type | Surface Mount (BGA) |
| Configuration Method | Active Serial / JTAG |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS057K3F35I2LG f35 Pin Configuration Guide
Complete pinout information for 10AS057K3F35I2LG (f35 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K3F35I2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K3F35I2LG is suitable for 7 applications: Wireless Baseband Processing, Military Radar and Electronic Warfare, Industrial Machine Vision, Test and Measurement Backplane, High-Throughput Data Acquisition, Aerospace Communications and Avionics, Video Broadcast and Processing.
Wireless Baseband Processing
The 10AS057K3F35I2LG's 570K logic elements and embedded DSP blocks deliver the throughput required for LTE and 5G NR physical-layer baseband processing. The dual-core ARM Cortex-A9 HPS handles MAC-layer scheduling and RF control loops while the FPGA fabric accelerates FFT, channel estimation, and turbo/LDPC decoding. Industrial temperature rating permits outdoor small-cell deployment.
Recommended
Military Radar and Electronic Warfare
The industrial-temperature, 570K-LE Arria 10 SX FPGA in F35 FC-FBGA is suited for prototype radar pulse compression, beamforming, and EW receiver designs. On-chip DSP blocks accelerate FFT and chirp-Z transforms at sample rates above 200 MSPS, while hardened transceivers link to ADCs and DACs at multi-Gbps rates. Industrial grade supports harsh airborne and naval enclosures.
Recommended
Industrial Machine Vision
The 10AS057K3F35I2LG pairs a dual-core Cortex-A9 HPS for vision software frameworks (OpenCV, HALCON) with FPGA fabric for image preprocessing, feature extraction, and convolutional inference. Industrial temperature operation enables deployment on factory floors and outdoor inspection rigs where ambient temperature swings exceed commercial ranges. The HPS peripherals accelerate GigE Vision and USB3 Vision ingest.
Recommended
Test and Measurement Backplane
The 10AS057K3F35I2LG suits modular instruments where the FPGA aggregates data from multiple ADC/DAC channels while the Cortex-A9 HPS runs Linux for display, networking, and SCPI control. PCI Express hard IP and multi-gigabit transceivers allow the instrument to plug into PXIe or proprietary backplanes. Industrial temperature grade supports 24/7 production-line test.
Recommended
High-Throughput Data Acquisition
The 10AS057K3F35I2LG ingests multi-GSPS ADC streams via its hardened transceivers and routes them through DSP blocks for real-time decimation, FFT, and triggering. The HPS manages disk storage, Ethernet streaming, and user interface. Industrial temperature rating and -3 speed grade make this variant suitable for oil-and-gas exploration and scientific instrumentation.
Recommended
Aerospace Communications and Avionics
The 10AS057K3F35I2LG with industrial temperature grade and 570K LE fabric enables airborne communications modems, ARINC 429/664 bridges, and flight-data recorders. The Cortex-A9 HPS runs DO-178 certifiable stacks, while the FPGA implements custom waveform processing and MIL-STD-1553 interfaces. The F35 FC-FBGA package survives high-vibration environments with proper PCB underfill.
Recommended
Video Broadcast and Processing
The 10AS057K3F35I2LG's 570K logic elements and DSP blocks accelerate HEVC/H.265 encoding, de-interlacing, and color-space conversion in broadcast encoder/decoder platforms. HDMI 2.0 and 12G-SDI ingest flow through hardened transceivers, while the HPS runs control software and web UIs. Industrial temperature operation supports 24/7 rack-mount chassis.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K3F35I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K3F35E2LG | 10AS057K3F35I2SG | 10AS057K2F35I2LG | 10AS048K3F35I2LG |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FC-FBGA F35 (35x35 mm) | 1152-ball FC-FBGA F35 (35x35 mm) | 1152-ball FC-FBGA F35 (35x35 mm) | 1152-ball FC-FBGA F35 (35x35 mm) | 1152-ball FC-FBGA F35 (35x35 mm) |
| Logic Elements | 570,000 | 570,000 | 570,000 | 570,000 | 480,000 |
| Speed Grade | -3 | -3 | -3 | -2 | -3 |
| Temperature Grade | Industrial (-40C to +100C) | Extended Commercial | Military | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| HPS Max Frequency | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.4 GHz (estimated, lower speed grade) | 1.5 GHz |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes |
| Estimated 1k Price (USD) | 3200 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Heterogeneous SoC with integrated dual ARM Cortex-A9 (vs Plain FPGA (e.g. 10AX057K3F35I2LG without HPS))
- Industrial temperature grade at speed grade -3 (vs 10AS057K2F35I2LG (speed grade -2))
- Mid-density 570K-LE balance vs 660K-LE variant (vs 10AS066K3F35I2LG)
Design Notes
Arria 10 SX SoC FPGAs at -3 speed grade can dissipate 15-25 W in high-utilization designs; the 35x35 mm F35 FC-FBGA requires a high-performance thermal solution. Attach a heatsink with thermal-interface material rated for the -40C to +100C industrial envelope, and consider forced-air cooling or a cold plate for fanless enclosures above 8 W steady-state dissipation. The exposed-die flip-chip BGA does not support PCB-bottom-side cooling without custom heat spreaders.
The 1152-ball FC-FBGA F35 (0.8 mm or 1.0 mm pitch, verify exact pitch in datasheet) requires a high-density-interconnect PCB stack-up with laser-drilled microvias, sequential lamination, and matched-length routing for the HPS DDR3/DDR4 interface. Use the Arria 10 SX pin-out file from Intel to plan escape routing and split references between HPS and FPGA power rails. Maintain at least four PCB layers for the core fabric with continuous ground planes for return-path integrity.
Decouple every transceiver and HPS power pin with the capacitor values specified in the Arria 10 SX device datasheet (typically 0.1 uF + 1 uF + 10 uF per supply). Use a sequenced power-supply scheme (TPS65086x or equivalent) to ensure the 0.9 V core, 1.1 V HPS, 1.8 V I/O, and 2.5 V/3.3 V auxiliary rails ramp in the order required by Quartus Prime configuration files to avoid in-rush latch-up.
Estimated: a common pitfall is using speed-grade -3 marketing material as a guaranteed Fmax - actual timing closure at industrial temperature and the chosen VCC core voltage must be verified in Quartus Prime Slow 1100 mV / 0.9 V / -40C corner. Another frequent mistake is assuming the HPS and FPGA can boot independently; configure both images in the QSPI flash with proper boot-header so the HPS can reconfigure the FPGA on partial-update events.
Compliance Information
RoHS and conflict-minerals status confirmed by Intel product page; AEC-Q100 not applicable for non-automotive FPGA; REACH and halogen-free status not explicitly stated in verified web data.
