10AX115N2F40I2SG - Arria 10 GX FPGA, 1.15M LEs, 1517-FCBGA | Intel
MPN: 10AX115N2F40I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4610 | $46,100.00 |
| 100 | $4280 | $428,000.00 |
| 500 | $3990 | $1,995,000.00 |
| 1,000 | $3750 | $3,750,000.00 |
Drop-in alternatives for 10AX115N2F40I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115N2F40I1SG
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$3720 / Unit
View Datasheet →10AX115N2F40I2LG
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View Datasheet →10AX115N2F40E2LG
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View Datasheet →10AX115N2F40E1SG
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View Datasheet →10AX115N1F40I1SG
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View Datasheet →10AX115N2F40I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory Bits | 68,857,856 |
| Adaptive Logic Modules (ALMs) | 427,200 |
| Registers | 1,708,800 |
| User I/O | 600 |
| Transceiver Protocol | GX (up to 14.1 Gbps) |
| DSP Blocks | Variable-precision, hard floating-point |
| Package | 1517-ball FCBGA, 40 x 40 mm, 1.0 mm pitch |
| Operating Temperature | -40C to +100C (Industrial) |
| Speed Grade | 2 |
| Process Technology | TSMC 20 nm |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (flip-chip BGA) |
10AX115N2F40I2SG 1517-ball fcbga, 40 x 40 mm, 1.0 mm pitch Pin Configuration Guide
Complete pinout information for 10AX115N2F40I2SG (1517-ball fcbga, 40 x 40 mm, 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115N2F40I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115N2F40I2SG is suitable for 6 applications: 100G Ethernet MAC/PCS/FEC Bridge, 4K/UHD Video Broadcast Processing, Radar and Electronic Warfare DSP, PCIe Gen3 Accelerator Card, OTN/SDH Telecom Framer, Industrial Imaging and Machine Vision.
100G Ethernet MAC/PCS/FEC Bridge
The 10AX115N2F40I2SG's 1.15M logic elements and integrated 14.1 Gbps GX transceivers make it well-suited for 100G Ethernet bridge designs. In a typical pipeline the FPGA implements the 100G MAC, PCS layers (CAUI-4 / 100GBASE-R4), and Reed-Solomon forward error correction, with up to 600 user I/Os available for parallel fabric interfacing to ASICs, network processors, or QSFP28 cages. Compared with smaller Arria 10 variants, the 1150K-LE fabric provides the headroom needed for an integrated FEC engine alongside the MAC/PCS, eliminating the need for an external FEC co-processor and reducing bill of materials.
Recommended
4K/UHD Video Broadcast Processing
Arria 10 GX devices are widely deployed in broadcast infrastructure for SMPTE ST 2022-6/2059 and ST 2110 IP-based video. The 10AX115N2F40I2SG can sustain multiple 12G-SDI or quad-link 3G-SDI channels while performing frame synchronisation, HDR conversion, and audio embedding in fabric. Its variable-precision DSP blocks accelerate chroma upsampling and color-space conversion, and the hard PCI Express Gen3 IP enables direct transfer of uncompressed video into GPU or capture cards. Industrial temperature grading suits outside-broadcast and ruggedized environments.
Recommended
Radar and Electronic Warfare DSP
Defense radar and electronic-warfare systems require thousands of multiply-accumulate operations per clock cycle for pulse compression, FFT, and digital-beamforming. The Arria 10 GX variable-precision DSP blocks, rated up to 1.5 TFLOPs (FP16) per device, deliver the arithmetic density needed for multi-channel phased-array processing. The 10AX115N2F40I2SG's 600 user I/Os connect to multiple ADC/DAC lanes and LVDS sensor interfaces, while the GX transceivers stream pre-processed data to back-end processors via 10G/40G links.
Recommended
PCIe Gen3 Accelerator Card
The Arria 10 GX 10AX115N2F40I2SG integrates hard PCI Express Gen3 x8 endpoint IP, simplifying accelerator-card designs that pair the FPGA with a host CPU over PCIe. The FPGA acts as a coprocessor for inference, data compression, or financial workloads, with onboard DDR4 controllers (via external memory interfaces) supplying the bandwidth the host CPU cannot deliver. Compared with soft PCIe cores, the hard IP block saves ~30K logic elements and reduces latency by hundreds of nanoseconds.
Recommended
OTN/SDH Telecom Framer
Optical Transport Network (OTN) and legacy SDH/SONET framers map client traffic into OTU/ODU containers with multi-stage multiplexing and forward error correction. The 10AX115N2F40I2SG's 14.1 Gbps GX transceivers support OTU2e/OTU3/OTU4 client rates, and the large logic capacity absorbs OTN ODU0/ODUflex/ODU4 multiplexing and GFP mapping. Industrial temperature operation and the flip-chip BGA's thermal performance suit outdoor telecom line-card environments.
Recommended
Industrial Imaging and Machine Vision
Multi-camera machine-vision pipelines stream CoaXPress, Camera Link, or GigE Vision data into the 10AX115N2F40I2SG, where the FPGA performs Bayer demosaicing, lens distortion correction, and feature extraction in real time. The variable-precision DSP blocks accelerate convolutional filters and neural-network inference for vision-guided robotics, and the 600 user I/Os accept data from up to 8 Camera Link cameras simultaneously. Industrial temperature grading allows deployment in factory automation cells without active cooling.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115N2F40I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115N2F40I1SG | 10AX115N2F40I2LG | 10AX115N2F40E2LG | 10AX115N2F40E1SG | 10AX115N1F40I1SG | 10AX115N1F40E1SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1517-FCBGA (F40) | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | 2 | 1 (faster) | 2 | 2 | 1 | 1 | 1 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Extended (0C to +100C) | Extended (0C to +100C) | Industrial (-40C to +100C) | Extended (0C to +100C) |
| Embedded Memory Bits | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 | 68,857,856 |
| User I/O | 600 | 600 | 600 | 600 | 600 | 600 | 600 |
| Transceiver Tier | N2 | N2 | N2 | N2 | N2 | N1 (lower) | N1 (lower) |
Key Differentiators
- Speed grade 2 vs speed grade 1 - balances Fmax and price (vs 10AX115N2F40I1SG)
- Industrial temperature grading with -40C operation (vs 10AX115N2F40E2LG)
- N2 transceiver tier - higher transceiver count than N1 (vs 10AX115N1F40I1SG)
Design Notes
The 1517-ball FCBGA at 1.0 mm pitch requires via-in-pad (VIPPO) or dog-bone fanout with a 0.8/0.4 mm (8/4 mil) via pad-and-pitch structure, and at least 8 PCB layers including dedicated power and ground planes. Estimated: a minimum 4-layer stack-up will fail timing on the 14.1 Gbps GX channels due to insufficient return-path stitching. Use laser-drilled microvias on the top side and stack them on 1.0 mm centres with a depth of ~0.4 mm. Coplanarity on the FCBGA pads must be held within 0.10 mm to avoid head-in-pillow defects during BGA reflow.
Decouple every transceiver bank and the core/PLL supply pins with 0.1 uF X7R ceramic capacitors placed within 2.0 mm of each ball, and add 10 uF/22 uF bulk capacitors on every supply rail. According to the Arria 10 pin connection guidelines, missing decoupling or insufficient bulk capacitance on the 0.95 V core rail will cause PLL jitter and GX link errors. Sequence the core, IO, and transceiver rails using the recommended power-on-reset ordering to avoid latch-up.
Do not hot-plug the FCBGA - the FPGA has no built-in hot-swap support and board insertion while powered will damage the die. Use a sequencing controller or PMBus hot-swap controller if you need live-insertion. Estimated: typical Arria 10 GX power at full fabric utilization on N2-1150 is around 35 to 45 W; verify your heatsink solution with the Quartus Prime Power Analyzer before committing to the thermal solution.
The Arria 10 GX transceivers operate up to 14.1 Gbps and require controlled-impedance differential traces (typically 85-ohm to 100-ohm differential). Match trace lengths to within 0.13 mm (5 mil) within a transceiver channel and 2.5 mm (100 mil) between related channels of the same interface. Use a HyperLynx or Ansys SIwave simulation of every transceiver channel to validate loss, crosstalk, and eye margins before tape-out.
Compliance Information
RoHS-compliant per Altera/Intel product page. AEC-Q100 not applicable (FPGA is not an automotive-grade discrete). REACH and conflict-minerals compliance inherited from Intel PSG.
