10AX115R3F40E2SG - Arria 10 GX 1150K LE FPGA, 28nm | Intel
MPN: 10AX115R3F40E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5985 | $5,985.00 |
| 10 | $5750 | $57,500.00 |
| 50 | $5450 | $272,500.00 |
| 100 | $5180 | $518,000.00 |
| 500 | $4925 | $2,462,500.00 |
Drop-in alternatives for 10AX115R3F40E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115R3F40E2LG
✅ Drop-In✓ In Stock
$1425 / Unit
View Datasheet →10AX115R2F40E2SG
✅ Drop-In✓ In Stock
$5410 / Unit
View Datasheet →10AX115R2F40E2LG
✅ Drop-In✓ In Stock
$10300 / Unit
View Datasheet →10AX090R3F40E2SG
✅ Drop-In✓ In Stock
$5400 / Unit
View Datasheet →10AX090R3F40E2LG
✅ Drop-In✓ In Stock
$5750 / Unit
View Datasheet →10AX090R2F40E2SG
✅ Drop-In✓ In Stock
$4750 / Unit
View Datasheet →10AX115R3F40E2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 |
| Embedded Memory | 68,857,856 bits (8,557 Kbit) |
| M20K Memory Blocks | 2,738 |
| DSP Blocks | 1,518 (variable-precision, hard FP) |
| Maximum User I/O | 342 |
| Transceiver Channels | 24 (up to 14.1 Gbps) |
| Hard Memory Controllers | DDR4/DDR3/QDR IV |
| Hard PCIe Gen3 IP Cores | 2 |
| Process Technology | TSMC 20 nm |
| Speed Grade | -2 |
| Temperature Grade | E2 (0C to +100C) |
| Package | 1517-ball FCBGA (F40), 1.0 mm pitch |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| Configuration Memory | Embedded (no external flash required for typical use) |
| RoHS Status | Compliant |
10AX115R3F40E2SG Pin Configuration
| Pin A1 | GND — Ground reference |
| Pin A2 | VCC — Core voltage supply |
| Pin B1 | GXB_TX0_P — Transceiver channel 0 transmit positive |
| Pin B2 | GXB_RX0_P — Transceiver channel 0 receive positive |
| Pin C1 | USER_IO_0 — User I/O bank 1A |
| Pin D1 | CLK_IN_0 — Differential clock input pair positive |
| Pin E1 | nCONFIG — Configuration active-low control |
| Pin F1 | MSEL0 — Configuration mode select 0 |
| Pin G1 | TCK — JTAG test clock |
| Pin H1 | TDI — JTAG test data in |
| Pin J1 | TDO — JTAG test data out |
| Pin K1 | TMS — JTAG test mode select |
| Pin L1 | VCCIO_1A — I/O bank 1A voltage supply |
| Pin M1 | GND — Ground reference |
| Pin N1 | REFCLK_P — Reference clock for transceivers positive |
| Pin P1 | VCCBAT — Battery backup supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115R3F40E2SG is suitable for 6 applications: 100G Optical Transport Networking Line Card, Software-Defined Radio (SDR) Baseband Processing, Broadcast Video Processing (4K/8K), PCIe Gen3 Accelerator Cards, Industrial High-Performance Imaging Systems, Aerospace Radar Signal Processing.
100G Optical Transport Networking Line Card
The 10AX115R3F40E2SG is well-suited for 100G optical line cards in OTN/OTU4 transport systems. Its 24 transceivers operate at up to 14.1 Gbps, which can be aggregated into multiple 40G/100G Ethernet, OTU4, or Interlaken interfaces. The 1,150,000 logic elements and 1,518 hard DSP blocks handle FEC encoding/decoding and OTN framer logic at line rate without external processing. The hard PCIe Gen3 cores enable direct host connectivity for software-defined networking (SDN) control plane. Placed on the line card with a QSFP28 cage, the FCBGA package enables reliable operation at the industrial temperature range.
Recommended
Software-Defined Radio (SDR) Baseband Processing
The 10AX115R3F40E2SG supports wideband SDR baseband processing for wireless infrastructure and military communications. Its 1,518 variable-precision DSP blocks deliver up to 1.5 TFLOPs single-precision FP, sufficient for LTE/LTE-A/5G channelization, FFT/iFFT, and digital up/down conversion. The 68.85 Mbit embedded memory buffers wide-bandwidth samples between DSP blocks. Transceivers at 14.1 Gbps interface directly to ADC/DAC devices (JESD204B) for high-speed data converters. The 1517-ball FCBGA package provides the signal density required for multi-channel SDR designs.
Recommended
Broadcast Video Processing (4K/8K)
The 10AX115R3F40E2SG handles 4K/8K broadcast video processing, including real-time HEVC/H.265 encoding, color space conversion, and multi-stream stitching. Its 1,150,000 logic elements support wide video pipelines while the 68.85 Mbit embedded memory buffers multiple frame lines. Transceers connect to SDI interfaces at 12G-SDI rates (11.88 Gbps). The hard PCIe Gen3 cores enable host transfers for live editing workflows. With -2 speed and E2 temperature grades, the device operates reliably in broadcast studio and outdoor production environments.
Recommended
PCIe Gen3 Accelerator Cards
The 10AX115R3F40E2SG is ideal for PCIe Gen3 accelerator cards in data center and HPC workloads. Its two hard PCIe Gen3 IP cores (x4 or x8 lane configurations) provide direct host connectivity without external bridge chips. The 1,518 hard DSP blocks accelerate compute kernels (FFT, GEMM, convolution), while the 1.15M logic elements implement custom datapaths. The 1517-ball FCBGA package supports the high-density power delivery and signal integrity required at PCIe Gen3 line rates. Placed on a half-height, half-length card with thermal management.
Recommended
Industrial High-Performance Imaging Systems
The 10AX115R3F40E2SG powers industrial machine vision and high-speed inspection systems. Its 1,518 DSP blocks enable real-time image processing (edge detection, pattern matching, FFT analysis) at multi-megapixel resolutions. Transceivers connect to high-speed image sensors via CoaXPress or Camera Link HS interfaces. The 68.85 Mbit embedded memory buffers line-scan or area-scan pixel data between processing stages. The E2 industrial temperature grade and 1517-ball FCBGA package support factory floor environments with vibration and temperature variation.
Recommended
Aerospace Radar Signal Processing
The 10AX115R3F40E2SG supports radar signal processing for defense and weather radar applications. Its 1,518 hard DSP blocks perform pulse compression, MTI filtering, and beamforming at real-time rates. Transceivers at 14.1 Gbps digitize radar IF signals and interface to high-speed ADCs. The 1.15M logic elements implement adaptive beamforming weights and clutter rejection algorithms. The FCBGA package's flip-chip interconnect ensures robust thermal and electrical performance in vibration-prone environments. Pair with a custom heatsink for high-duty-cycle radar operation.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115R3F40E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115R3F40E2LG | 10AX115R2F40E2SG | 10AX115R2F40E2LG | 10AX090R3F40E2SG |
|---|---|---|---|---|---|
| Package | 1517-ball FCBGA (F40) | 1517-ball FCBGA (F40) - same | 1517-ball FCBGA (F40) - same | 1517-ball FCBGA (F40) - same | 1517-ball FCBGA (F40) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 1,150,000 | 1,150,000 (same die) | 1,150,000 (same die) | 1,150,000 (same die) | 900,000 (-21.7%) |
| Embedded Memory | 68,857,856 bits | 68,857,856 bits (same die) | 68,857,856 bits (same die) | 68,857,856 bits (same die) | 53,560,320 bits (-22.2%) |
| DSP Blocks | 1,518 | 1,518 (same die) | 1,518 (same die) | 1,518 (same die) | 1,518 (same die) |
| Transceivers | 24 ch up to 14.1 Gbps | 24 ch up to 14.1 Gbps | 24 ch up to 14.1 Gbps | 24 ch up to 14.1 Gbps | 24 ch up to 14.1 Gbps |
| Speed Grade | -2 | -2 (same) | -2 (same) | -2 (same) | -2 (same) |
| Temperature Grade | E2 (0C to +100C) | E2 (same) | E2 (same) | E2 (same) | E2 (same) |
| Transceiver Power Tier | R3 (high-performance) | R3 (same) | R2 (lower power) | R2 (lower power) | R3 (same) |
| Solder Type | Standard (SnPb-free) | Lead-free reflow | Standard | Lead-free reflow | Standard |
| Approx Qty-1 Price (USD) | 5,985 | 5,985 | 5,750 | 5,750 | 4,990 |
Key Differentiators
- Highest density Intel Arria 10 in F40 FCBGA package (vs 10AX090R3F40E2SG)
- R3 high-performance transceiver power tier (vs 10AX115R2F40E2SG)
- Pin-compatible with full Arria 10 F40 family (vs Cyclone 10 GX 10CX220YF672E5G)
Design Notes
The 1517-ball FCBGA package uses a 1.0 mm ball pitch and requires an HDI PCB stackup with microvia-in-pad (VIP) technology. Recommended stackup: 12+ layers including dedicated ground/power planes under the package. Use ENIG or ENEPIG surface finish for reliable ball attachment. Per Intel's package user guide, BGA pads require non-solder-mask-defined (NSMD) geometry with 0.55 mm pad diameter to ensure proper ball collapse and joint reliability.
The 10AX115R3F40E2SG can dissipate up to 35 W in fully-utilized configurations. Use a high-performance thermal interface material (TIM) with thermal conductivity above 5 W/mK, and attach a heatsink with at least 4 C/W thermal resistance. For passive cooling in sealed enclosures, ensure the FCBGA package's top is exposed (lid-up variant recommended) or use the integrated heat slug. Estimated: at 25 W dissipation, junction temperature rises 35 C above ambient with a 1.4 C/W theta_JA. Always design for less than 100 C junction under worst-case load.
Transceiver channels operating at 14.1 Gbps require matched-length routing within +/- 0.05 mm tolerance, with ground vias every 0.5 mm to maintain return path continuity. Use 100 ohm differential impedance for GXB_TX/RX pairs with 85 ohm common-mode. Per Intel's transceiver user guide, separate transceiver power rails (VCCH_GXB, VCCA_GXB) from digital core supplies to minimize noise coupling. Place AC coupling capacitors within 2 mm of the device ball.
The 10AX115R3F40E2SG requires multi-rail power distribution: VCC (0.9 V core), VCCPT (1.0 V PHY transceiver), VCCBAT (2.5 V battery backup), and VCCIO (1.2-3.3 V I/O banks). Use a sequence controller (such as the LTC2928 or Intel's recommended sequencer) to enforce proper power-up order: VCCBAT first, then VCCPT, then VCC, then VCCIO. Failure to sequence properly can damage the device. Decoupling: 100 nF X7R capacitors within 1 mm of every bank supply ball, plus bulk 47 uF polymer caps per rail.
Do not confuse the E2 (industrial 0C to +100C) temperature grade with the I2 (-40C to +100C) extended industrial grade - the I2 variant requires additional thermal qualification and may have different timing margins. The FCBGA package is moisture-sensitive (MSL3); follow JEDEC J-STD-033 bake procedures if exposure to ambient exceeds 168 hours before assembly. Do not bypass the configuration pins MSEL[2:0] - the Arria 10 will not configure if MSEL values are incorrect. Ensure the JTAG chain order is correct when programming via USB-Blaster or JTAG cable.
Compliance Information
RoHS compliant per Intel product page. E2 temperature grade (0C to +100C) is industrial, not AEC-Q100 automotive. The LG variant uses lead-free solder for high-temperature reflow processes; standard variant (no L suffix) is Pb-free with SAC solder balls.
