A42MX24-2PQG160I - 36K Gate 5V FPGA 160-PQFP | Microchip
MPN: A42MX24-2PQG160I β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $61.65 | $616.50 |
| 100 | $55.2 | $5,520.00 |
| 500 | $49.1 | $24,550.00 |
| 1,000 | $44 | $44,000.00 |
Drop-in alternatives for A42MX24-2PQG160I β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
A42MX24-PQG160I
β Drop-Inπ Reference alternative (not in catalog)
A42MX24-2PQG160M
β Drop-Inπ Reference alternative (not in catalog)
A42MX24-2PQ160I
β Drop-Inπ Reference alternative (not in catalog)
A42MX24-PQ160I
β Drop-Inβ In Stock
$22.3 / Unit
View Datasheet βA42MX24-2PQG160I Maximum Ratings & Electrical Characteristics
| Family | 42MX (MX FPGA) |
| System Gates | 36000 gates |
| Logic Cells / CLBs | 912 |
| User I/Os | 125 |
| Process Technology | 0.45 um CMOS |
| Supply Voltage | 3.3V / 5V (mixed-voltage) |
| Architecture | Antifuse (one-time programmable) |
| Speed Grade | -2 |
| Maximum Clock Frequency | [DATA_NEEDED: Fmax for -2 grade] |
| Package | 160-Pin PQFP (BQFP), 0.65 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial, I suffix) |
| PCI Compliance | PCI Local Bus Specification v2.1 |
| Low Power Mode | Yes |
| Configuration Storage | Non-volatile (no external ROM needed) |
| Lead Free / RoHS | Lead free (G suffix, LEAD FREE) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL] |
A42MX24-2PQG160I Pin Configuration
| Pin 1-40 | I/O / Cluster I/O β User programmable I/O banks (MultiPlex I/O, 3.3V/5V) |
| Pin [per JEDEC S-PQFP-G160] | VDD β Core supply (5V nominal) - multiple pins [DATA_NEEDED: exact pin numbers] |
| Pin [per JEDEC S-PQFP-G160] | GND β Ground - multiple pins [DATA_NEEDED: exact pin numbers] |
| Pin [DATA_NEEDED] | CLKA / CLKBLK β Dedicated clock inputs [DATA_NEEDED: exact pin numbers] |
| Pin [DATA_NEEDED] | FPGA_RESET β Global reset [DATA_NEEDED: exact pin numbers] |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX24-2PQG160I is suitable for 6 applications: Legacy 5V PLD Consolidation, Industrial Control and Automation, PCI Bus Interface Logic, Defense and Avionics Sustainment, High-Reliability Embedded Logic, ASIC Prototyping and Bridge Logic.
Legacy 5V PLD Consolidation
The A42MX24-2PQG160I is purpose-built for integrating multiple legacy 5V PLDs, PALs, and GALs into a single 36K-gate chip. Its native 5.0V architecture means no level shifters or dual-rail power trees are needed when replacing older 5V glue logic, and MultiPlex I/Os directly interface 5.0V and 3.3V domains. The antifuse fabric powers up instantly configured, matching the behavior of the ROM-less legacy devices it replaces. In sustainment programs, one A42MX24 typically replaces 5-15 TTL/PLD packages, cutting board area and failure points while preserving proven 5V system timing.
Recommended
Industrial Control and Automation
In industrial controllers, motor-drive interface logic, and factory automation backplanes, the A42MX24-2PQG160I provides deterministic, one-time-programmed logic immune to configuration corruption from power glitches - a known weakness of SRAM FPGAs on noisy industrial floors. The industrial temperature rating of -40C to +85C covers unconditioned cabinets and cold-start environments. The PCI Local Bus v2.1 compliance allows direct attachment to industrial PC backplanes, and the low-power mode reduces cabinet heat. Antifuse non-volatility also removes configuration load time, so control logic is active immediately at power-up.
Recommended
PCI Bus Interface Logic
The A42MX24 is fully compliant with the PCI Local Bus Specification version 2.1 and offers programmable PCI I/O characteristics, making it a natural host for custom PCI interface cores in 33MHz systems. MultiPlex I/Os can be programmed for PCI-compliant drive and slew at both 5.0V and 3.3V signaling, letting one design serve both bus voltage environments. With 125 user I/Os, a single device implements the PCI state machine plus target application logic such as FIFOs and register files. Implementing PCI in antifuse fabric avoids SRAM configuration security concerns in commercial equipment.
Recommended
Defense and Avionics Sustainment
Legacy defense and avionics platforms standardized on the Actel MX family because antifuse FPGAs tolerate radiation-induced configuration upsets and provide instant-on, single-chip operation without boot devices. The A42MX24-2PQG160M variant (military range) shares this die for programs needing extended qualification. For depot-level sustainment of radar interfaces, mission-data encoders, and 1553 glue logic built on 5V architecture, the A42MX24-2PQG160I keeps obsolete designs manufacturable. The 0.45um process is well characterized, and design files in Libero remain compatible for re-programming new devices.
Recommended
High-Reliability Embedded Logic
Applications that cannot tolerate configuration corruption - medical device control logic, test-equipment sequencers, and security systems - benefit from the one-time-programmed antifuse fabric of the A42MX24-2PQG160I. Unlike SRAM FPGAs, there is no bitstream to intercept or corrupt, providing inherent design-security and failure-mode advantages. The 36K-gate capacity handles state machines, counters, bus bridges, and custom peripherals, while 125 I/Os interface mixed 3.3V/5V subsystems. Instant power-up configuration simplifies watchdog and Brown-out recovery design, since logic is functional within microseconds of power application.
Recommended
ASIC Prototyping and Bridge Logic
Before committing to ASIC tape-out or while an ASIC is in fabrication, the A42MX24-2PQG160I serves as a low-cost prototyping and system-bridge device for modest gate counts. Microchip positions MX explicitly as a single-chip ASIC alternative for high-volume, cost-sensitive designs where a full ASIC is not economical. The antifuse fabric delivers ASIC-like deterministic timing without reconfiguration latency, and the 160-pin PQFP is inexpensive to assemble. Engineers can validate RTL, interface real 5V peripherals, and ship bridge logic while iterating on the target ASIC design.
Recommended
Recommended Products Summary
Engineering reference data for A42MX24-2PQG160I β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX24-PQG160I | A42MX24-2PQG160M | A42MX24-2PQ160I | A42MX36-PQG208I |
|---|---|---|---|---|---|
| Package | 160-PQFP (BQFP), 0.65 mm | 160-PQFP (BQFP) - same | 160-PQFP (BQFP) - same | 160-PQFP - same footprint, leaded finish | 208-PQFP - different |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36,000 | 36,000 | 36,000 | 36,000 | Higher (42MX36 family) |
| Logic Cells | 912 | 912 | 912 | 912 | [DATA_NEEDED] |
| User I/Os | 125 | 125 | 125 | 125 | Up to 202 (family max) |
| Speed Grade | -2 | Standard | -2 | -2 | -1 |
| Temperature Range | -40C to +85C (Industrial) | -40C to +85C | Military range | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V |
| Lead Finish | Lead free (G) | Lead free (G) | Lead free (G) | Leaded | Lead free (G) |
| Price (qty 1) | $68.50 as of 2026-08-30 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- One-time-programmed non-volatile fabric (vs SRAM-based FPGAs (Xilinx/Altera))
- Native 5.0V mixed-voltage architecture (vs Modern FPGAs (1.2-2.5V only))
- Speed grade -2 performance vs standard grade (vs A42MX24-PQG160I)
Design Notes
The A42MX24 operates from a 5V core with 3.3V/5V MultiPlex I/O banks. Decouple each VDD/GND pin pair with 0.1uF ceramic capacitors placed within 5 mm of the pin, plus bulk 10uF per rail. Mixed-voltage systems must ensure 3.3V banks are powered before 5V I/O drivers drive them, or use I/O bank grouping to respect the datasheet power-up ordering.
The antifuse fabric is one-time programmable - there is no reflow-and-retry. Budget 15-25% spare devices per programming session for yield loss, and lock your design in Libero before ordering. Also remember the -2 speed grade timing is faster than standard grade: swapping in a standard-grade A42MX24-PQG160I requires full static timing re-verification even though the footprint is identical.
Programmable PCI I/O requires attention to drive strength and slew settings on the PCI bus. When using MultiPlex I/Os at 5.0V with PCI v2.1 compliance, follow the 40MX/42MX datasheet DS2136 PCI implementation section for output timing parameters. Keep 160-PQFP lead-length stubs short on the PCI bus; series termination resistors (22-33 ohm) are typically needed on clock and high-fanout nets.
Compliance Information
G suffix denotes lead-free package; distributor listings mark part as LEAD FREE. REACH/halogen/conflict-minerals status not stated in provided data.
