A42MX16-3PQG160 - 24K Gate MX FPGA, 125 I/O | Microchip
MPN: A42MX16-3PQG160 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $62.1 | $621.00 |
| 100 | $55.8 | $5,580.00 |
| 500 | $50.2 | $25,100.00 |
| 1,000 | $45.1 | $45,100.00 |
Drop-in alternatives for A42MX16-3PQG160 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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A42MX16-1PQG160I
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View Datasheet →A42MX16-2PQG160
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$298 / Unit
View Datasheet →A42MX16-2PQG160I
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$1 / Unit
View Datasheet →A42MX16-3PQG160 Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) |
| System Gates | 24000 |
| Configurable Logic Blocks (CLBs) | 608 |
| Logic Cells | 1232 |
| User I/O | 125 |
| Speed Grade | -3 (fastest commercial grade) |
| Supply Voltage | [DATA_NEEDED: supply voltage range] |
| Technology | CMOS antifuse (one-time programmable) |
| Package | 160-BQFP / PQFP-160 (PQG160) |
| Terminal Pitch | 0.635 mm |
| Mounting Type | Surface Mount |
| JTAG / Boundary Scan | IEEE 1149.1 compatible |
| Programming Type | One-Time Programmable (antifuse) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Lead Free |
| Manufacturer Part Status | Active (ships from distribution) |
A42MX16-3PQG160 Pin Configuration
| Pin 1 | IO — User input/output |
| Pin [DATA_NEEDED] | VCC — Core supply |
| Pin [DATA_NEEDED] | GND — Ground |
| Pin [DATA_NEEDED] | TCK — JTAG test clock (IEEE 1149.1) |
| Pin [DATA_NEEDED] | TDI — JTAG test data in |
| Pin [DATA_NEEDED] | TDO — JTAG test data out |
| Pin [DATA_NEEDED] | TMS — JTAG test mode select |
| Pin [DATA_NEEDED] | CLK — Dedicated clock input |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX16-3PQG160 is suitable for 6 applications: Legacy PLD Consolidation, Industrial Automation Control, Telecommunications Line Cards, Defense and Avionics Logic, ASIC Prototyping and Bridge Logic, Test and Measurement Equipment.
Legacy PLD Consolidation
The MX family was designed by Microsemi specifically to integrate legacy PLD, PAL, and GAL designs into a single low-cost device. The A42MX16-3PQG160's 24,000 system gates and 608 CLBs provide enough capacity to absorb multiple older 22V10-class devices plus surrounding glue logic, reducing board area and BOM line items. The antifuse fabric programs once and retains configuration permanently with no boot-time load, matching the instant-on behavior of the PLDs it replaces in industrial control panels and line cards.
Recommended
Industrial Automation Control
In factory automation and motor control panels, the A42MX16-3PQG160 implements address decoding, interrupt arbitration, PWM fan-out, and sensor interface glue logic. Its 125 user I/O connect encoders, limit switches, and communication transceivers, while the -3 speed grade supports the fastest decode paths of the family. Because the antifuse configuration is immune to configuration-memory upset, the device powers up deterministic at every cycle - a key requirement for safety-adjacent control sequences in PLC backplanes.
Recommended
Telecommunications Line Cards
Telecom line cards historically relied on MX antifuse FPGAs for framing logic, backplane interfaces, and TDM bus bridging. The A42MX16-3PQG160 provides 24K gates for channel-count logic and IEEE 1149.1 JTAG for board-level production test, both essential in NEBS-style card designs. The mature CMOS process and stable, non-changing MX fabric mean designs verified years ago remain bit-identical through continued production, avoiding the requalification churn typical of SRAM FPGA fabric updates.
Recommended
Defense and Avionics Logic
Antifuse FPGAs are favored in defense and avionics payloads because their one-time-programmed interconnect contains no configuration memory that can be disturbed by radiation-induced single-event effects. The A42MX16-3PQG160's 24K gates suit telemetry formatting, bus interface adaptation, and voter/comparator logic. The non-volatile fabric also removes the need for external configuration flash, reducing parts count and improving startup determinism in mission-critical systems subject to long program lifecycles.
Recommended
ASIC Prototyping and Bridge Logic
The MX family is positioned by Microchip as a reliable single-chip ASIC alternative, and the A42MX16-3PQG160 fills this role for low-to-medium volume ASIC replacements. Its 24,000 gates accommodate state machines, address generators, and protocol converters, while the -3 grade provides the fastest available timing within the family. Because the fabric is mask-programmed-equivalent once programmed, it avoids the configuration-stream security concerns of SRAM FPGAs in proprietary bridge-logic designs.
Recommended
Test and Measurement Equipment
Bench instruments and automated test fixtures use the A42MX16-3PQG160 for trigger distribution, timing generation, and fixture-specific adaptation logic. Its 125 I/O drive relay matrices and comparator banks, and JTAG boundary scan simplifies in-fixture self-test. The fixed antifuse routing keeps propagation delays deterministic, which matters for trigger skew budgets; the -3 speed grade minimizes worst-case path delay within the MX16 density point.
Recommended
Recommended Products Summary
Engineering reference data for A42MX16-3PQG160 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX16-1PQG160I | A42MX16-2PQG160 | A42MX16-2PQG160I |
|---|---|---|---|---|
| Package | PQFP-160 (PQG160), 0.635 mm pitch | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 24000 | 24000 | 24000 | 24000 |
| CLBs / Logic Cells | 608 / 1232 | 608 / 1232 | 608 / 1232 | 608 / 1232 |
| Speed Grade | -3 (fastest) | -1 (slowest) | -2 | -2 |
| Temperature Grade | Commercial [DATA_NEEDED: exact range] | Industrial (I) | Commercial | Industrial (I) |
| User I/O | 125 | 125 | 125 | 125 |
| Programming Technology | CMOS antifuse (OTP) | CMOS antifuse (OTP) | CMOS antifuse (OTP) | CMOS antifuse (OTP) |
| Relative Cost Position | Premium (fastest grade) | Lower cost | Lower cost | Lower cost |
Key Differentiators
- Fastest speed grade in the A42MX16 family (vs A42MX16-2PQG160)
- Non-volatile antifuse fabric (vs SRAM-based competitor FPGAs)
- JTAG boundary scan (IEEE 1149.1) (vs A42MX16-2PQG160 (same feature, but -3 timing margin))
Design Notes
The MX fabric is one-time programmable antifuse - the design cannot be changed after programming. Complete gate-level simulation and static timing closure in Microchip Designer (Actel Designer) before submitting the device to programming, and order engineering lots accordingly. Do not rely on in-field firmware updates as with SRAM FPGAs.
Verify the exact VCC specification for the -3PQG160 ordering code against datasheet DS2316 before board design; MX family marketing cites a 5.0 V architecture while A42MX16 CMOS die data cites 3.0V-3.6V operation with 3.3V nominal. Decouple each VCC pin with 0.1 uF ceramics placed within 2 mm of the PQFP supply pins.
With 125 user I/O on a 0.635 mm pitch PQFP, limit the number of simultaneously switching outputs per ground return by spreading I/O assignment across banks and adding series 22-33 ohm resistors on fast edges. Use IEEE 1149.1 JTAG chain access for production test of the surrounding board instead of bed-of-nails probing.
The PQFP-160 footprint with 0.635 mm pitch requires fine-pitch PCB capability (typically 6/6 mil minimum). Design the land pattern per the Microchip PQG160 mechanical drawing in DS2316 and keep the -3 grade's faster edges in mind when routing clock lines - keep clock traces short and reference a solid ground plane.
Compliance Information
Listed as LEAD FREE by Microchip USA and Lisleapex distributor data. REACH and conflict-minerals declarations not found in provided data.
