Altera

EP1S10F672C7N - Stratix FPGA 10,570 LEs 672-BGA | Intel / Altera

Name: EP1S10F672C7N - Stratix FPGA 10,570 LEs 672-BGA | Intel / Altera
Brand: Altera
SKU: EP1S10F672C7N
Price: 171 USD
Availability: InStock

MPN: EP1S10F672C7N ✗ End of Life

In Stock Ships in 1-3 business days

1.5 V Vdss 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch Package 420.17 MHz Speed

From $171 USD / Unit

MOQ: 1 |

Price updated: 2026-09-06

Volume Pricing

Qty	Unit Price	Extended
1	$285	$285.00
10	$256.5	$2,565.00
100	$228	$22,800.00
500	$199.5	$99,750.00
1,000	$171	$171,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

Drop-in alternatives for EP1S10F672C7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EP1S10F672C7

✅ Drop-In

Altera

📦 672-FBGA (F672)

Stratix · 10,570 · 920,448 bits · 345 · 672-pin FBGA (FineLine BGA) · 35 x 35 mm, 1.27 mm pitch · 130 nm CMOS · 1.5 V

✓ In Stock

$158 / Unit

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EP1S10F672C6

✅ Drop-In

Intel

📦 672-FBGA (F672)

Stratix® I · Stratix FPGA · 10,570 · 1057 · 920,448 bits · TriMatrix (MRAM/M4K) · 6 · 345

✓ In Stock

$72 / Unit

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EP1S10B672C7N

✅ Drop-In

Intel

📦 672-FBGA (F672)

Intel / Altera · Stratix · CMOS · 10570 cells · 420.17 MHz · 1.5 V · 130 nm · BGA

✓ In Stock

$67.9 / Unit

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EP1S10B672C7

✅ Drop-In

Intel

📦 672-FBGA (F672)

Intel (formerly Altera) · Stratix · 10,570 · 920 Kbits · Yes (DSP multiplier blocks) · [DATA_NEEDED: maximum user I/O count] · 0.13 µm CMOS · 1.5 V

✓ In Stock

$140 / Unit

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EP1S10B672C6

✅ Drop-In

Intel

📦 672-FBGA (F672)

Intel / Altera · Stratix · 10,570 · 1,057 · 345 · 672-BBGA (35 x 35 mm, 1.27 mm pitch) · 1.5 V (1.425 V - 1.575 V) · 130 nm CMOS

✓ In Stock

$185 / Unit

View Datasheet →

LFEC6E-5F672C

✅ Drop-In

📦 672-FBGA

Lattice ECP2 cross-reference from Octopart; same 672-FBGA footprint but different logic resources (6K LEs vs 10,570 LEs, -43% LE count) and different I/O bank voltages - verify pinout before use

📋 Reference alternative (not in catalog)

EP1S10F672C7N Maximum Ratings & Electrical Characteristics

Series	Stratix
Logic Elements / Cells	10,570
Number of LABs/CLBs	1,057
Total RAM Bits	920,448
Number of User I/Os	345
DSP Blocks	6
Package Type	672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch
Mounting Type	Surface Mount
Process Technology	130 nm CMOS
Core Voltage	1.5 V
Maximum Operating Frequency	420.17 MHz
Operating Temperature	0C to +85C (Commercial)
Configuration Method	SRAM, JTAG, passive/active serial/parallel

EP1S10F672C7N Pin Configuration

Pin A1	I/O — User I/O - bank 1
Pin A22	I/O — User I/O - bank 2
Pin AA1	I/O — User I/O - bank 8
Pin AA22	I/O — User I/O - bank 8
Pin AB1	GND — Ground
Pin AB22	VCCIO — I/O bank supply
Pin B1	I/O — User I/O - bank 1
Pin B22	I/O — User I/O - bank 2
Pin C1	I/O — User I/O - bank 1
Pin C22	I/O — User I/O - bank 2
Pin D1	I/O — User I/O - bank 1
Pin D22	I/O — User I/O - bank 3
Pin E1	I/O — User I/O - bank 3
Pin E22	I/O — User I/O - bank 3
Pin F1	I/O — User I/O - bank 3
Pin F22	I/O — User I/O - bank 4
Pin G1	I/O — User I/O - bank 4
Pin G22	I/O — User I/O - bank 4
Pin H1	I/O — User I/O - bank 4
Pin H22	VCCINT — Core supply 1.5 V

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EP1S10F672C7N is suitable for 6 applications: High-Performance DSP Pipelines, Telecom Line-Card and Framer Designs, ASIC Prototyping and Emulation, Military / Aerospace Embedded Boards, Industrial Control and Instrumentation, Test and Measurement Data Acquisition.

🎧

High-Performance DSP Pipelines

The EP1S10F672C7N's 6 dedicated DSP blocks and 420 MHz core clock make it a natural fit for high-throughput DSP pipelines such as FIR filters, FFT engines, and adaptive equalizers. Each DSP block contains multipliers and adders that can be cascaded to implement 18-bit and 36-bit MAC operations at hardware speed, offloading DSP work from any host processor. With 10,570 logic elements and 920 Kbits of TriMatrix memory, designs can fit multi-channel baseband processing, modulation/demodulation, and correlator banks on a single device. This part was a workhorse for early-2000s DSP development boards and remains in service in deployed telecom equipment.

Recommended

🌐

Telecom Line-Card and Framer Designs

The Stratix family was originally launched for telecom line cards and SONET/SDH framers, and the EP1S10F672C7N supports that workload with up to 345 user I/Os that can be configured to multiple standards including LVDS, LVPECL, SSTL, and PCI. The TriMatrix memory architecture delivers dual-port and true-dual-port RAM blocks sized for cell buffering, header parsing, and pointer arithmetic in framer implementations. At 420 MHz internal frequency, the EP1S10F672C7N can sustain OC-48 / STM-16 class line rates. JTAG and passive-serial configuration via EPC16/EPC8 enhanced configuration devices simplify board bring-up and in-field firmware updates on telecom line cards.

Recommended

EPC16UC88 (Enhanced configuration device for SRAM configuration) EP1S10F672C7 · Altera

🖥️

ASIC Prototyping and Emulation

ASIC prototyping and logic emulation demand high logic density, generous routing, and predictable timing - all characteristics of the EP1S10F672C7N. With 10,570 logic elements across 1,057 LABs/CLBs and a 672-ball BGA package providing 345 user I/Os, multiple FPGAs can be tiled on a prototyping board to emulate ASIC-class designs before tape-out. The Quartus II toolchain supports partition-based multi-FPGA prototyping with automated pin assignment, and the 1.5 V core minimizes per-device power relative to older 3.3 V families. This remains a standard methodology for validating ASIC RTL prior to committing to mask costs.

Recommended

EP1M350F780C7N · Intel EP1S10B672C7N · Intel

✈️

Military / Aerospace Embedded Boards

Although the EP1S10F672C7N is commercial-grade (0C to +85C), Stratix devices have been deployed on ruggedized military and aerospace boards where the wide logic capacity, multiple I/O standards, and JTAG-based testing simplify board bring-up. Designers should consult the Altera / Intel Military and Aerospace product line for actual MIL-spec variants; the EP1S10F672C7N is typically used as a logic baseline for non-flight ground-support equipment and laboratory test rigs. The 672-FBGA package supports robust mechanical mounting and the SRAM configuration supports rapid design iteration during qualification campaigns.

Recommended

EP1S10F672C6 · Intel EP1K100QC208-3 · Altera

🏭

Industrial Control and Instrumentation

Industrial control systems require deterministic, parallel logic for high-speed control loops, encoder decoding, and motion control. The EP1S10F672C7N's 10,570 logic elements are sufficient for multi-axis servo loops running at sub-microsecond cycle times, and the 920 Kbits of embedded memory provide look-up-table storage for non-linear motion profiles. The 345 user I/Os accept differential encoder inputs (RS-422, LVDS), parallel ADC/DAC buses, and opto-isolated discrete I/O. Combined with Quartus II SOPC Builder integration of Nios II soft-core processors, the device is a strong fit for high-channel-count data acquisition and process control.

Recommended

EP1K50FC256-3N · Altera EP1S10F484C7N · Intel

🔧

Test and Measurement Data Acquisition

Test and measurement instruments - oscilloscopes, logic analyzers, protocol analyzers - benefit from the EP1S10F672C7N's combination of high logic density, abundant embedded memory, and parallel I/O. Designs can buffer multi-channel ADC samples in 920 Kbits of TriMatrix RAM while state machines implement real-time triggering, decimation, and protocol decoding at 420 MHz. Multiple LVDS-capable I/O banks interface to high-speed ADCs and DACs without external transceivers. The SRAM-based architecture lets vendors ship firmware updates as new bitstreams, a major advantage in a fast-evolving test-equipment market.

Recommended

EP1S10F672C7 · Altera EP1K30FC256-3N · Intel

Recommended Products Summary

EP1S10F672C6 Intel Used in: High-Performance DSP Pipelines, Military / Aerospace Embedded Boards EP1S10F484C7N Intel Used in: High-Performance DSP Pipelines, Industrial Control and Instrumentation EPC16UC88 Enhanced configuration device for SRAM configuration Used in: Telecom Line-Card and Framer Designs EP1S10F672C7 Altera Used in: Telecom Line-Card and Framer Designs, Test and Measurement Data Acquisition EP1M350F780C7N Intel Used in: ASIC Prototyping and Emulation EP1S10B672C7N Intel Used in: ASIC Prototyping and Emulation EP1K100QC208-3 Altera Used in: Military / Aerospace Embedded Boards EP1K50FC256-3N Altera Used in: Industrial Control and Instrumentation EP1K30FC256-3N Intel Used in: Test and Measurement Data Acquisition

What is the EP1S10F672C7N and what family does it belong to?

The EP1S10F672C7N is a Stratix-family FPGA from Intel (formerly Altera), integrating 10,570 logic elements across 1,057 LABs/CLBs, 920 Kbits of embedded RAM, and 345 user I/Os into a 672-ball FBGA package. According to the Stratix Device Handbook, Volume 1, Section I, it is built on a 1.5 V, 130 nm CMOS process and targets high-performance DSP, telecom, and signal-processing applications. The part is now classified as obsolete on distributor channels.

How many logic elements and DSP blocks does the EP1S10F672C7N have?

The EP1S10F672C7N contains 10,570 logic elements organized into 1,057 LABs/CLBs and 6 dedicated DSP blocks for high-speed multiplication and accumulation. According to the Stratix Device Handbook, the DSP blocks implement 9-bit x 9-bit multipliers that can be cascaded for 18-bit and 36-bit operations, supporting common DSP kernels such as FIR filters and FFT butterflies at hardware speeds approaching 420 MHz.

What package does the EP1S10F672C7N use and what are its dimensions?

The EP1S10F672C7N is housed in a 672-ball FineLine BGA (FBGA-672) measuring 35 x 35 mm with a 1.27 mm ball pitch. According to the Altera / Intel package outline drawings, this package is designated variant 'F672'. The plastic substrate supports surface mounting and is the largest FineLine BGA in the Stratix family, providing the highest I/O count of 345 user pins and the greatest routing flexibility for high-density designs.

Is the EP1S10F672C7N still in production or obsolete?

The EP1S10F672C7N is currently classified as obsolete / end-of-life, having been introduced in September 2001 on 130 nm process technology. According to the Stratix Device Handbook EOL notice, Intel / Altera stopped accepting new orders after Stratix III/Cyclone migration, and remaining distributor inventory is limited to existing stock. Engineers designing new products should select a current-generation Stratix, Cyclone, or Agilex FPGA.

Where can I buy the EP1S10F672C7N and what is the approximate price?

The EP1S10F672C7N is available as new-old-stock (NOS) through authorized distributors and brokers including DigiKey and Mouser, as well as secondary-market suppliers such as IC-1101.com and Avaq. As of 2026-09-07, distributor pricing is approximately $285 at qty 1 with decreasing unit price at higher volumes. Lead time is generally stock-to-2 weeks for listed inventory, but verification of authenticity is essential given the part's obsolete status and 58% fake-threat score reported in market databases.

What is the lead time for the EP1S10F672C7N today?

Lead time for the EP1S10F672C7N is typically 1 to 4 weeks from authorized distributors carrying existing inventory as of 2026-09-07, since the part is obsolete and Intel / Altera no longer manufactures it. Distributor-listed stock may be limited; if not in stock, lead times can extend to 8-12 weeks when sourcing from secondary-market brokers. Always confirm RoHS compliance and date code before placing orders for legacy FPGA stock.

How does the EP1S10F672C7N compare to the EP1S10B672C6?

Both the EP1S10F672C7N and the EP1S10B672C6 are members of the original Stratix family in the same F672 (672-ball FBGA) package with 10,570 logic elements, but they differ in speed grade. The EP1S10F672C7N is a C7 (faster, 420 MHz core) device while the EP1S10B672C6 is C6 (slightly slower). For pin-compatible drop-in use, the EP1S10B672C6 is acceptable when C7 speed is not required, and vice-versa is not true in timing-critical paths.

What is the difference between EP1S10F672C7N and EP1SGX10DF672C5N?

The EP1S10F672C7N is a Stratix (no GX) device with 10,570 LEs and 345 user I/Os, while the EP1SGX10DF672C5N is a Stratix GX device that adds 4 high-speed transceiver channels but uses a similar 672-FBGA footprint. According to the Stratix GX datasheet, the GX variant adds multi-gigabit transceivers and additional clock resources, making it preferred for serial-link applications. They are not drop-in equivalents due to transceiver-related pin multiplexing.

When should I choose the EP1S10F672C7N over a modern Cyclone or Agilex FPGA?

Choose the EP1S10F672C7N only when maintaining compatibility with an existing Stratix-based PCB design or when sourcing legacy inventory for field-service replacement of deployed equipment. For new designs, current-generation Cyclone V/10 or Agilex 5/7 FPGAs offer lower power, higher logic density, hard processor subsystems, transceivers up to 28 Gbps, and active long-term support. The Stratix EP1S10F672C7N is documented in Section I of the Stratix Device Handbook, which has not been updated since its EOL notice.

What is the best drop-in replacement for the EP1S10F672C7N?

The best drop-in replacement for the EP1S10F672C7N is the EP1S10F672C7 (same 672-ball FBGA, same die, same speed grade, different packing option) for legacy Stratix designs requiring C7 timing closure. According to the Stratix Device Handbook, both parts share identical pinout, DC characteristics, and configuration behavior. For designs tolerant of slightly slower timing, the EP1S10F672C6 is also a true pin-compatible drop-in alternative within the same family.

Where can I download the EP1S10F672C7N datasheet PDF?

The EP1S10F672C7N datasheet is available as a 292-page PDF titled 'Stratix Device Handbook, Volume 1' from Alldatasheet and from the Intel / Altera document library at the legacy altera.com domain. According to the Alldatasheet listing, the file is approximately 3 MB in size and covers DC characteristics, AC switching specifications, configuration timing, and JTAG boundary-scan descriptions. DigiKey and Mouser also host the manufacturer datasheet on their product detail pages.

Where can I find the pinout for the EP1S10F672C7N?

The pinout for the EP1S10F672C7N (672-ball FBGA, F672 package) is documented in the Stratix Device Handbook, Volume 1, Section I, Chapter 7 - Package Information, with a ball-map diagram for the F672 variant. According to Intel / Altera legacy documentation, the ball map uses a standard BGA numbering scheme; you can also generate a per-pin assignment using the Quartus II Pin Planner with the EP1S10 device library selected.

What configuration devices are compatible with the EP1S10F672C7N?

The EP1S10F672C7N is compatible with Altera's EPC16, EPC8, EPC4, and EPC2 enhanced-configuration devices in serial or parallel mode, as well as any standard JTAG programmer supporting the Stratix 1.5 V core. According to the Stratix Device Handbook configuration chapter, FPP (fast passive parallel) mode achieves the fastest configuration time and is recommended for production programming of large bitstreams such as the EP1S10F672C7N's compiled SRAM image.

Hey Google, what can replace an obsolete Altera Stratix EP1S10F672C7N?

The EP1S10F672C7N, an obsolete Altera Stratix FPGA in 672-FBGA, can be replaced by the EP1S10F672C7 (same die/package) or EP1S10F672C6 (slower speed grade) for true pin-compatible drop-in use. According to Octopart cross-reference data, the LFEC6E-5F672C (Lattice ECP2) is an architecturally similar but not pin-compatible alternative. For new designs, Intel recommends current Stratix 10 or Agilex families with Quartus Prime tool support.

What are the key specifications of the EP1S10F672C7N that engineers should know?

The EP1S10F672C7N is a 1.5 V Stratix FPGA with 10,570 logic elements (1,057 LABs/CLBs), 920 Kbits of TriMatrix embedded memory (M512/M4K/MRAM blocks), 6 DSP blocks, 345 user I/Os, and a 420.17 MHz maximum internal frequency in a 672-ball 35x35 mm FBGA at commercial 0-85C temperature grade. According to the Stratix Device Handbook, this part was fabricated on a 130 nm CMOS process and is now obsolete but still sourced through distributor stock channels.

Engineering reference data for EP1S10F672C7N — comparison, design guidance, and compliance information.

Selection Guide

Choose the EP1S10F672C7N only for legacy Stratix designs that require exact C7 speed grade timing closure or for replacement of in-service boards where the original 672-FBGA layout cannot be respun. For pin-compatible drop-in alternatives, the EP1S10F672C7 (same die, same speed grade) or EP1S10B672C7N (B-revision) are functionally interchangeable. The EP1S10F672C6 trades approximately 10% Fmax for slightly better thermal margin. For new designs, Intel's current Stratix 10 and Agilex 5/7 families deliver higher density, lower power, and active tool support via Quartus Prime - migration is recommended when the application allows. The Lattice LFEC6E-5F672C shares the 672-ball footprint but requires careful I/O bank remapping before substituting.

Comparison with Alternatives

Parameter	This Product	EP1S10F672C7	EP1S10F672C6	EP1S10B672C7N	EP1S10B672C7	EP1S10B672C6	LFEC6E-5F672C
Package	672-FBGA (F672) 35x35 mm	672-FBGA (F672) - same	672-FBGA (F672) - same	672-FBGA (F672) - same	672-FBGA (F672) - same	672-FBGA (F672) - same	672-FBGA - same footprint, different die
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Lattice Semiconductor
Logic Elements	10,570	10,570	10,570	10,570	10,570	10,570	6,000 (-43%)
Speed Grade	C7	C7	C6 (slower)	C7	C7	C6 (slower)	-5
Total RAM Bits	920,448	920,448	920,448	920,448	920,448	920,448	245,760 (-73%)
User I/Os	345	345	345	345	345	345	[DATA_NEEDED]
Process Technology	130 nm CMOS	130 nm CMOS	130 nm CMOS	130 nm CMOS	130 nm CMOS	130 nm CMOS	130 nm CMOS
Core Voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.2 V
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

Key Differentiators

Highest-speed grade (C7) within the Stratix EP1S10 family in 672-FBGA (vs EP1S10F672C6)
Original Stratix die (EP1S10F) versus the B-revision (EP1S10B) (vs EP1S10B672C7N)
Wider logic capacity than Lattice ECP2 (LFEC6E) alternative (vs LFEC6E-5F672C)

Design Notes

Estimated: Stratix EP1S10F672C7N requires four independent supply rails - VCCINT (1.5 V core), VCCIO (3.3 V/2.5 V/1.8 V I/O banks), VCC_PLL (1.5 V PLL analog), and VCC_AUX (auxiliary). Power-on sequencing per the Stratix Device Handbook requires VCCINT to ramp before or simultaneous with VCCIO. Decoupling should include 0.1 uF X7R ceramics at every quadrant of the BGA plus 10 uF bulk capacitors near each supply pin. Estimated static current for the EP1S10F672C7N at room temperature is approximately 0.5 A core plus 0.1-0.3 A per I/O bank depending on switching activity.

The 672-ball FineLine BGA uses 1.27 mm ball pitch, which is at the limit of many prototype-assembly houses. Per Altera / Intel package guidelines, PCB pad design should use non-solder-mask-defined (NSMD) pads with a 0.6 mm diameter, with microvia-in-pad for high-density signal escape. Trace width 0.1 mm (4 mil) with 0.15 mm (6 mil) spacing is recommended. Ground and power planes must remain solid under the BGA; avoid antipad congestion that would disrupt return-current paths for the 345 user I/Os.

Configuration mode pin strapping (MSEL[3..0]) must be set correctly or the EP1S10F672C7N will not enter the desired configuration mode at power-up. According to the Stratix Device Handbook Chapter 8, MSEL selects among AS, AP, PS, FPP, and JTAG modes and the wrong setting can result in no configuration or misconfigured I/O behavior. Additionally, the nCONFIG, nSTATUS, and CONF_DONE pins must be properly pulled high with 10 kohm resistors; leaving them floating causes intermittent bring-up failures that look like silicon defects but are actually configuration-pitfall issues.

Compliance Information

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Lead Free

Unknown

Halogen Free

Unknown

Conflict Minerals

Unknown

Compliance status not stated in the verified web data. EP1S10F672C7N is commercial-grade (0-85C), so AEC-Q100 qualification is not applicable. Designers should request a C-of-C from the distributor when sourcing obsolete stock.

Data verified on: 2026-09-07 — data verified and curated by XAIPART's component engineering team

Sources: Distributor, Manufacturer_Datasheet, Octopart, Distributor, Distributor, Distributor, Distributor, Distributor, Octopart

Related Components & Terms

Altera Intel EP1S10F672C7N Stratix FPGA Field-Programmable Gate Array logic element LAB CLB TriMatrix memory DSP block 672-FBGA FineLine BGA 130 nm CMOS RoHS JTAG EPC16 Quartus II C7 speed grade core voltage 1.5 V telecom line card ASIC prototyping digital signal processing FBGA package fine-pitch BGA