EP1SGX25CF672C7 - Stratix GX FPGA 25K LE | Altera 672-BGA
MPN: EP1SGX25CF672C7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $521.99 | $521.99 |
| 10 | $480 | $4,800.00 |
| 100 | $425 | $42,500.00 |
| 500 | $380 | $190,000.00 |
| 1,000 | $340 | $340,000.00 |
Drop-in alternatives for EP1SGX25CF672C7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1SGX25CF672C7N
✅ Drop-In✓ In Stock
$338.5 / Unit
View Datasheet →EP1SGX25CF672C6
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$171 / Unit
View Datasheet →EP1SGX25CF672C6N
✅ Drop-In✓ In Stock
$210 / Unit
View Datasheet →EP1SGX25CF672C5
✅ Drop-In✓ In Stock
$1304.99 / Unit
View Datasheet →EP1SGX10CF672C7
✅ Drop-In✓ In Stock
$185 / Unit
View Datasheet →EP1SGX10CF672C7N
✅ Drop-In✓ In Stock
$182.1 / Unit
View Datasheet →EP1SGX25CF672C7 Maximum Ratings & Electrical Characteristics
| Family | Stratix® GX |
| Logic Elements / Cells | 25,660 |
| Logic Array Blocks (LABs) | 2,566 |
| Total RAM Bits | 1,944,576 |
| Maximum User I/O | 455 |
| Number of I/Os | 455 |
| Core Supply Voltage | 1.5 V |
| Process Technology | 130 nm CMOS |
| Operating Temperature | 0 °C to 85 °C (commercial, C-grade) |
| Mounting Type | Surface Mount |
| Package | 672-ball FC-FBGA, 33 × 33 mm, 1.0 mm pitch |
| RoHS Status | RoHS non-compliant (variant as listed); Pb-free / RoHS versions use "N" suffix |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG |
| Device Series | Stratix GX (SGX) |
| Lead-Free / Pb-Free | Lead-free package, RoHS status varies by suffix |
EP1SGX25CF672C7 Pin Configuration
| Pin 1 | VCC — Core supply voltage (1.5 V nominal) |
| Pin 2 | VCCIO — I/O supply voltage (bank-dependent, 1.5/1.8/2.5/3.3 V) |
| Pin 3 | GND — Ground reference |
| Pin 4 | IO[0] — User I/O bank 0 |
| Pin 5 | IO[1] — User I/O bank 0 |
| Pin 6 | IO[2] — User I/O bank 0 |
| Pin 7 | IO[3] — User I/O bank 0 |
| Pin 8 | IO[4] — User I/O bank 1 |
| Pin 9 | IO[5] — User I/O bank 1 |
| Pin 10 | IO[6] — User I/O bank 1 |
| Pin 11 | IO[7] — User I/O bank 1 |
| Pin 12 | TX_P — Transceiver channel transmit positive |
| Pin 13 | TX_N — Transceiver channel transmit negative |
| Pin 14 | RX_P — Transceiver channel receive positive |
| Pin 15 | RX_N — Transceiver channel receive negative |
| Pin 16 | REFCLK_P — Transceiver reference clock positive |
| Pin 17 | REFCLK_N — Transceiver reference clock negative |
| Pin 18 | CONFIG_DONE — Configuration complete (open-drain) |
| Pin 19 | nCONFIG — Configuration control (active-low) |
| Pin 20 | nSTATUS — Configuration status (active-low) |
| Pin 21 | TCK — JTAG clock |
| Pin 22 | TDI — JTAG data in |
| Pin 23 | TDO — JTAG data out |
| Pin 24 | TMS — JTAG mode select |
| Pin 25 | MSEL0 — Configuration mode select 0 |
| Pin 26 | MSEL1 — Configuration mode select 1 |
| Pin 27 | MSEL2 — Configuration mode select 2 |
| Pin 28 | CLK0 — Primary clock input (LVDS/LVTTL) |
| Pin 29 | CLK1 — Secondary clock input |
| Pin 30 | PLL_OUT — PLL output (routed internally) |
| Pin 31 | RESET_n — Device reset (active-low) |
| Pin 32 | NC — Not connected (per datasheet ball map) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1SGX25CF672C7 is suitable for 6 applications: PCI Express Endpoint Bridge, Gigabit Ethernet MAC / Switch Line Card, Custom Telecom Datapath / Glue Logic, Software-Defined Radio / Signal Intelligence, ASIC Prototyping Platform, Industrial Test & Measurement Backplane.
PCI Express Endpoint Bridge
The EP1SGX25CF672C7's integrated multi-gigabit transceivers (sufficient for PCIe Gen1 x4 / Gen2 rates of the generation) and 25,660 logic elements make it a fit for early PCI Express endpoint cards in server motherboards, RAID controllers, and FPGA accelerator cards. With 1,944,576 RAM bits, the device holds PCIe TLP headers, completion buffers, and small DMA FIFOs without external SRAM, simplifying board design. Placed on a x4 PCIe edge connector with 100-ohm differential lanes routed as controlled-impedance stripline, the device implements the PCIe hard IP plus a custom DMA engine. Compared to a discrete PHY plus ASIC, the integrated transceiver preserves board space but draws roughly 5-8 W at full link utilization, requiring thermal management on the line card.
Recommended
Gigabit Ethernet MAC / Switch Line Card
For telecom and enterprise switching line cards, the EP1SGX25CF672C7 supports multiple SGMII / 1000BASE-X MACs plus a small custom switch fabric. Its 25,660 logic elements are sufficient to implement 8-12 GMACs with classification engines, while 1,944,576 RAM bits hold the MAC address table and per-port counters. The 455 user I/Os enable 16+ tri-speed Ethernet PHYs and SFP cages to be connected directly. Compared to a fixed-function switch ASIC, the FPGA allows custom protocol extensions (e.g., PFC, ECN, telemetry) but consumes roughly 8-10 W with all transceivers active; plan thermal design accordingly.
Recommended
Custom Telecom Datapath / Glue Logic
The EP1SGX25CF672C7 is widely deployed as flexible glue logic and custom packet-processing logic on telecom line cards (e.g., framer-MAC bridging, OAM insertion, protocol offload). Its 130 nm Stratix GX fabric offers deterministic latency and on-chip TriMatrix memory sufficient for small lookup tables and CRC engines. With up to 455 user I/Os and integrated PLLs, the device bridges high-speed serial links to parallel backplane buses. The 1.5 V core supply and high I/O count demand careful power-rail sequencing and decoupling — follow Altera's Stratix GX hardware design guide for the 672-FBGA decoupling scheme.
Recommended
Software-Defined Radio / Signal Intelligence
The EP1SGX25CF672C7's combination of embedded DSP blocks (~80 GMACs), 25,660 logic elements and high-speed transceivers makes it usable in mid-bandwidth software-defined radio (SDR) and signal-intelligence platforms — particularly custom FPGA mezzanine cards (FMCs / PMC sites) that digitize IF signals and stream them to a host processor. With 1,944,576 RAM bits, the FPGA holds FIR/FFT coefficient tables and overlap-save buffers for channelization. Operating at 1.5 V core with 130 nm CMOS, the device is power-hungry versus modern 28 nm FPGAs (~5-8 W for typical SDR workloads) but is widely available in the legacy inventory channel as of 2026-09-07.
Recommended
ASIC Prototyping Platform
Engineers use the EP1SGX25CF672C7 on Stratix GX prototyping boards to validate mid-complexity ASIC RTL before tape-out. With 25,660 logic elements and 1,944,576 RAM bits, the device maps a representative slice of a 5-10M-gate ASIC into a single FPGA, while the high-speed transceivers model ASIC SerDes interfaces at functional level. The 672-ball FC-FBGA exposes 455 I/Os for probing and ASIC-style multi-bank partitioning. Compared to ASIC tape-out at $1-3M NRE, this FPGA-based prototyping avoids mask cost but runs at roughly 1/10 the ASIC clock frequency, so functional validation rather than at-speed validation is the deliverable.
Recommended
Industrial Test & Measurement Backplane
For high-channel-count ATE and PXI/PXIe instrumentation backplanes, the EP1SGX25CF672C7 acts as a flexible timing engine, protocol formatter, and trigger distribution hub. Its 455 I/Os are enough to fan out TTL/LVDS triggers to dozens of instrument slots, while 25,660 logic elements implement timing sequencers and pattern generators. The integrated transceivers provide backplane links to host controllers at gigabit rates. Compared to fixed-function timing ASICs, the FPGA allows late-stage protocol changes but requires a 1.5 V core supply plus multiple I/O voltages (LVTTL/LVDS/LVCMOS), which must be sequenced carefully during power-up.
Recommended
Recommended Products Summary
Engineering reference data for EP1SGX25CF672C7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1SGX25CF672C7N | EP1SGX25CF672C6 | EP1SGX25CF672C6N | EP1SGX25CF672C5 | EP1SGX10CF672C7 | EP1SGX10CF672C7N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Logic Elements | 25,660 | 25,660 | 25,660 | 25,660 | 25,660 | 10,570 (-59%) | 10,570 (-59%) |
| Total RAM Bits | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 920,448 (-53%) | 920,448 (-53%) |
| User I/O Count | 455 | 455 | 455 | 455 | 455 | 334 (-27%) | 334 (-27%) |
| Speed Grade | -7 | -7 | -6 (-15% fmax) | -6 (-15% fmax) | -5 (-25% fmax) | -7 | -7 |
| Temperature Grade | Commercial 0-85 °C | Commercial 0-85 °C | Commercial 0-85 °C | Commercial 0-85 °C | Commercial 0-85 °C | Commercial 0-85 °C | Commercial 0-85 °C |
| RoHS Status | Non-compliant (variant) | Compliant | Non-compliant | Compliant | Non-compliant | Non-compliant | Compliant |
| Core Supply | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
Key Differentiators
- Identical silicon and footprint, RoHS compliance added (vs EP1SGX25CF672C7N)
- Higher LE and RAM density at the same package (vs EP1SGX10CF672C7)
- Faster -7 speed grade vs -6 / -5 alternatives (vs EP1SGX25CF672C5)
Design Notes
The 672-ball FC-FBGA with 1.0 mm pitch requires an 8+ layer PCB stack-up with microvia or via-in-pad technology for reliable BGA breakout. Allocate the top layer for fan-out, a dedicated ground plane on layer 2, and a power plane on layer 3 to provide low-impedance return paths for the 1.5 V core and banked VCCIO rails. Match the length of every transceiver differential pair to within 5 mil and maintain 100-ohm differential impedance (±10%) for multi-gigabit signal integrity.
Estimated: at typical 100 MHz fabric utilization and 4 active transceivers, the EP1SGX25CF672C7 draws roughly 5-8 W from the 1.5 V core rail plus bank-dependent VCCIO current. Use a switching regulator with 3% set-point accuracy for the 1.5 V core, and place 0.1 µF + 10 µF ceramic decoupling within 100 mil of every VCC/VCCIO ball pair. Sequence the 1.5 V core before any VCCIO bank to prevent I/O latch-up during power-up; Altera's Stratix GX hardware design guide specifies a minimum 1 ms delay.
Do not assume EP1SGX25CF672C7 and EP1SGX25CF672C7N are drop-in for tooling — Quartus II selects the part number verbatim and emits a configuration bitstream keyed to the suffix. The RoHS variant (N-suffix) carries the same bitstream but has different ordering codes; verify MSEL[2:0] strapping matches your configuration mode (passive serial, fast passive parallel, or JTAG). The device is obsolete — lock the design's configuration mode to a single scheme because second-source FPGAs (e.g., Stratix V GX) do not share the MSEL pin semantics.
Reference-clock routing is the single most common link-quality problem on Stratix GX boards. Keep REFCLK_P/REFCLK_N traces length-matched within 1 mm and isolated from data lanes by at least 4× the dielectric thickness (3W rule). Use AC-coupling capacitors (0.01 µF) on every TX lane at the FPGA pin, never at the far-end connector, to avoid corrupting the transmit pre-emphasis. The 33 × 33 mm package is large enough that split-plane cuts under the die can fragment the ground return — keep a contiguous ground plane directly under the BGA.
Compliance Information
Per alterasemiconductor.com listing, the EP1SGX25CF672C7 (no 'N' suffix) is documented as RoHS non-compliant. The pin-compatible EP1SGX25CF672C7N is the RoHS / Pb-free variant. AEC-Q100 is not applicable to FPGAs; halogen-free and REACH status were not stated in the verified data and remain unknown.
