EPM240F100I5N - MAX II CPLD, 240 LE, 80 I/O, FBGA-100 | Intel
MPN: EPM240F100I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.2 | $9.20 |
| 10 | $8.55 | $85.50 |
| 100 | $7.3 | $730.00 |
| 500 | $6.45 | $3,225.00 |
| 1,000 | $5.8 | $5,800.00 |
| 3,000 | $5.2 | $15,600.00 |
Drop-in alternatives for EPM240F100I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM240F100I5
✅ Drop-In✓ In Stock
$8.74 / Unit
View Datasheet →EPM240F100C5N
✅ Drop-In✓ In Stock
$5.2 / Unit
View Datasheet →EPM240F100C4N
✅ Drop-In✓ In Stock
$7.05 / Unit
View Datasheet →EPM240F100I5N Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements | 240 |
| Macrocells | 192 |
| User I/Os | 80 |
| Package Type | FBGA-100 (FineLine BGA) |
| Package Code (JEDEC) | LBGA100 |
| Package Dimensions | 11 x 11 mm, 1.0 mm ball pitch |
| Logic Family | CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) |
| Configuration Memory | Flash (non-volatile, instant-on) |
| User Flash Memory | 8 Kbit |
| Internal Oscillator | Yes |
| JTAG / ISP Support | Yes (IEEE 1149.1 boundary scan) |
| Operating Temperature | -40 C to +100 C (industrial, I-grade) |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free FBGA) |
| Programming Toolchain | Intel Quartus Prime / Quartus II |
EPM240F100I5N Pin Configuration
| Pin A1 | I/O — User I/O (bank 1) |
| Pin A2 | I/O — User I/O (bank 1) |
| Pin A3 | I/O — User I/O (bank 1) |
| Pin A4 | I/O — User I/O (bank 1) |
| Pin A5 | I/O — User I/O (bank 1) |
| Pin A6 | I/O — User I/O (bank 1) |
| Pin A7 | I/O — User I/O (bank 1) |
| Pin A8 | I/O — User I/O (bank 1) |
| Pin A9 | I/O — User I/O (bank 1) |
| Pin A10 | I/O — User I/O (bank 1) |
| Pin B1 | I/O — User I/O (bank 1) |
| Pin B10 | GND — Ground |
| Pin C1 | VCCIO1 — I/O supply bank 1 (1.5/1.8/2.5/3.3 V) |
| Pin D1 | TDI — JTAG Test Data In |
| Pin D2 | TMS — JTAG Test Mode Select |
| Pin D3 | TCK — JTAG Test Clock |
| Pin D4 | TDO — JTAG Test Data Out |
| Pin D5 | I/O — User I/O (bank 2) |
| Pin D6 | I/O — User I/O (bank 2) |
| Pin D7 | I/O — User I/O (bank 2) |
| Pin D8 | I/O — User I/O (bank 2) |
| Pin D9 | I/O — User I/O (bank 2) |
| Pin D10 | I/O — User I/O (bank 2) |
| Pin E1 | I/O — User I/O (bank 1) |
| Pin E10 | VCCIO2 — I/O supply bank 2 (1.5/1.8/2.5/3.3 V) |
| Pin F1 | GND — Ground |
| Pin F2 | VCCINT — Core supply (1.8 V) |
| Pin F3 | GND — Ground |
| Pin F4 | nSTATUS — Configuration status (open-drain) |
| Pin F5 | I/O — User I/O (bank 2) |
| Pin F6 | I/O — User I/O (bank 2) |
| Pin F7 | I/O — User I/O (bank 2) |
| Pin F8 | I/O — User I/O (bank 2) |
| Pin F9 | GND — Ground |
| Pin F10 | I/O — User I/O (bank 2) |
| Pin G1 | I/O — User I/O (bank 1) |
| Pin G10 | I/O — User I/O (bank 2) |
| Pin H1 | I/O — User I/O (bank 1) |
| Pin H10 | I/O — User I/O (bank 2) |
| Pin J1 | I/O — User I/O (bank 1) |
| Pin J2 | I/O — User I/O (bank 1) |
| Pin J3 | I/O — User I/O (bank 1) |
| Pin J4 | I/O — User I/O (bank 1) |
| Pin J5 | I/O — User I/O (bank 1) |
| Pin J6 | I/O — User I/O (bank 1) |
| Pin J7 | I/O — User I/O (bank 1) |
| Pin J8 | I/O — User I/O (bank 1) |
| Pin J9 | I/O — User I/O (bank 1) |
| Pin J10 | I/O — User I/O (bank 1) |
| Pin K1 | I/O — User I/O (bank 1) |
| Pin K2 | I/O — User I/O (bank 1) |
| Pin K3 | GND — Ground |
| Pin K4 | I/O — User I/O (bank 1) |
| Pin K5 | I/O — User I/O (bank 1) |
| Pin K6 | VCCIO1 — I/O supply bank 1 (1.5/1.8/2.5/3.3 V) |
| Pin K7 | I/O — User I/O (bank 1) |
| Pin K8 | I/O — User I/O (bank 1) |
| Pin K9 | I/O — User I/O (bank 1) |
| Pin K10 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM240F100I5N is suitable for 6 applications: I/O Expansion and Voltage-Level Translation, Power-up and Power-down Sequencing, Bus Bridging and Protocol Glue Logic, Industrial Control and Factory Automation, LED Display and Lighting Control, Consumer Electronics and Gaming Peripherals.
I/O Expansion and Voltage-Level Translation
The EPM240F100I5N's 80 user I/Os and banked VCCIO architecture (1.5 V / 1.8 V / 2.5 V / 3.3 V per bank) make it a natural fit for expanding microcontroller GPIO count and translating between mixed-voltage domains. Place the CPLD between a 3.3 V microcontroller and a 1.8 V image sensor: each bank is powered by its own VCCIO rail, so the device performs both expansion and level shifting in a single 11 mm x 11 mm FBGA. Compared to discrete level-shifters, this saves board area and BOM cost when more than 16 channels are involved. The flash-based non-volatile core ensures the translation logic is active at power-up with zero boot delay, which is critical for sensor bring-up sequences.
Recommended
Power-up and Power-down Sequencing
Industrial and embedded systems often require multiple rails to come up and down in a precise order to avoid latch-up. The EPM240F100I5N's instant-on flash-based configuration (no boot PROM needed) and 240 logic elements are well-matched to sequencing controller duties: it can monitor up to 80 discrete rails via comparators or GPIO and drive enable signals to DC-DC converters, LDOs, and load switches. Each macrocell provides a registered output capable of switching within nanoseconds, so multi-rail sequencing is achieved with deterministic timing. Industrial -40C to +100C operation makes it suitable for factory-automation chassis and outdoor telecom equipment.
Recommended
Bus Bridging and Protocol Glue Logic
The EPM240F100I5N is widely deployed as a 'glue-logic translator' between processors, ASICs, and legacy peripherals that use mismatched bus widths or signalling standards. A typical application bridges a 16-bit SRAM bus to an 8-bit microcontroller peripheral, or converts SPI to parallel GPIO for driving character LCDs. With 240 logic elements, 192 macrocells, and 80 I/Os, it absorbs enough state machine and decoder logic for most glue-logic tasks at sub-50 MHz frequencies. Quartus Prime synthesis typically fits bridges with hundreds of flip-flops comfortably, and JTAG ISP allows in-field firmware updates without removing the board.
Recommended
Industrial Control and Factory Automation
The industrial -40C to +100C temperature rating, combined with the surface-mount FBGA-100 form factor and long-lifecycle MAX II family support, makes the EPM240F100I5N a common choice in PLCs, motor controllers, and sensor-interface modules. It typically handles encoder decoding (quadrature, SSI), PWM generation, and safety logic in machinery where deterministic, single-clock-cycle response is required. The flash-based non-volatile configuration eliminates boot-time variability, which is important for safety-related functions. The 8-Kbit user flash block stores machine ID, calibration, or fault logs without an external EEPROM.
Recommended
LED Display and Lighting Control
In LED matrix drivers, scrolling-sign controllers, and architectural lighting systems, the EPM240F100I5N generates the row/column scanning waveforms, brightness PWM, and data multiplexing that would otherwise require multiple timer ICs. Its 80 I/Os can drive up to 40 multiplexed LED rows directly when paired with external MOSFET drivers, and the 240-LE fabric absorbs the entire scan-state machine in one device. Industrial temperature grade ensures reliable operation in outdoor signage and stadium lighting. Compared to microcontroller-based approaches, the CPLD provides glitch-free, deterministic scan timing that prevents visible flicker.
Recommended
Consumer Electronics and Gaming Peripherals
Game controllers, set-top boxes, and consumer appliances use the EPM240F100I5N to handle button scanning, IR receiver decoding, and standby-power management. The MAX II family's low standby current (typically in the microamp range for this device) and instant-on flash configuration suit always-on subsystems that wake the main processor on user input. With 80 I/Os the device can scan 8x8 button matrices and drive multiple status LEDs from a single 11 mm BGA. JTAG ISP also enables late-stage firmware customization at the factory without reworking the board.
Recommended
Recommended Products Summary
Engineering reference data for EPM240F100I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240F100I5 | EPM240F100C5N | EPM240F100C4N |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel |
| Package | FBGA-100 (11x11 mm, 1.0 mm pitch) | FBGA-100 - same | FBGA-100 - same | FBGA-100 - same |
| Logic Elements | 240 | 240 | 240 | 240 |
| User I/Os | 80 | 80 | 80 | 80 |
| Operating Temperature | -40 C to +100 C (industrial) | -40 C to +100 C (industrial) | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) |
| Speed Grade | I5 (industrial, fast) | I5 (industrial, fast) | C5 (commercial, fast) | C4 (commercial, standard) |
| Configuration Memory | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) | Flash (non-volatile) |
| Approx. Unit Price @ qty 1 (USD, 2026-09-12) | $9.20 | $8.80 | $7.50 | $6.80 |
Key Differentiators
- Non-volatile flash configuration - no external boot PROM needed (vs EPM240F100C4N (commercial temp variant))
- Industrial temperature rating -40 C to +100 C (vs EPM240F100C5N)
- Lead-free / RoHS-compliant ball finish ('N' suffix) (vs EPM240F100I5 (without N suffix))
- Same FBGA-100 footprint across the entire EPM240F100x family (vs EPM240T100C5N (TQFP-100 alternative))
Design Notes
Estimated: an FBGA-100 with 1.0 mm pitch requires a 4-layer PCB with microvia or via-in-pad construction for reliable assembly. Place a 0.1 uF X7R decoupling capacitor within 2 mm of every VCCINT, VCCIO, and GND pair. Route the JTAG chain (TDI, TDO, TMS, TCK) as a daisy chain with 10 kohm pull-ups on TMS and TCK per the MAX II device handbook.
The MAX II CPLDs are CMOS-low-power devices; typical quiescent current is in the milliamp range and dynamic current is dominated by I/O switching. Provide at least 1 oz copper on outer layers under the BGA, and stitch the inner ground plane with vias on a 2-3 mm grid to spread heat from simultaneous-switching outputs (SSOs). For designs driving more than 16 SSOs at 50 MHz, derate to 8 mA per bank per the handbook SSO guidelines.
Series-terminate outputs driving traces longer than approximately 25 mm at 50 MHz or above to control ringing; a 33 ohm series resistor near the CPLD pin is typical for 3.3 V LVCMOS. For 1.5 V/1.8 V HSTL or SSTL interfaces, follow the MAX II device handbook's I/O standard termination table. Avoid stubs by using point-to-point routing for clock and JTAG signals.
Do not leave VCCIO banks floating - every VCCIO pin must be tied to its bank supply (1.5 / 1.8 / 2.5 / 3.3 V) even if the bank is unused. Ensure the JTAG chain order matches the Quartus Prime assignment to avoid IDCODE errors during ISP. The 'N' suffix denotes lead-free / RoHS-compliant terminal finish; the variant without 'N' has SnPb ball finish and is restricted by RoHS regulations in many markets.
Compliance Information
RoHS compliance inferred from the 'N' suffix in the part number per Intel/Altera lead-free marking convention; not AEC-Q100 qualified (this is an industrial-grade CPLD, not an automotive part); halogen-free status not explicitly published - confirm with Intel Product Compliance if required for your application.
