EPM3256AQI208-10 - MAX 3000A 256-Macro CPLD, 10ns, PQFP-208 | Altera
MPN: EPM3256AQI208-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.58 | $32.58 |
| 10 | $29.32 | $293.20 |
| 100 | $26.1 | $2,610.00 |
| 500 | $22.85 | $11,425.00 |
| 1,000 | $19.95 | $19,950.00 |
Drop-in alternatives for EPM3256AQI208-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3256AQC208-10
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View Datasheet βEPM3256AQC208-7
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$17.2 / Unit
View Datasheet βEPM3256AQC208-7N
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EPM3256AQI208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 |
| Usable Gates | 5,000 |
| Logic Elements / LABs | 16 Logic Array Blocks |
| User I/Os | 161 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency (fCNT) | 95.2 MHz |
| Internal Counter Speed | Up to 227.3 MHz |
| Supply Voltage - Core | 3.3 V |
| I/O Logic Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | EEPROM, In-System via JTAG (IEEE 1149.1) |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 |
| Operating Temperature | 0C to +70C (Industrial suffix 'I' per part number) |
| Package | 208-pin PQFP (Plastic Quad Flat Pack), FQFP code |
| Terminal Form | Gull-wing SMD |
| RoHS Status | Compliant (per lead-free 'Q' suffix) |
| Mounting Type | Surface Mount |
EPM3256AQI208-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | VCCINT β Core 3.3V supply |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 46 | I/O β User I/O pin (bank 2) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | I/O β User I/O pin (bank 2) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | VCCINT β Core 3.3V supply |
| Pin 56 | I/O β User I/O pin (bank 2) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | I/O β User I/O pin (bank 2) |
| Pin 59 | I/O β User I/O pin (bank 2) |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin (bank 3) |
| Pin 62 | I/O β User I/O pin (bank 3) |
| Pin 63 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 76 | I/O β User I/O pin (bank 3) |
| Pin 77 | I/O β User I/O pin (bank 3) |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | I/O β User I/O pin (bank 3) |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | VCCINT β Core 3.3V supply |
| Pin 86 | I/O β User I/O pin (bank 3) |
| Pin 87 | I/O β User I/O pin (bank 3) |
| Pin 88 | I/O β User I/O pin (bank 3) |
| Pin 89 | I/O β User I/O pin (bank 3) |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O pin (bank 4) |
| Pin 92 | I/O β User I/O pin (bank 4) |
| Pin 93 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 94 | I/O β User I/O pin (bank 4) |
| Pin 95 | I/O β User I/O pin (bank 4) |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β User I/O pin (bank 4) |
| Pin 98 | I/O β User I/O pin (bank 4) |
| Pin 99 | I/O β User I/O pin (bank 4) |
| Pin 100 | I/O β User I/O pin (bank 4) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (bank 4) |
| Pin 103 | I/O β User I/O pin (bank 4) |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | I/O β User I/O pin (bank 4) |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | GND β Ground |
| Pin 111 | I/O β User I/O pin (bank 4) |
| Pin 112 | I/O β User I/O pin (bank 4) |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | VCCINT β Core 3.3V supply |
| Pin 116 | I/O β User I/O pin (bank 4) |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O pin (bank 4) |
| Pin 122 | I/O β User I/O pin (bank 4) |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | GND β Ground |
| Pin 131 | I/O β User I/O pin (bank 4) |
| Pin 132 | I/O β User I/O pin (bank 4) |
| Pin 133 | I/O β User I/O pin (bank 4) |
| Pin 134 | I/O β User I/O pin (bank 4) |
| Pin 135 | VCCINT β Core 3.3V supply |
| Pin 136 | I/O β User I/O pin (bank 4) |
| Pin 137 | I/O β User I/O pin (bank 4) |
| Pin 138 | I/O β User I/O pin (bank 4) |
| Pin 139 | I/O β User I/O pin (bank 4) |
| Pin 140 | GND β Ground |
| Pin 141 | TDI β JTAG Test Data In |
| Pin 142 | TMS β JTAG Test Mode Select |
| Pin 143 | TCK β JTAG Test Clock |
| Pin 144 | TDO β JTAG Test Data Out |
| Pin 145 | GND β Ground |
| Pin 146 | I/O β User I/O pin (bank 1) |
| Pin 147 | I/O β User I/O pin (bank 1) |
| Pin 148 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 149 | I/O β User I/O pin (bank 1) |
| Pin 150 | I/O β User I/O pin (bank 1) |
| Pin 151 | GND β Ground |
| Pin 152 | I/O β User I/O pin (bank 1) |
| Pin 153 | I/O β User I/O pin (bank 1) |
| Pin 154 | I/O β User I/O pin (bank 1) |
| Pin 155 | I/O β User I/O pin (bank 1) |
| Pin 156 | GND β Ground |
| Pin 157 | I/O β User I/O pin (bank 1) |
| Pin 158 | I/O β User I/O pin (bank 1) |
| Pin 159 | I/O β User I/O pin (bank 1) |
| Pin 160 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 161 | I/O β User I/O pin (bank 1) |
| Pin 162 | I/O β User I/O pin (bank 1) |
| Pin 163 | I/O β User I/O pin (bank 1) |
| Pin 164 | I/O β User I/O pin (bank 1) |
| Pin 165 | GND β Ground |
| Pin 166 | I/O β User I/O pin (bank 1) |
| Pin 167 | I/O β User I/O pin (bank 1) |
| Pin 168 | I/O β User I/O pin (bank 1) |
| Pin 169 | I/O β User I/O pin (bank 1) |
| Pin 170 | VCCINT β Core 3.3V supply |
| Pin 171 | I/O β User I/O pin (bank 1) |
| Pin 172 | I/O β User I/O pin (bank 1) |
| Pin 173 | I/O β User I/O pin (bank 1) |
| Pin 174 | I/O β User I/O pin (bank 1) |
| Pin 175 | GND β Ground |
| Pin 176 | I/O β User I/O pin (bank 2) |
| Pin 177 | I/O β User I/O pin (bank 2) |
| Pin 178 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 179 | I/O β User I/O pin (bank 2) |
| Pin 180 | I/O β User I/O pin (bank 2) |
| Pin 181 | GND β Ground |
| Pin 182 | I/O β User I/O pin (bank 2) |
| Pin 183 | I/O β User I/O pin (bank 2) |
| Pin 184 | I/O β User I/O pin (bank 2) |
| Pin 185 | I/O β User I/O pin (bank 2) |
| Pin 186 | GND β Ground |
| Pin 187 | I/O β User I/O pin (bank 2) |
| Pin 188 | I/O β User I/O pin (bank 2) |
| Pin 189 | I/O β User I/O pin (bank 2) |
| Pin 190 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 191 | I/O β User I/O pin (bank 2) |
| Pin 192 | I/O β User I/O pin (bank 2) |
| Pin 193 | I/O β User I/O pin (bank 2) |
| Pin 194 | I/O β User I/O pin (bank 2) |
| Pin 195 | GND β Ground |
| Pin 196 | I/O β User I/O pin (bank 2) |
| Pin 197 | I/O β User I/O pin (bank 2) |
| Pin 198 | I/O β User I/O pin (bank 2) |
| Pin 199 | I/O β User I/O pin (bank 2) |
| Pin 200 | VCCINT β Core 3.3V supply |
| Pin 201 | I/O β User I/O pin (bank 2) |
| Pin 202 | I/O β User I/O pin (bank 2) |
| Pin 203 | I/O β User I/O pin (bank 2) |
| Pin 204 | I/O β User I/O pin (bank 2) |
| Pin 205 | GND β Ground |
| Pin 206 | OE1 β Output Enable / global control |
| Pin 207 | OE2/GCLK β Output Enable or Global Clock input |
| Pin 208 | CLR β Global Clear (active high) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3256AQI208-10 is suitable for 7 applications: PCI Bus Interface Glue Logic, Microcontroller Address Decoding & Bus Steering, Industrial Control State Machines, I/O Expansion & Parallel Interface Bridging, Legacy Peripheral Replacement & Board Modernization, Interrupt Steering & System Arbiter, Test & Measurement Front-End Logic.
PCI Bus Interface Glue Logic
The EPM3256AQI208-10 is a natural fit for PCI Local Bus Specification Revision 2.2 compliant glue logic, which the MAX 3000A family explicitly supports per the Altera datasheet. Its 10ns tPD and 95.2 MHz fCNT cover 33 MHz PCI timing with margin, while 161 user I/Os absorb a 32-bit address/data bus plus control signals (FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PAR, PERR#, SERR#). Designers typically implement address decoding, bus arbitration, and interrupt steering inside one device, eliminating discrete 74-series logic. The 3.3V core with MultiVolt I/O interoperates with both 5V and 3.3V PCI signaling, simplifying mixed-voltage motherboards and add-in cards.
Recommended
Microcontroller Address Decoding & Bus Steering
The EPM3256AQI208-10 serves as a deterministic, instant-on decoder between a microcontroller and multiple peripherals (memory, sensors, communication ICs). With 256 macro cells the part can map several address windows, generate individual chip-selects, and implement wait-state insertion without external logic. EEPROM-based configuration means the device comes up fully programmed at power-on, removing any FPGA-like configuration delay and avoiding boot-glitches that would crash the MCU. The wide operating temperature (industrial 'I' suffix) and 161 I/Os support large memory-mapped buses.
Recommended
Industrial Control State Machines
The EPM3256AQI208-10's 256 macro cells comfortably host multi-state control machines for industrial equipment such as conveyor controllers, packaging machinery, and PLC I/O expansion. Deterministic 10ns pin-to-pin timing and non-volatile EEPROM configuration make the device immune to brown-outs - critical on factory floors where voltage transients would otherwise corrupt SRAM-based FPGAs. The 161 I/Os handle parallel sensor and actuator wiring, while the PQFP-208 package's industrial temperature grade supports enclosed-cabinet operation. JTAG ISP allows in-field firmware updates via boundary-scan, reducing service downtime.
Recommended
I/O Expansion & Parallel Interface Bridging
The EPM3256AQI208-10 expands MCU GPIO counts and bridges mismatched parallel interfaces (e.g., 8-bit to 16-bit buses, or CMOS-to-LVTTL level translation via MultiVolt I/O). Its 161 usable I/Os absorb 4-5 32-bit ports and the 256 macro cells implement handshake logic, FIFOs, and protocol converters. The MultiVolt feature lets the device mix 5V peripherals with a 3.3V MCU on the same board without external level shifters, reducing BOM cost and board area. PCI 2.2 compliance also covers many general-purpose bus interfaces.
Recommended
Legacy Peripheral Replacement & Board Modernization
The EPM3256AQI208-10 is widely used to replace multiple discrete TTL/CMOS glue-logic ICs (74-series, 4000-series, simple PAL/GALs) on legacy boards. Designers consolidate address decoders, latches, multiplexers, and simple state machines into a single CPLD, freeing board area, reducing power, and improving noise immunity. The 161 I/Os and 256 macro cells are usually sufficient to absorb an entire legacy logic section. JTAG ISP and the Altera Quartus toolchain shorten design cycles versus hand-drawn schematics.
Recommended
Interrupt Steering & System Arbiter
The EPM3256AQI208-10 implements multi-source interrupt steering and bus arbitration for systems with several masters (MCU + DMA + peripheral controllers). Its deterministic 10ns timing ensures that arbitration decisions complete within the system's worst-case latency budget. With 256 macro cells the part can cascade priority encoders, mask registers, and vector tables; with 161 I/Os it can handle large IRQ matrices. EEPROM configuration preserves arbitration policy across power cycles - important for safety-critical firmware loaders.
Recommended
Test & Measurement Front-End Logic
The EPM3256AQI208-10 supports test-equipment front-end logic where deterministic timing matters: waveform gating, trigger routing, multiplexer control, and pattern generation. Its 95.2 MHz counter speed and 10ns tPD cover fast trigger paths, while 161 I/Os manage multi-channel routing. PCI 2.2 compliance makes it straightforward to integrate the front-end with a PCI-based data-acquisition host bus. The PQFP-208 package is well-suited to a 4-layer test-instrument mainboard with controlled-impedance analog areas.
Recommended
Recommended Products Summary
Engineering reference data for EPM3256AQI208-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3256AQC208-10 | EPM3256AQC208-10N | EPM3256AQI208-10N | EPM3256AQC208-7 |
|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same |
| Brand | Altera | Altera (same brand) | Altera (same brand) | Altera (same brand) | Altera (same brand) |
| Macro Cells | 256 | 256 | 256 | 256 | 256 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 7 ns (faster) |
| Temperature Grade | Industrial (0C to 70C) | Commercial (0C to 70C) | Commercial, lead-free | Industrial, lead-free | Commercial |
| RoHS / Lead-Free | RoHS compliant (Q suffix) | RoHS compliant (Q) | Lead-free (N suffix) | Lead-free (N suffix) | RoHS compliant (Q) |
| Usable Gates | 5,000 | 5,000 | 5,000 | 5,000 | 5,000 |
| User I/Os | 161 | 161 | 161 | 161 | 161 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest logic density in the MAX 3000A family (vs EPM3128ATC144-10)
- PCI Local Bus 2.2 compliant (vs EPM3064ATC100-10)
- EEPROM non-volatile configuration (instant-on) (vs SRAM-based FPGAs (e.g., Cyclone series))
Design Notes
Decouple each VCCIO bank and VCCINT rail separately. Place a 0.1 uF ceramic capacitor as close as possible to every VCC pin group (typically one per pin pair as defined in the MAX 3000A datasheet pinout), plus a 10 uF bulk tantalum or ceramic near the package. MultiVolt I/O banks may be powered independently at 2.5V, 3.3V, or 5V - never float any VCCIO pin. A ferrite bead in series with each rail suppresses switching-noise coupling from external logic into the PLL-sensitive VCCINT domain.
PQFP-208 has 0.5 mm pitch gull-wing leads per JEDEC MS-022. Use a 4-layer PCB with continuous ground plane under the device for controlled-impedance signal return paths. Route JTAG signals (TCK, TMS, TDI, TDO) with 50-ohm characteristic impedance and keep them clear of high-current switching traces. Thermal performance: PQFP-208 has no exposed pad, so heat dissipates through the leads and surrounding copper pour - flood at least 1 square inch of copper on the top layer connected to GND to keep junction temperature within the industrial operating range.
Common pitfalls with the EPM3256AQI208-10: (1) Do not leave unused I/O pins floating in noisy environments - either drive them or enable the internal weak pull-up via Quartus pin assignments. (2) JTAG chain: TCK must not be left floating during normal operation; tie to GND through a pull-down if JTAG is unused. (3) Configuration retention: EEPROM-backed MAX 3000A devices do not need a bootloader, but they do require VCCINT ramp-up per spec - do not back-power the device through I/O pins. (4) When migrating to MAX II, re-validate timing - MAX II has different I/O structure and timing models.
At 95.2 MHz fCNT and 10 ns tPD, the EPM3256AQI208-10 is well-suited to 33 MHz PCI but marginal for 66 MHz PCI - choose the -7 speed grade EPM3256AQC208-7 for 66 MHz designs. Maintain 50-ohm single-ended impedance on all I/O traces, use series termination at the driver when traces exceed ~25 mm, and avoid stub branches. For MultiVolt 5V-tolerant outputs into 3.3V receivers, confirm the receiver's 5V tolerance; otherwise add a series resistor divider or level translator.
Compliance Information
RoHS compliant per Altera/Intel product marking ('Q' suffix in part number denotes lead-free per legacy ordering code). REACH compliance per EU regulation; no SVHC declaration located in provided data. AEC-Q100 not applicable for industrial-grade CPLDs. Conflict-minerals declaration available from Altera/Intel.
