EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
MPN: EPM7128SQC160-6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 250 | $12.4 | $3,100.00 |
| 500 | $11.1 | $5,550.00 |
Drop-in alternatives for EPM7128SQC160-6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128SQC160-6N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128SQC160-6F
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128SQC160-10
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →EPM7128SQC160-10N
✅ Drop-In✓ In Stock
$9.2 / Unit
View Datasheet →EPM7128SQC160-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPM7128SQC160-15N
✅ Drop-In✓ In Stock
$23 / Unit
View Datasheet →EPM7128SQC160-6 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000S |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2500 |
| User I/O Pins | 100 |
| Logic Array Blocks (LABs) | 4 |
| Pin-to-Pin Propagation Delay (tPD) | 6 ns |
| Maximum Internal Frequency (fMAX) | 147.1 MHz |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | 0.5 µm CMOS EEPROM |
| Programmable Type | In-System Programmable (ISP) via JTAG |
| Operating Temperature (Commercial) | 0 °C to +70 °C |
| Package | 160-Pin PQFP (28 × 28 mm) |
| Mounting Type | Surface Mount |
| Supplier Device Package | 160-PQFP (28×28) |
| JTAG Support | Yes (IEEE Std 1149.1) |
EPM7128SQC160-6 160-pqfp (28×28) Pin Configuration Guide
Complete pinout information for EPM7128SQC160-6 (160-pqfp (28×28) package) with 100 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM7128SQC160-6.
Refer to the datasheet for full pin configuration.
Estimated pin count: 100 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC160-6 is suitable for 6 applications: Microprocessor Address Decoding, Asynchronous Bus Interface Bridging, Peripheral Controller (UART, Timers, Interrupt Controller), I/O Expansion and Level Translation, Legacy Industrial Control (5 V Glue Logic), State Machine and Protocol Encoder.
Microprocessor Address Decoding
The EPM7128SQC160-6 is widely used for address decoding on 8/16/32-bit microprocessor buses such as 8051, x86, 68k, and PowerPC. Its 6 ns pin-to-pin propagation delay fits comfortably under one 33 MHz bus cycle, ensuring glitch-free chip-select generation. The 128 macrocells comfortably absorb multi-bank memory maps with 4-8 chip selects per block, while the 100 user I/Os handle wide address/data/control buses without external muxing. The non-volatile EEPROM cells retain configuration through power cycles, eliminating external boot PROMs. Designers typically enter a Boolean equation for each chip-select in MAX+PLUS II or Quartus and rely on deterministic timing closure that CPLDs provide better than FPGAs.
Recommended
Asynchronous Bus Interface Bridging
The EPM7128SQC160-6 bridges asynchronous buses between processors, peripherals, and memory devices (e.g., ISA-to-PCMCIA, VME-to-PCI legacy bridges). Its 100 user I/Os and 5 V tolerance on all pins simplify mixed-voltage bridging on legacy boards. The 6 ns tPD handles handshaking protocols like DTACK, READY, and WAIT insertion without metastability, and the in-system JTAG port lets field technicians update bridging logic without desoldering. With 4 LABs and predictable interconnect delays, the CPLD produces equal-length paths across all handshake signals - critical for parallel bus integrity where skew causes intermittent read/write failures.
Recommended
Peripheral Controller (UART, Timers, Interrupt Controller)
The EPM7128SQC160-6 implements a discrete UART, programmable interval timer, or interrupt controller on legacy 5 V systems. Its 128 macrocells hold a 16550-compatible UART plus DMA handshake logic, or a multi-channel 8254 timer, all within one package. The 6 ns speed grade supports baud rates above 1 Mbaud, and the 5 V I/O directly drives RS-232 transceivers without level shifters. Engineers use MAX+PLUS II schematic capture or VHDL to map the peripheral register set into macrocells, achieving deterministic interrupt latency that soft microcontrollers on FPGAs cannot match. The non-volatile configuration survives brown-outs without bootloader code.
Recommended
I/O Expansion and Level Translation
The EPM7128SQC160-6 expands I/O count and translates between 5 V and 3.3 V logic on mixed-voltage boards. With 100 user I/Os, it functions as a large fan-out buffer or a level-translating bridge for 5 V MCUs talking to 3.3 V peripherals. The 5 V-tolerant I/Os interface directly to legacy TTL, while internal logic level-shifts to LVCMOS-3.3 outputs. Designers often implement GPIO expanders, keypad scanners, or LED multiplexers here, taking advantage of the 6 ns propagation delay for glitch-free scanning at kHz to low-MHz refresh rates. The JTAG port also lets production engineers reconfigure the I/O map for board revisions.
Recommended
Legacy Industrial Control (5 V Glue Logic)
The EPM7128SQC160-6 is a workhorse in legacy industrial PLCs, motor controllers, and instrumentation that still uses 5 V logic. The 5 V supply tolerance matches industrial 24 V→5 V DC-DC rails directly, and the 100 user I/Os absorb dozens of optocoupler inputs and relay-driver outputs. Its deterministic timing makes it ideal for safety-critical state machines where worst-case propagation must be known a priori - a key advantage over FPGAs. The PQFP-160 footprint and 0 °C to +70 °C commercial range fit standard 4-layer industrial boards. With lifecycle now obsolete, designers maintain existing lines using Rochester Electronics stock and consider MAX II for new builds.
Recommended
State Machine and Protocol Encoder
The EPM7128SQC160-6 implements high-speed state machines for protocol encoding (SPI, I²C, custom serial), pulse generation, and waveform synthesis. Its 128 macrocells comfortably hold 16-32 state machines of moderate complexity, and the 6 ns tPD supports bit rates above 50 Mbps in custom protocols. The deterministic timing and absence of configuration bitstream (unlike FPGAs) means no boot-time delay - the CPLD is operational within microseconds of power-up. JTAG-based ISP allows field reprogramming of state-machine logic without removing the device from the PCB, useful for production-line tuning. Common uses include stepper-motor sequencers, custom LCD controllers, and proprietary RF baseband encoders.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC160-6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC160-6N | EPM7128SQC160-6F | EPM7128SQC160-10 | EPM7128SQC160-10N | EPM7128SQC160-15 | EPM7128SQC160-15N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) | 160-PQFP (28x28 mm) |
| Pin-to-Pin Delay (tPD) | 6 ns | 6 ns | 6 ns | 10 ns | 10 ns | 15 ns | 15 ns |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O | 100 | 100 | 100 | 100 | 100 | 100 | 100 |
| Supply Voltage | 5 V (4.75 V - 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Max Internal Frequency (fMAX) | 147.1 MHz | 147.1 MHz | 147.1 MHz | ~125 MHz | ~125 MHz | ~100 MHz | ~100 MHz |
| Pb-Free / Lead-Free | Standard (Pb-bearing) | Yes (Pb-free) | Standard (Pb-bearing) | Standard (Pb-bearing) | Yes (Pb-free) | Standard (Pb-bearing) | Yes (Pb-free) |
| Operating Temperature | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Industrial variant (0 °C to +70 °C labeled F) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest readily-available speed grade in MAX 7000S 160-pin PQFP (vs EPM7128SQC160-10)
- Pb-free reflow profile compatibility in the same package (vs EPM7128SQC160-6N)
- Higher macrocell density within the same PQFP-160 family (vs EPM7128SQC160)
- Non-volatile EEPROM configuration vs SRAM FPGAs (vs Cyclone series FPGAs)
Design Notes
The EPM7128SQC160-6 requires a stable 5 V ±5 % supply. Decouple VCC with a 100 µF bulk capacitor near the PQFP-160 plus a 0.1 µF ceramic per supply pin pair (VCC/GND). Add a 10 µF tantalum and a ferrite bead on the 5 V rail feeding the CPLD to suppress switching noise from neighbouring digital ICs. The I/Os source/sink up to 24 mA per pin (per-pin limit); total simultaneous switching current must not exceed the package's ICC limit - derate by 30 % if more than 32 outputs switch simultaneously at high frequency. Estimated: 128 macrocells @ 20 % utilization ≈ 100 mA quiescent + I/O contribution.
Route all four dedicated GND pins (and any unused GND-adjacent pads) directly to a continuous ground plane on the top or second layer. Place the JTAG connector (TCK, TMS, TDI, TDO) within 50 mm of the device and add 4.7 kΩ pull-ups on TMS and TDI, with a 4.7 kΩ pull-down on TCK per IEEE 1149.1. Keep clock inputs (GCLK1, GCLK2) shorter than 25 mm and away from switching I/O. PQFP-160 packages benefit from a 4-layer PCB with dedicated power and ground planes for signal integrity; 2-layer boards may fail timing at fMAX above 100 MHz.
Common pitfalls: (1) Forgetting to enable the JTAG pins with the JTAG instruction register, locking out ISP - always load the JTAG instruction to BYPASS or EXTEST before power-down. (2) Assigning I/O pins to JTAG functions inadvertently, which disables normal I/O - reserve TCK/TMS/TDI/TDO via the device pin assignment. (3) Using 3.3 V peripherals on EPM7128 I/O outputs without level translation - the EPM7128 outputs 5 V CMOS levels and may damage 3.3 V-only devices. (4) Exceeding the maximum I/O toggle rate during simultaneous switching, which causes ground bounce and false clocking - estimate: 32 outputs @ 50 MHz produce 1.6 A peak transient.
For designs where signals exceed 50 MHz or fan out to more than 8 loads, use 33 Ω series-termination resistors at the CPLD outputs. The PQFP-160 lead inductance (~5 nH per pin) becomes significant above 75 MHz; controlled-impedance traces (50 Ω microstrip on 4-layer boards) are recommended. Avoid point-to-point topology for clocks - use a short stub or H-tree. Add a 33 Ω resistor in series with TCK if JTAG chain exceeds 200 mm. Estimated: PQFP-160 lead inductance of ~5 nH creates ~7 % overshoot at 100 MHz transitions on 50 Ω traces - termination dampens the ring.
Compliance Information
Original EPM7128SQC160-6 is Pb-bearing per MAX 7000S family datasheet (lead-free variants carry -N suffix). RoHS compliance is only via the -6N variant. No AEC-Q100 qualification - this is a commercial/industrial-grade CPLD. REACH and conflict-mineral compliance status not in verified data.
