EPM9560RC/ARC240 - MAX 9000 CPLD, 560 Macrocells, 240-Pin RQFP | Altera
MPN: EPM9560RC/ARC240 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85.5 | $855.00 |
| 100 | $76 | $7,600.00 |
| 500 | $68.5 | $34,250.00 |
| 1,000 | $61 | $61,000.00 |
Drop-in alternatives for EPM9560RC/ARC240 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560ARC240-10
β Drop-Inβ In Stock
$28.8 / Unit
View Datasheet βEPM9560RC240-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9560RC240-20
β Drop-Inπ Reference alternative (not in catalog)
EPM9560ARC240-10N
β Drop-Inβ In Stock
$19.5 / Unit
View Datasheet βEPM9560ARI240-10
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9560ARI240-10N
β Drop-Inβ In Stock
$105 / Unit
View Datasheet βEPM9560RC/ARC240 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Logic Cells / Macrocells | 560 macrocells |
| Usable Gates | 12,000 gates |
| Maximum User I/Os | 191 (240-pin RQFP variant) |
| Number of Logic Array Blocks (LABs) | 35 LABs of 16 macrocells each |
| Supply Voltage | 5.0 V |
| Internal Frequency | 144.9 MHz (typical) |
| Propagation Delay (tPD) | 10 ns (speed grade -10) |
| Pin-to-Pin Logic Delay | 16 ns typical |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) |
| Global Clock Networks | 4 |
| Package | 240-pin RQFP (Plastic Quad Flatpack) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) |
EPM9560RC/ARC240 Pin Configuration
| Pin 1 | I/O β User I/O - macrocell pin |
| Pin 60 | GND β Ground |
| Pin 120 | VCC β 5.0 V supply |
| Pin 180 | I/O β User I/O - macrocell pin |
| Pin 211 | TDI β JTAG Test Data In |
| Pin 212 | TMS β JTAG Test Mode Select |
| Pin 213 | TCK β JTAG Test Clock |
| Pin 214 | TDO β JTAG Test Data Out |
| Pin 215 | GLOBAL_CLK1 β Global clock input 1 |
| Pin 216 | GLOBAL_CLK2 β Global clock input 2 |
| Pin 217 | GLOBAL_CLK3 β Global clock input 3 |
| Pin 218 | GLOBAL_CLK4 β Global clock input 4 |
| Pin 240 | INPUT/GCLK β Dedicated input/global clock pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC/ARC240 is suitable for 6 applications: Microprocessor Bus Decode and Address Mapping, Legacy Industrial Glue Logic Replacement, Peripheral Interface Bridging, State-Machine Control and Sequencing, Address Demultiplexing for Memory Banks, Test Equipment and Instrumentation Front-End.
Microprocessor Bus Decode and Address Mapping
The EPM9560RC/ARC240 excels at 32-bit and 64-bit microprocessor bus decode with its 560 macrocells and 191 user I/Os, allowing the entire chip-select and address-decoding logic for a CPU/memory/peripheral system to be consolidated in a single non-volatile device. With 10 ns tPD on the -10 speed grade, address decoding completes within one clock cycle of systems running up to ~80 MHz. Unlike SRAM FPGAs, the MAX 9000 EEPROM-based architecture means the device boots instantly with no external PROM, simplifying board design. Place the CPLD between the CPU address bus and each peripheral chip-select pin, with the JTAG chain reserved for in-field firmware updates.
Recommended
Legacy Industrial Glue Logic Replacement
The EPM9560RC/ARC240 is widely deployed as glue logic on legacy industrial backplanes and factory automation controllers, where 5 V-tolerant I/O and high pin count eliminate the need for multiple 74-series TTL parts. The MAX 9000 architecture's deterministic tPD timing model is critical for handshake-based protocols where race conditions would be catastrophic. Up to 191 user I/Os handle dozens of mixed signals in one device, and 12,000 usable gates replace entire boards of discrete logic. The 5 V supply and TTL-compatible thresholds remain compatible with older industrial subsystems that have not migrated to 3.3 V.
Recommended
Peripheral Interface Bridging
When bridging between mismatched peripheral buses (ISA, VME, PC/104, SCSI, or proprietary parallel protocols), the EPM9560RC/ARC240 provides the protocol-conversion glue logic with non-volatile single-chip simplicity. With 16 dedicated input pins, 4 global clock networks, and 560 macrocells, complex state machines for handshaking, FIFO control, and byte-swapping are absorbed into one CPLD. The deterministic pin-to-pin delay of 16 ns typical simplifies protocol timing closure. JTAG-based in-system programmability allows field firmware updates without removing the board from the chassis.
Recommended
State-Machine Control and Sequencing
Complex state machines for motor control sequencing, power-supply start-up/shut-down coordination, and fault-handling logic fit naturally in the EPM9560RC/ARC240's macrocell array. Each macrocell includes a programmable flip-flop with selectable registered/combinatorial paths, making the device efficient for Mealy/Moore state-machine implementation. The 144.9 MHz maximum internal frequency supports high-speed sequencer loops. With 4 global clock networks, multiple asynchronous state machines can be synchronized without external clock-distribution buffers.
Recommended
Address Demultiplexing for Memory Banks
The EPM9560RC/ARC240 handles address demultiplexing and chip-select generation across multiple DRAM/SRAM banks in embedded memory subsystems. With 191 user I/Os, dozens of chip-select, output-enable, and write-enable signals are produced from a single address bus, eliminating discrete decoder chips. The 10 ns tPD on the -10 grade ensures row-address to chip-select timing is satisfied for fast SRAMs. The deterministic timing eliminates hold-time violations common with SRAM FPGA implementations.
Recommended
Test Equipment and Instrumentation Front-End
Test and measurement instruments use the EPM9560RC/ARC240 for front-panel logic, calibration sequencing, and signal-routing control. The deterministic timing model is essential where test-accuracy windows must be guaranteed regardless of routing. With 560 macrocells, complex self-test routines and calibration state machines fit in one device. The EEPROM-based configuration survives power cycles without reloading, eliminating calibration drift on bench-top equipment. JTAG boundary scan supports in-circuit testability during manufacturing.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC/ARC240 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC240-10 | EPM9560RC240-15 | EPM9560RC240-20 | EPM9560ARC240-10N | EPM9560ARI240-10 | EPM9560ARI240-10N |
|---|---|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade suffix] | 10 ns | 15 ns | 20 ns | 10 ns | 10 ns | 10 ns |
| Operating Temperature | [DATA_NEEDED: -10/-15/-20 grade commercial 0-70C default] | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C | -40 C to +85 C |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| RoHS / Lead-Free | [DATA_NEEDED: depends on specific suffix -10 vs -10N] | Leaded | Leaded | Leaded | Lead-free (RoHS) | Leaded | Lead-free (RoHS) |
Key Differentiators
- Highest-density MAX 9000 member in 240-pin RQFP package (vs EPM9560ARC208-10 (208-pin variant))
- Industrial temperature option available with pin-compatible ARI variant (vs EPM9480RC240-15 (MAX 9000 lower-density predecessor))
- Lead-free RoHS-compliant assembly option (vs EPM9560ARC240-10 (leaded variant))
Design Notes
Place 0.1 uF ceramic decoupling capacitors within 100 mils of every VCC/GND pair on the EPM9560RC/ARC240. The MAX 9000 EEPROM array draws transient current peaks during in-system programming (ISP), and inadequate decoupling causes programming failures and JTAG chain errors. Use a bulk 10 uF tantalum or ceramic capacitor near the device's primary VCC pin to handle ISP programming surges. With multiple VCC pins distributed around the 240-pin RQFP package, ensure each one has dedicated local decoupling.
The 240-pin RQFP package has 0.500 mm terminal pitch, requiring careful PCB layout to avoid solder bridging during assembly. Use a solder paste stencil with apertures 80% of the pad size, and reflow with a profile matching the package's moisture sensitivity level (MSL). For prototype builds, hand-soldering the fine-pitch RQFP is impractical; use a hot-air rework station or reflow oven. Reserve PCB space for a JTAG header (TDI/TDO/TMS/TCK) for in-system programming access.
The 240-pin RQFP package has limited heat dissipation, and the EPM9560RC/ARC240 can dissipate up to 1.5 W worst case with all 191 I/Os switching at high frequency. Estimated: at 5.0 V with 50% I/O toggling at 100 MHz, internal power is approximately 0.8 W. Above 70 C ambient, derate by 10 mW per degree C, or add a small heat-spreader copper pour beneath the package. For industrial temperature grades (-40 C to +85 C), thermal stress on solder joints is higher; conformal coating is recommended.
The MAX 9000 macrocell output drive is rated for standard TTL loads; for high-speed signals exceeding 50 MHz, use series damping resistors (22-33 ohm) near the CPLD output to reduce transmission-line reflections. Keep clock traces short and use a ground reference plane beneath all clock nets. The 4 global clock networks have lower skew than routed clocks - assign critical clocks to dedicated GCLK pins rather than general I/O.
Do not assume the EPM9560RC/ARC240 is RoHS-compliant without checking the specific suffix ('N' suffix indicates lead-free). Mixing leaded and lead-free parts on the same board violates RoHS assembly directives. Also, the MAX 9000's 5.0 V supply is not directly compatible with 3.3 V logic - level shifters are required for modern low-voltage interfaces. JTAG chain integrity must be verified by checking TCK/TMS pull-up resistors per IEEE 1149.1 specifications.
Compliance Information
RoHS/lead-free status depends on suffix (-10 vs -10N). Per Altera's MAX 9000 documentation, lead-free variants carry the 'N' suffix. No AEC-Q100 automotive qualification exists for this part - it is a legacy industrial/commercial CPLD.
