FPGA & CPLD
Products (6,800+)
EPM9480RC208-15N - MAX 9000 CPLD 480 Macro Cells | Altera
The Altera EPM9480RC208-15N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 10,000 usable gates, 480 macro cells, and a maximum operating frequency of 117.6 MHz, housed in a 208-pin RQFP (PowerQuad Flat Pack) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks with a programmable interconnect matrix, allowing designers to implement custom digital logic functions without fabricating a custom ASIC. CPLDs sit between simple PLDs (PAL/GAL) and FPGAs in the programmable logic hierarchy, offering deterministic timing, non-volatile configuration, and instant-on operation. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM-based configuration cells for non-volatile operation. Key features of the EPM9480RC208-15N include 480 macro cells organized into logic array blocks, 10,000 usable gates, a 15 ns pin-to-pin propagation delay (speed grade -15), and 117.6 MHz maximum internal frequency. The device provides 5.0 V in-system programmability via the JTAG interface, allowing field upgrades without removing the device from the board. The 208-pin RQFP package offers a high I/O count suitable for bus-intensive designs. The MAX 9000 architecture uses a programmable interconnect array (PIA) to route signals between logic array blocks, providing predictable timing independent of routing. Each macro cell contains a flip-flop and combinatorial logic, enabling both registered and combinatorial functions. The EEPROM configuration retains the design after power-down, eliminating the need for external configuration memory. Typical applications include glue logic consolidation, bus interface bridging, address decoding, state machine implementation, and legacy system maintenance. The 5.0 V operation makes it compatible with older TTL and CMOS logic families, simplifying integration into existing 5 V designs. When designing with this device, ensure the JTAG chain is properly terminated and that the ISP programming voltage is stable. The 208-pin RQFP package requires careful PCB layout to manage signal integrity on high-speed buses. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for evaluation and sourcing.
EPM9480RC208-20 - MAX 9000 CPLD, 12K Gates, 560 Macro Cells | Intel
The Intel (formerly Altera) EPM9480RC208-20 is a high-density Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates and 560 macro cells with a 20 ns pin-to-pin propagation delay in a 208-pin RQFP (Plastic Quad Flat Pack) surface-mount package. It is built on a 5V CMOS EEPROM-based architecture that provides non-volatile, in-system programmable logic with 100 percent factory-tested AC and DC characteristics. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL devices and high-density FPGAs. CPLDs use a classic PLA-style AND/OR macro cell fabric with non-volatile on-chip storage, giving them instant-on configuration, deterministic timing, and immunity to configuration memory corruption. The MAX 9000 family is the high-density, high-I/O extension of the classic Altera MAX architecture, providing predictable timing suitable for glue logic, bus interfacing, and state-machine decoding in industrial and telecommunications systems. Key features of the EPM9480RC208-20 include a 20 ns worst-case pin-to-pin delay through the Logic Array Blocks (LABs), 560 macro cells distributed across 16 LABs, and a maximum operating frequency of approximately 117.6 MHz for registered logic. The device operates from a 5V core supply with 5V-tolerant I/O on most pins, supports in-system programmability via the IEEE 1149.1 JTAG interface, and integrates a JTAG-based boundary-scan test capability for board-level test access. Architecturally, the EPM9480RC208-20 uses Altera's classic MAX 9000 multi-LAB structure with a global Programmable Interconnect Array (PIA) that routes signals between LABs with predictable delay. Each macro cell contains a programmable AND/OR array, a flip-flop, and a configurable I/O architecture, allowing designers to implement both combinatorial and registered logic with consistent timing regardless of placement. Typical applications include bus-interface and protocol-bridge logic (PCI, ISA, VME), address decoding and wait-state generation for microprocessors, glue logic between processors and peripherals, industrial control state machines, and legacy telecommunications backplane design. The instant-on non-volatile configuration makes the MAX 9000 family especially suited for applications where FPGA configuration time is unacceptable. When designing with the EPM9480RC208-20, ensure the 5V supply rail is well-decoupled with 0.1 uF ceramic capacitors placed close to each VCC pin group, and observe the 208-pin RQFP thermal envelope when operating at high toggle rates. Use the Altera MAX+PLUS II or Quartus design toolchain for entry, fitting, and JTAG programming. Designers migrating to newer products should evaluate MAX II or MAX V CPLDs as modern, lower-power alternatives. This page synthesizes distributor pricing from Octopart and DigiKey listings, drop-in pin-compatible alternatives from the same Altera MAX 9000 family, and practical design considerations not duplicated from the manufacturer datasheet.
EPM9480RC240-15 - MAX 9000 CPLD 480 Macro Cells 15ns | Altera
The Altera EPM9480RC240-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 480 macro cells, 12,000 usable gates, and a 15 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (32x32 mm) package operating from a 5.0 V supply. It is an in-system programmable (ISP) EEPROM-based PLD built on third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic device -> digital IC. MAX 9000 devices use EEPROM configuration cells, so they retain their design without an external boot PROM and are live within microseconds of power-up. Key features include 480 macro cells, 12,000 usable gates, 15 ns pin-to-pin delay (tPD), 5.0 V in-system programmability through a built-in IEEE Std. 1149.1 JTAG interface, and 4.75 V to 5.25 V internal supply operation. The 240-pin RQFP package provides up to 191 user I/O pins, enabling wide bus interfaces in a single device. The MAX 9000 architecture uses a Multiple Array MatriX of logic array blocks (LABs) interconnected by a fast, predictable routing structure. Because timing is fixed and deterministic, EPM9480RC240-15 designs do not require the timing closure iterations typical of SRAM-based FPGAs, which simplifies worst-case timing analysis for 5 V legacy systems. Typical applications include 5 V industrial control glue logic, ISA/PCI bus bridging, legacy telecom line-card control, test and measurement instrumentation, and replacement of discrete 74-series logic in existing designs. The 15 ns speed grade suits moderate-speed state machines and address decoding. When designing with this device, note that the MAX 9000 family is a mature, non-RoHS 5 V technology; verify availability and plan for a lifecycle strategy. Decouple every VCC pin with a 0.1 uF ceramic capacitor placed close to the package. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for the EPM9480RC240-15.
EPM9480RC240-20 - 480-Macrocell MAX 9000 CPLD, 240-RQFP | Altera
The Altera EPM9480RC240-20 is a 480-macrocell, 10,000-usable-gate Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 240-pin RQFP (Power Quad Flat Pack) package. Built on a third-generation Multiple Array MatriX (MAX) architecture in high-performance CMOS EEPROM technology, the device delivers a 20 ns maximum pin-to-pin propagation delay (tpd) and supports in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. The part operates from a 4.75 V to 5.25 V internal supply and supports configurable I/O signaling at 3.3 V or 5 V to bridge mixed-voltage system designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-backed programmable logic device that sits in the hierarchy between simple PLDs (PAL/GAL) and high-density FPGAs. Compared with FPGAs, CPLDs offer deterministic timing, instant-on non-volatile configuration, and superior I/O count per dollar for glue-logic, bus-interface, and state-machine tasks. The MAX 9000 family is Altera's high-density CPLD line, integrating multiple Logic Array Blocks (LABs) connected via a programmable interconnect array (PIA) and is used in system-level logic integration where multiple PAL/GAL or 22V10 devices would otherwise be needed. Key features include 480 macrocells (with 676 flip-flops per MAX 9000 family), 10,000 usable gates, 175 user I/O pins, a 100 MHz maximum clock frequency on related -C variants, and CMOS EEPROM technology. The 240-pin RQFP (32x32 mm) package provides mechanical robustness and a generous PCB footprint suitable for prototype boards and industrial backplane designs. The architecture integrates PAL/GAL/22V10-equivalent blocks plus FPGA-class functionality into a single non-volatile device. Typical applications include industrial bus interface bridging, legacy glue-logic consolidation (replacing multiple PAL/GAL/22V10 devices), state-machine controllers, address decoding, power-up sequencing for multi-rail systems, and telecom backplane controllers. Designers often select the MAX 9000 family when non-volatile instant-on behavior and deterministic 20 ns timing are required, and when 175+ I/O pins are needed in a single device. When designing with this part, perform a complete thermal analysis because the 240-pin RQFP package dissipates more power than smaller BGA packages. Reference Altera Application Note 74 (Evaluating Power for Altera Devices) for power budgeting. Use the JTAG interface (IEEE 1149.1) for in-system programming and boundary-scan test; ensure your programmer supports MAX 9000 ISP via the ByteBlaster or compatible cable. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes not found in the manufacturer datasheet itself.
EPM9560ABC356-10 - MAX 9000 CPLD, 560 Macrocells, 356-BGA | Altera
The Altera (Intel) EPM9560ABC356-10 is a high-density CMOS EEPROM-based CPLD from the MAX 9000 device family, delivering 12,000 usable gates and 560 macrocells in a 356-ball LBGA package with 216 user I/Os. The "-10" speed grade corresponds to a 10 ns pin-to-pin logic delay and supports internal counter frequencies up to 144 MHz, making it one of the highest-density members of the legacy MAX 9000A family. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays on a single die with a global interconnect fabric. Architecturally, a CPLD sits between simple SPLDs/GALs and high-density FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA. The MAX 9000A family uses Altera's third-generation Multiple Array MatriX (MAX) architecture with dual-output macrocells that allow independent use of combinatorial and registered logic on each output. Key features of the EPM9560ABC356-10 include 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, 35 Logic Array Blocks (LABs), full PCI Local Bus Specification Revision 2.2 compliance for plug-and-play peripheral designs, and operation from a single 4.75 V to 5.25 V supply. Commercial temperature grade (0 °C to 70 °C) and a 356-LBGA (35 x 35 mm) surface-mount package suit it for high-I/O glue-logic and bus-interface designs. From a technical perspective, each macrocell contains a programmable AND/OR array, a flip-flop, and dual outputs that can drive registered and combinatorial paths independently. The 10 ns tPD and 144 MHz fCNT enable the device to meet PCI 2.2 timing constraints at 33 MHz without wait-state insertion. 5-V ISP allows board-level reconfiguration through the JTAG chain, eliminating the need for an external PROM programmer and supporting manufacturing flow updates. Typical applications include PCI bus interface and bridge logic, high-performance glue logic between processors and peripherals, bus multiplexing and address decoding, and legacy industrial control systems. The high I/O count (216 user I/Os) and PCI compliance make it especially valuable where dense, deterministic logic is required between processors, memory, and peripheral ASICs. When designing with the EPM9560ABC356-10, ensure the JTAG chain integrity and provide clean 5 V power with adequate decoupling. Engineers migrating to newer designs should note that the MAX 9000 family is mature/legacy - verify long-term supply before new product introduction and consider MAX II or MAX V devices for new designs unless exact pin compatibility is required. This page synthesizes distributor inventory, parametric alternatives, and practical design notes not found in the original Altera datasheet alone.
EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel
The Intel (Altera) EPM9560ARC208-10 is a MAX 9000A family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 153 user I/O pins in a 208-pin RQFP (PowerQuad/plastic quad flat pack) package, with a 10 ns pin-to-pin propagation delay and 5.0 V CMOS EEPROM-based in-system programmability. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks and a programmable interconnect matrix on a single die, providing deterministic non-volatile logic that is active immediately at power-up. In the logic hierarchy, a CPLD sits between simple glue logic (PAL/GAL) and full FPGAs: CPLDs offer lower density but predictable timing, single-chip non-volatility, and no external configuration memory. The MAX 9000 family uses a third-generation Multiple Array MatriX (MAX) architecture with EEPROM cells, so configuration is retained without a battery or boot PROM. Key features of the EPM9560ARC208-10 include 560 macrocells organized into 35 logic array blocks, 12,000 usable gates, 153 user I/O pins, a 10 ns maximum pin-to-pin propagation delay (speed grade -10), and an internal frequency of up to 144.9 MHz. The device operates from a 5.0 V supply and is specified over the commercial 0 C to +70 C temperature range. In-system programmability (ISP) via the IEEE 1149.1 JTAG boundary-scan interface allows field upgrades without removing the device from the board. The MAX 9000 architecture routes signals through a programmable interconnect array that provides uniform, predictable delays, unlike segmented FPGA routing. This makes the EPM9560ARC208-10 well suited to address decoding, bus bridging, state machines, and legacy glue-logic consolidation where deterministic timing matters more than raw gate count. The 208-pin RQFP package with exposed pad supports surface mounting and provides a manageable thermal path for the 5 V CMOS core. Typical applications include industrial control backplanes, telecommunications line cards, test-and-measurement instruments, and legacy system maintenance where an existing MAX 9000 design must be reproduced or repaired. Because the MAX 9000 family is mature, designers should confirm lifecycle status and consider pin-compatible MAX 9000A speed-grade variants or a migration path to MAX II/MAX V devices for new designs. When designing with this device, decouple every VCC pin with a 0.1 uF ceramic capacitor placed close to the pin, and provide a clean 5.0 V rail with less than 5% ripple. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera
The Altera EPM9560ARC208-10N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, 153 user I/O pins, and a 10 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It is a 5 V in-system-programmable EEPROM-based PLD built on Altera's third-generation MAX architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural structure of a PAL with the density and flexibility of an FPGA. CPLDs sit between simple glue logic and full FPGAs in the programmable logic hierarchy: they offer non-volatile configuration, deterministic pin-to-pin timing, and low standby power, making them ideal for address decoding, bus bridging, state machines, and interface glue. The MAX 9000 family extends this concept to 6,000-12,000 usable gates with counter speeds up to 144 MHz. Key features of the EPM9560ARC208-10N include 560 macrocells organized in 20 LABs, 153 user I/O pins, 10 ns pin-to-pin delay, 144.9 MHz internal counter frequency, and 5 V CMOS EEPROM technology that retains configuration without an external boot device. The EEPROM-based architecture allows in-system programming (ISP) via the JTAG interface, eliminating the need for a separate configuration PROM. The MAX 9000 architecture uses a Multiple Array MatriX (MAX) structure with product-term logic, providing predictable timing independent of routing. This deterministic timing behavior is a key advantage over SRAM-based FPGAs for safety-critical and real-time control applications where worst-case delay must be guaranteed. Typical applications include industrial control backplanes, telecommunications line cards, PCI/ISA bus interfaces, instrumentation front-ends, and legacy system replacement where 5 V logic compatibility is required. The 208-pin RQFP package provides 153 I/O pins for wide bus interfacing. When designing with this device, note that it is a 5 V core part and requires 5 V supply rails; level shifting is needed when interfacing with 3.3 V or lower logic. The EEPROM configuration is retained for over 20 years, but the device is now obsolete and should be designed out for new projects. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and migration decisions.
EPM9560ARC240-10 - MAX 9000 CPLD 560 Macrocells 144.9MHz | Altera
The Altera EPM9560ARC240-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 12,000 usable gates, 560 macrocells, and 216 user I/Os in a 240-pin PowerQuad QFP (RQFP/EAR240) package. Operating at 5.0V with an internal frequency of up to 144.9 MHz and a pin-to-pin propagation delay of 11.4 ns, this device is built on the third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that combines the integration density of FPGAs with the predictable timing and low power of PAL/GAL architectures. Within the broader semiconductor taxonomy, the CPLD sits under Programmable Logic > Programmable Logic Device > Logic ICs > Integrated Circuits. CPLDs are characterized by coarse-grained macrocell fabric with non-volatile EEPROM or flash configuration memory, instant power-on behavior (no boot time), deterministic pin-to-pin timing, and typical use in glue-logic, bus interfacing, and state-machine replacement roles. The MAX 9000 architecture integrates multiple Logic Array Blocks (LABs) connected via a programmable interconnect array, each LAB containing 16 macrocells with configurable product-term logic. The EPM9560ARC240-10's 560 macrocells support complex combinatorial and registered logic functions, while 191-216 user I/Os (depending on package variant) provide extensive external connectivity for bus and peripheral bridging. The EEPROM configuration cell ensures the device operates instantly at power-up with no external boot memory. Designed on a high-performance 5.0-V CMOS EEPROM process, the device supports selectable 3.3-V or 5.0-V I/O pin operation through separate VCCINT (internal logic supply) and VCCIO (I/O driver supply) pins. This dual-rail I/O capability makes it compatible with both legacy 5V systems and modern 3.3V peripherals without level translation. The 240-pin RQFP package provides high pin count for I/O-rich designs in industrial, telecom, and embedded systems. Typical applications include bus-bridging logic (ISA/PCI to local bus), state-machine and sequencer replacement in industrial controllers, glue logic for ASIC/ASSP integration, address decoding in microprocessor systems, and legacy 5V telecom equipment. Its instant-on characteristic also suits safety-critical systems where deterministic startup behavior is required. When designing with this device, ensure VCCINT and VCCIO rails are properly decoupled with 0.1uF and 10uF capacitors placed close to the respective pins, and verify that the chosen package variant's I/O count matches your design's pin-out requirements. The MAX 9000 family is supported by Altera's legacy MAX+PLUS II toolchain. This page synthesizes distributor pricing, drop-in same-package alternatives within the MAX 9000 family, and practical design notes not consolidated in the manufacturer datasheet.
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
The Intel (formerly Altera) EPM9560ARC240-10N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 560 macro cells, 191 user I/Os, and a 10 ns propagation delay, housed in a 240-pin RQFP package. It operates from a 5.0 V supply and is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which delivers predictable, deterministic interconnect timing suited to high-speed glue-logic, bus-interface, and state-machine designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell blocks with a programmable interconnect matrix. CPLDs sit between simple SPLDs (PAL/GAL) and larger FPGAs in the programmable-logic hierarchy: they offer lower density than FPGAs but provide instant-on operation, deterministic timing, and high drive strength on every pin. MAX 9000 specifically extends the MAX architecture to higher logic capacity, making it suitable for system-level integration of address decoding, interrupt controllers, and peripheral bridging on 5V-tolerant boards. Key features include 560 macro cells distributed across 16 Logic Array Blocks (LABs), 191 available user I/O pins, 10 ns pin-to-pin propagation delay (tPD), an internal frequency of 145 MHz, in-system programmability via IEEE 1149.1 JTAG, and a 5.0 V core supply. The device is electrically erasable (EEPROM-based), allowing unlimited reprogramming cycles during development and field upgrades. It supports multi-voltage I/O interfacing to 3.3 V and 5.0 V devices through its 5 V-tolerant I/O structure. The EPM9560ARC240-10N uses a non-volatile EEPROM process, which means configuration is retained without an external boot PROM and the device begins operation within microseconds of power-up. Architecture-wise, the MAX 9000 family integrates a global FastTrack interconnect that delivers consistent tPD across all paths regardless of routing complexity, removing the place-and-route iteration cycles typical of FPGAs. Each macrocell contains a programmable flip-flop, product-term array, and configurable output enable, giving designers fine-grained control over registered vs. combinatorial logic and bus-hold characteristics. Typical applications include 5V system glue logic in telecom backplanes, ISA/PCI bus address decoding, interrupt controllers, peripheral bridging between microprocessors and DSPs, and industrial control state machines. The 240-pin RQFP package also supports larger industrial 16-bit and 32-bit embedded designs that need many general-purpose I/Os and JTAG-based in-field firmware updates. Designers migrating from older bipolar PALs gain higher density while preserving deterministic 10 ns timing. When designing with this device, allow adequate decoupling (at least one 0.1 µF per VCC pin and a 10 µF bulk) directly at the package, and use the JTAG chain for production programming rather than relying on legacy Altera ByteBlaster parallel-port hardware. Note that this part is in active obsolescence planning - confirm long-term availability before committing to new designs, and consider MAX II or MAX V CPLDs for new 3.3 V designs while reserving the MAX 9000 for legacy 5 V board maintenance. This page synthesizes distributor pricing from DigiKey and Mouser, MAX 9000 family drop-in alternatives (including the -10 and -15 speed grades), and PCB layout/decoupling notes that complement the manufacturer datasheet.
EPM9560ARC304-10F - MAX 9000A CPLD 560 Macrocell | Altera
The Altera EPM9560ARC304-10F is a MAX 9000A-series Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, 216 user I/O pins, and a 10 ns maximum pin-to-pin propagation delay, housed in a 304-pin RQFP (PowerQuad II) package. It operates from a 5 V supply (4.75 V to 5.25 V) over the commercial 0 C to +70 C temperature range and is in-system programmable (ISP) via the IEEE 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC built from an array of macrocells and a programmable interconnect matrix. Unlike an FPGA, which uses fine-grained lookup-table logic and volatile SRAM configuration, a CPLD uses non-volatile EEPROM-based configuration and coarse-grained macrocells, giving deterministic, single-cycle timing and instant-on operation. In the logic IC hierarchy, the EPM9560A sits under CPLD -> programmable logic device (PLD) -> digital logic IC -> semiconductor. The MAX 9000A family extends the original MAX 9000 architecture with enhanced ISP support and improved routability. The EPM9560A provides 35 logic array blocks (LABs) and 560 macrocells, delivering enough density for bus bridging, glue logic consolidation, and state-machine implementation that would otherwise require dozens of 74-series TTL packages. Its 10 ns tPD supports system clock rates up to approximately 100 MHz for simple combinatorial paths. Key differentiators include 5 V tolerant I/O for direct interfacing with legacy TTL and CMOS logic, non-volatile configuration that retains the design without an external configuration PROM, and the 304-pin RQFP package that exposes 216 I/O for wide bus applications. The device is supported by Altera MAX+PLUS II and Quartus II development tools. Typical applications include PCI/ISA bus interface logic, telecommunications line-card glue logic, industrial control state machines, and legacy system replacement where 5 V logic levels are mandatory. The EPM9560ARC304-10F is widely used as a drop-in replacement for older MAX 9000 designs and for sustaining long-lifecycle industrial and telecom equipment. When designing with this device, note that the 5 V core draws significant static current and the 304-pin RQFP requires careful power/ground plane design. Because the part is a mature, non-volatile CPLD, it is often selected specifically to avoid the configuration-PROM overhead and boot-time delay of SRAM-based FPGAs. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sustaining this legacy MAX 9000A design.
EPM9560ARI208-10 - MAX 9000 CPLD 560 Macro Cells | Intel
The Intel (Altera) EPM9560ARI208-10 is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macro cells, 12,000 usable gates, and a 10 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad Flat Pack) package. It operates from a 5.0 V supply and delivers a maximum internal frequency of 144.9 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of an FPGA with the non-volatile, instant-on behavior of a PAL. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM technology. In the broader hierarchy, the EPM9560ARI208-10 sits within the CPLD category, which is a subset of programmable logic devices (PLDs), which in turn belong to the digital logic IC family. Unlike SRAM-based FPGAs, EEPROM CPLDs retain their configuration without an external boot device, making them ideal for glue logic, bus bridging, and power-on-critical control paths. Key features of the EPM9560ARI208-10 include 560 macro cells, 12,000 usable gates, 153 user I/O pins, and a 10 ns propagation delay (speed grade -10). The device supports 5.0 V in-system programmability (ISP) and offers 144.9 MHz internal operation, enabling high-speed address decoding and state machine implementation. Its 208-pin RQFP package provides a compact footprint for dense board designs. The MAX 9000 architecture uses a hierarchical routing structure with logic array blocks (LABs) and programmable interconnect arrays, delivering predictable timing without the place-and-route variability of FPGA fabrics. This deterministic timing is a major advantage for safety-critical and real-time control applications. Typical applications include industrial automation controllers, telecommunications line cards, test and measurement instruments, and legacy system maintenance where 5 V logic compatibility is required. The device is widely used as a bus interface and glue logic replacement for discrete 74-series logic. When designing with this CPLD, ensure the 5.0 V supply is well-decoupled with 0.1 uF ceramic capacitors on every VCC pin, and account for the 10 ns propagation delay in critical timing paths. The EEPROM configuration allows instant-on operation, eliminating the configuration load time required by SRAM FPGAs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and design decisions.
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
The Altera EPM9560ARI208-10N is a high-density, high-performance in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 12,000 usable gates, 560 macrocells, and a 208-pin RQFP (Resource QFP) plastic package. It delivers pin-to-pin propagation delay (tPD1) of 10 ns and counter frequencies up to 144.9 MHz, making it one of the fastest EEPROM-based CPLDs of its generation. The device is fabricated on an advanced 5.0 V CMOS EEPROM process that allows in-system programmability (ISP) via JTAG, eliminating the need for external programmers in production. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a global interconnect matrix, sitting hierarchically between simple SPLDs (PALs, GALs, 22V10s) and high-density FPGAs. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which integrates multiple Logic Array Blocks (LABs) of 16 macrocells each, interconnected through a programmable switch matrix. The EPM9560 has 35 LABs giving 560 macrocells total, which provides high-density glue-logic integration for system-level designs. Key features include 5.0 V single-supply operation, JTAG-based in-system programming, built-in JTAG boundary-scan (IEEE 1149.1), programmable interconnect, 212 user I/O pins, and 484 flip-flops. The 208-pin RQFP package supports industrial 0 C to 70 C operating temperature and provides ample I/O for parallel bus interfaces, memory control, and state-machine-intensive glue logic. Unlike SRAM-based FPGAs, the EEPROM cells retain configuration without external boot memory, simplifying board design. The MAX architecture uses a row-and-column interconnect structure where each LAB communicates through the Programmable Interconnect Array (PIA). This delivers predictable timing - critical for replacing discrete 22V10, PAL, and GAL devices in legacy designs - with deterministic 10 ns pin-to-pin delays and 4.5 ns clock-to-output (tCO) timing. The EEPROM process gives 100 program/erase cycles endurance and 20-year data retention. Typical applications include peripheral bus interfacing (ISA, PCI, VME), memory address decoding and control logic, state-machine-based protocol converters, glue-logic integration replacing multiple discrete PLDs, and industrial control systems requiring non-volatile reconfigurable logic. The high I/O count and 5 V tolerance make it well-suited for legacy system designs. When designing with the EPM9560, allocate sufficient decoupling (one 0.1 uF per VCC/GND pair) and follow the JTAG chain guidelines in the MAX 9000 datasheet family. The -10N suffix indicates the 10 ns speed grade with commercial 0-70 C temperature range; the 208-pin RQFP is the lower-cost plastic alternative to the 356-pin BGA version. This page synthesizes distributor pricing, drop-in alternatives, design notes, and lifecycle context for the EPM9560ARI208-10N that are not aggregated on the manufacturer datasheet.
EPM9560ARI240-10 - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560ARI240-10 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macro cells, and 191 user I/O pins, housed in a 240-pin RQFP (PowerQuad) package and rated for 10 ns pin-to-pin propagation delay at 5.0 V CMOS operation. It is an industrial-temperature-grade member of the EPM9560 family, specified for operation from -40 C to +85 C. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and a fixed interconnect matrix on a single die, allowing a designer to implement custom combinational and sequential logic without fabricating a custom ASIC. CPLDs sit between simple PLDs (PAL/GAL) and full FPGAs in the programmable logic hierarchy: they offer non-volatile configuration, deterministic timing, and low standby power, but smaller logic capacity than an FPGA. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using EEPROM-based configuration cells, so the device retains its configuration after power-down without an external configuration PROM. Key features of the EPM9560ARI240-10 include 560 macro cells organized into logic array blocks, 12,000 usable gates, 191 user I/O pins, a 144.9 MHz internal frequency, and 10 ns pin-to-pin propagation delay. The 5.0 V CMOS process provides TTL-compatible I/O levels, simplifying interface to legacy 5 V logic. EEPROM configuration gives the device instant-on operation and high immunity to single-event configuration loss compared with SRAM-based FPGAs. The MAX 9000 architecture uses a global interconnect array that routes every macro cell to every logic array block, giving predictable, data-sheet-guaranteed timing independent of placement and routing. This deterministic timing model is a major advantage for glue-logic, bus-interface, and state-machine designs where worst-case delay must be known before layout. Typical applications include legacy bus bridging (ISA, PCI, VME), address decoding and chip-select generation, custom state machines, and industrial control logic. The 240-pin RQFP package and 191 I/O count suit designs that need wide parallel buses. Because the device is a mature, EEPROM-based CPLD, it is widely used to replace obsolete discrete glue logic in long-lifecycle industrial and telecom equipment. When designing with this device, note that it is a 5.0 V core part and is not 3.3 V tolerant on all pins without level shifting; confirm the I/O standard requirements of any modern 3.3 V peripheral before direct connection. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
The Intel EPM9560ARI240-10N is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 12,000 usable gates, 560 macrocells, and 216 user I/Os in a 240-pin RQFP package. Built on Intel's (formerly Altera) third-generation Multiple Array MatriX (MAX) architecture, this device supports in-system programmability (ISP) via a 5.0V supply with a maximum internal frequency of 144.9 MHz and a propagation delay of 10 ns. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like logic blocks with a programmable interconnect matrix on a single die. The MAX 9000 family sits at the top of the MAX architecture hierarchy: macrocell -> Logic Array Block (LAB) -> Multiple Array MatriX (MAX) -> CPLD -> Programmable Logic -> Programmable Logic Device (PLD) -> Standard Logic IC. CPLDs are commonly used as glue logic, bus bridges, state machines, and interface controllers, where deterministic timing and instant-on non-volatile configuration provide advantages over SRAM-based FPGAs. Key features include 12,000 usable gates, 560 macrocells, 16 logic array blocks, 191 user-available I/Os (per Mouser), 144.9 MHz maximum internal frequency, 5.0V in-system programmability, and an operating temperature grade of -40C to +85C (industrial). The -10 speed grade corresponds to a 10 ns pin-to-pin propagation delay through the interconnect network, and the device supports the standard IEEE 1149.1 JTAG boundary-scan interface. The architecture also includes fast input and output registers, predictable interconnect delays, and JTAG-based ISP that allows board-level reconfiguration without removing the device. Typical applications include high-speed glue logic, peripheral bus bridging (e.g., PCI-to-local bus), state-machine controllers, address decoding and wait-state generation, interface translation between disparate logic families, industrial control systems, telecommunications backplane glue, and prototyping of complex digital designs where deterministic timing is required. The wide I/O count and abundant macrocells also suit large combinational and registered logic implementations that would otherwise require multiple smaller PLDs. When designing with the EPM9560ARI240-10N, observe the 5V VCCIO and VCCINT supply rails with proper decoupling, allocate sufficient ground pins, and respect the recommended I/O toggle-rate limits to minimize simultaneous switching noise (SSN). For new designs, designers should also evaluate the newer MAX V, MAX 10, or MAX II families, since the MAX 9000 series is in NRND (Not Recommended for New Designs) status. However, the EPM9560ARI240-10N remains a drop-in solution for maintaining legacy hardware where the proven MAX 9000 architecture is required. This page synthesizes distributor pricing, drop-in MAX 9000 family alternatives, and practical design notes that go beyond what is in the bare datasheet, helping engineers evaluate supply, longevity, and PCB-reuse alternatives.
EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
The Intel EPM9560ELI84-20 is a member of the Altera MAX 9000 family of high-performance CMOS EEPROM-based programmable logic devices (PLDs) with 6,000 usable gates, delivered in an 84-pin Plastic Leaded Chip Carrier (PLCC) package with -20 speed grade. It features 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that bridges the gap between traditional PAL/GAL SPLDs and larger FPGAs. The MAX 9000 family uses a third-generation Multiple Array MatriX (MAX) architecture that integrates multiple Logic Array Blocks (LABs) connected through a programmable interconnect array (PIA), offering predictable timing, deterministic pin-to-pin delays, and instant-on operation without external configuration memory. Key features include 6,000 usable gates, 560 macrocells, 16 logic array blocks, maximum 212 user I/O pins (package-dependent), 212 flip-flops, and pin-to-pin propagation delay of 20 ns. The device operates from a 5.0 V single supply, supports 5-V ISP via JTAG, and provides multiVolt I/O for interfacing to 5.0 V, 3.3 V, and 2.5 V logic levels. The MAX architecture combines EEPROM configuration cells with a fast, uniform interconnect structure. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, output enable, and feedback path. The interconnect array uses the same continuous, fast-track routing scheme found in earlier MAX families, providing deterministic timing suitable for glue-logic, bus-interface, and state-machine replacement. Typical applications include peripheral bus interfaces (PCI, ISA, VME), peripheral glue logic for microprocessors, control logic for DSPs and microcontrollers, state-machine and sequencer replacement, and 5-V industrial systems requiring non-volatile instant-on logic. The non-volatile EEPROM configuration makes the device ideal for systems where the logic must be active within microseconds of power-up without external boot memory. When designing with this device, note that the EPM9560ELI84-20 uses 5.0 V VCC and 5.0-V-tolerant I/O pins. Decoupling capacitors (one 0.1 uF and one 10 uF per supply) must be placed as close to the VCC and GND pins as possible. The JTAG pins TCK, TMS, TDI, TDO, and TRST must be terminated per IEEE 1149.1 for reliable in-system programming. This page synthesizes distributor inventory, drop-in alternatives within the MAX 9000 family, and practical design notes not found in the legacy Altera datasheet. Prices are listed as of 2026-09-13 and are subject to distributor stock and lifecycle status.
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
The Intel / Altera EPM9560GC280-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, offering 560 macro cells and 12,000 usable gates in a 280-pin Ceramic Pin Grid Array (CPGA) package. It features a maximum propagation delay of 15 ns and an internal toggle frequency of up to 117.6 MHz, with commercial-grade 0 to 70C operating temperature. The device supports 5.0V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface, eliminating the need for external programmers and enabling rapid prototyping and field upgrades. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of traditional PAL/GAL logic with high-density macro-cell arrays, residing in the product hierarchy between simple PLDs and FPGAs. CPLDs use EEPROM or flash cells for configuration retention, so they boot instantly without external boot memory - making them ideal for glue-logic, bus-interface, and power-sequencing roles. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, providing predictable timing via deterministic interconnect and fast pin-to-pin propagation. Key specifications include 560 macro cells, 12,000 typical gates, 16.6 ns pin-to-pin logic delay (per the manufacturer datasheet), 117.6 MHz maximum internal frequency, and 5.0V VCCIO operation. The CPGA280 ceramic package supports high-reliability and industrial-temperature environments, with Through-Hole mounting suitable for legacy and aerospace PCB designs. Multiple I/O standards and a JTAG-compliant boundary-scan test interface simplify board-level test, while the EEPROM-based configuration cell array provides instant-on behavior at power-up with no external boot PROM. Typical applications include high-speed bus decoding and address mapping, peripheral glue logic in microprocessor and DSP systems, power-supply sequencing controllers, industrial control logic, and legacy through-hole designs where surface-mount CPLDs are not acceptable. The 15 ns speed grade is well matched to mid-frequency control paths in networking, telecom, and test equipment. The CPGA280 package also makes this part suitable for high-reliability military and aerospace systems that require hermetic ceramic packaging. When designing with this part, note that the CPGA280 through-hole package requires plated-through-hole PCB fabrication and a socket for in-system programming convenience; surface-mount migration to a QFP equivalent is typically achieved via the EPM9560ARI240 or EPM9560ARC208 same-family parts. Ensure that the JTAG chain is properly terminated to support 5.0V ISP programming and boundary-scan testing per IEEE 1149.1. This page consolidates distributor pricing, same-family drop-in alternatives, and engineering design notes that extend the manufacturer datasheet with practical procurement and design guidance.
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
The Intel EPM9560GC280-15N is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, providing 560 macrocells, 12,000 typical usable gates, and a 16.6 ns pin-to-pin propagation delay in a 280-pin Ceramic Pin Grid Array (CPGA-280) package. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks with a programmable interconnect matrix. Compared to simple SPLDs, CPLDs deliver higher logic density, deterministic timing, and predictable propagation delays — making them ideal for glue-logic, address decoding, bus interfacing, and state-machine implementation in digital systems. Key features include a 117.6 MHz maximum clock frequency, JTAG boundary-scan test capability, 5.0-V in-system programmability, and a commercial-grade temperature rating. The MAX architecture provides predictable interconnect delays that are independent of routing, which simplifies static timing analysis and guarantees consistent performance across designs. The device is also reprogrammable, allowing iterative design changes without replacing hardware. The EPM9560GC280-15N uses electrically erasable CMOS EEPROM configuration memory, retaining its programmed logic without external configuration storage. The MAX 9000 family integrates high-density logic, predictable timing, and ISP into a single package suitable for both prototyping and volume production. Typical applications include high-density glue logic in telecommunications and networking equipment, peripheral and bus-interface controllers, address decoding in microprocessor systems, state-machine and sequencer logic, and industrial control systems. The 280-pin CPGA package supports through-hole PCB assembly commonly used in legacy telecom and industrial platforms. When designing with this CPLD, account for the 5.0-V VCC requirement; modern 3.3-V systems need a level-shifting interface. The ceramic CPGA package requires a socket or through-hole footprint, and designers should refer to Altera's MAX 9000 datasheet for I/O banking and pinout details. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes not found in the manufacturer datasheet.
EPM9560GC280-20 - MAX 9000 CPLD, 560 Macrocells, 5V, CPGA-280
The Altera (now Intel) EPM9560GC280-20 is a high-performance, high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, built on the third-generation Multiple Array MatriX (MAX) architecture. It delivers 12,000 usable gates organized into 560 macrocells and offers up to 212 user I/O pins in a 280-pin Ceramic Pin Grid Array (CPGA-280) package, with a pin-to-pin propagation delay of 20 ns (the "-20" speed grade) and counter frequencies up to 100 MHz. The device operates from a 5.0 V core supply (4.75 V to 5.25 V) and supports configurable I/O operation at 3.3 V or 5.0 V for mixed-voltage interfacing. A CPLD is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell arrays, providing deterministic timing, instant-on behavior (no configuration PROM required), and in-system programmability. Within the broader hierarchy, CPLDs sit below FPGAs in density but above simple SPLDs in logic capacity; the MAX 9000 family specifically targets high-density glue-logic, bus-interface, and state-machine applications where predictable timing and ISP via JTAG (IEEE 1149.1) are critical. Key features include 5.0 V in-system programmability through the built-in JTAG interface, pin-to-pin delays as fast as 10 ns (in faster speed grades), counter speeds up to 144 MHz, and support for both 3.3 V and 5.0 V I/O. The EEPROM-based configuration cell provides non-volatile storage, eliminating the need for an external boot PROM. The high macrocell count and wide I/O count make the EPM9560 suitable for large bus-width interfaces and complex peripheral bridging. Typical applications include telecommunications infrastructure (T1/E1 framers, line-card glue logic), industrial control (programmable state machines, peripheral bus expansion), military/aerospace systems (where CPGA packaging offers hermeticity and thermal performance), and legacy 5 V system designs requiring high-density logic integration with deterministic timing. The CPGA-280 package also supports through-hole socketed assembly, useful for prototyping and high-reliability military programs. When designing with this device, ensure adequate decoupling on all VCC pins and follow Altera's JTAG chain recommendations for in-system programming. Designers migrating to newer designs should evaluate MAX II or MAX V CPLDs for lower power, but the EPM9560 remains the preferred choice for existing 5 V systems and long-lifecycle programs where re-qualification is impractical.
EPM9560GC280-20N - 560 Macrocell MAX 9000 CPLD, 280-Pin CPGA | Altera
The Altera EPM9560GC280-20N is a high-density, 5.0-V in-system programmable CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, built on Altera's third-generation Multiple Array MatriX (MAX) architecture. The device delivers 6,000 to 12,000 usable gates and 560 macrocells with 212 user I/O lines, housed in a 280-pin Ceramic Pin Grid Array (CPGA) package, with a pin-to-pin delay of 20 ns. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a central interconnect. CPLDs sit alongside FPGAs in the programmable logic hierarchy, offering predictable timing, instant-on behavior from EEPROM storage, and high I/O count — making them preferred for glue logic, bus interfacing, and state-machine control in systems where deterministic timing matters more than raw logic density. Key features include 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, 4.75 V to 5.25 V supply operation, configurable I/O voltage at 3.3 V or 5 V, and counter speeds up to 144 MHz. The MAX architecture provides fast, predictable input-to-output combinational delays and supports PCI compliance, making the device suitable for high-performance bus-interface applications. Architecturally, the EPM9560GC280-20N integrates Logic Array Blocks (LABs), an interconnect matrix, and I/O control blocks. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, supporting D, T, JK, and SR flip-flop modes. The EEPROM configuration cell provides non-volatile storage, eliminating the need for an external boot PROM and enabling instant-on operation at power-up. Typical applications include PCI bus interfaces, high-speed glue logic between microprocessors and peripherals, bus arbitration logic, DSP control interfaces, and legacy industrial-control replacement designs. The wide I/O count and JTAG ISP support make it especially attractive for prototyping and field-upgradable systems. When designing with the EPM9560GC280-20N, ensure proper decoupling of each VCC and GND pin pair, and follow Altera's MAX 9000 application notes for JTAG chain configuration and signal-integrity layout. The 'N' suffix typically denotes an industrial temperature grade or lead-free finish — verify with the manufacturer datasheet for the specific grade of your part. This page synthesizes distributor pricing, same-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet — providing an engineering-grade reference for the EPM9560GC280-20N that goes beyond what DigiKey, Mouser, or Octopart product pages offer individually.
EPM9560GI280-15 - 560-Macrocell MAX 9000 EPLD, 280-Pin PGA | Intel
The Intel EPM9560GI280-15 is a high-performance CMOS EEPROM-based programmable logic device (PLD) from the MAX 9000 family, delivering 560 macrocells and 772 flip-flops in a 280-pin Pin Grid Array (PGA) ceramic package. It supports up to 216 user I/O pins, an internal frequency of 145 MHz, and a propagation delay of 11.4 ns (with speed grade -15), making it suitable for high-density glue-logic, bus-interface, and state-machine designs. A programmable logic device (PLD) is a general-purpose digital integrated circuit whose logic function and interconnects are defined by the end user after manufacturing. The MAX 9000 series implements a third-generation Multiple Array MatriX (MAX) architecture combining a programmable logic array with a fixed EEPROM configuration memory, allowing in-system programmability via 5.0-V tolerant ISP. Within the broader taxonomy, the EPM9560 is a Complex PLD (CPLD) positioned between small PLDs and full FPGAs, optimized for deterministic timing, fast pin-to-pin propagation, and low power at moderate logic densities. Key features include 5.0-V in-system programmability (ISP), 3.3-V or 5-V flexible I/O operation, an internal frequency up to 145 MHz, propagation delay of 11.4 ns (tPD) at the -15 speed grade, 216 user I/Os, 12 dedicated inputs, and 560 macrocells for wide combinational/sequential logic. The 280-pin PGA ceramic, metal-sealed cofired package provides industrial-grade reliability across -40°C to 85°C operation. The MAX architecture integrates a global interconnect matrix that delivers consistent, predictable timing across all 560 macrocells, which is critical when replacing multiple discrete PAL/GAL devices with a single CPLD. Each macrocell contains a programmable AND/OR array with a flip-flop, allowing implementation of state machines, counters, and registered logic without FPGA-like routing variability. Typical applications include industrial control glue logic, communications backplane interfacing, PCI bus bridging, and legacy system upgrades. Engineers typically choose the EPM9560 when deterministic timing, instant-on from EEPROM, and high I/O count are required in environments where modern FPGAs are over-spec or over-priced. When designing with the EPM9560GI280-15, ensure that the chosen socket supports 280-pin PGA with the correct pin grid pattern; verify that the Quartus / MAX+PLUS II legacy toolchain still supports the device family for new compilation flows. For new designs, evaluate MAX II or MAX V CPLDs as modern equivalents with lower power and faster compilation. This page synthesizes distributor inventory, drop-in ceramic-PGA alternatives from the MAX 9000 family, and practical design considerations not consolidated in the original datasheet, giving procurement and engineering teams a faster decision path.
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
The Intel/Altera EPM9560GI280-20 is a high-density CMOS EEPROM-based Programmable Logic Device (PLD) from the MAX 9000 device family, delivering 560 macrocells, 216 I/O lines, and 772 flip-flops in a 280-pin Pin Grid Array (PGA) package. The "-20" speed grade denotes a 20 ns pin-to-pin delay, and the "GI" package code identifies the ceramic PGA industrial-temperature variant. A Programmable Logic Device (PLD) is a general-purpose digital integrated circuit whose internal logic and interconnect are defined by the user after manufacturing, allowing one silicon device to implement a wide range of glue logic, state machines, bus interfaces, and datapath controllers. The MAX 9000 family is built on a third-generation Multiple Array MatriX (MAX) architecture that combines fine-grained Logic Array Blocks (LABs) with an EEPROM programming technology, providing non-volatile configuration that retains state across power cycles without an external boot PROM. Key features of the EPM9560GI280-20 include 12,000 usable gates, 560 macrocells, 216 user I/O pins, 772 flip-flops, an in-system programmability (ISP) interface compliant with IEEE Std. 1149.1 (JTAG), and a 5.0 V VCC core supply. The device is supported by the Altera MAX+PLUS II development system, which offers schematic, VHDL, Verilog HDL, and AHDL design entry together with synthesis, simulation, timing analysis, and device programming. The MAX 9000 architecture arranges 560 macrocells into 28 LABs of 16 macrocells each, with a continuous FastTrack interconnect running across the chip. Each macrocell contains a programmable-AND/fixed-OR array, an XOR gate for polarity control, a programmable register with clock, clock-enable, clear, and preset controls, and an I/O architecture that supports input, output, output-enable, and bidirectional operation. The result is a flexible platform suitable for high-density glue logic, register-intensive datapaths, and bus-interface bridging. Typical applications include telecom and datacom line-card glue logic, industrial control and factory automation controllers, military and aerospace avionics, legacy bus-interface bridging, and high-density state-machine replacement of discrete 74LS/74F logic. The non-volatile EEPROM cell array makes it well suited to applications that must boot into a defined state without external configuration memory. When designing with this device, ensure that the 5.0 V VCC supply rises monotonically and that I/O pin overshoot/undershoot is limited to the datasheet's transient envelope (overshoot to 7.0 V and undershoot to -2.0 V for periods under 20 ns under no-load conditions). Designers should also verify timing closure against the 20 ns speed grade using MAX+PLUS II timing analysis. This page synthesizes distributor availability, parametric context, and drop-in alternative options for the EPM9560GI280-20 that are not consolidated in the original MAX 9000 datasheet.
EPM9560GM280-15 - 560 Macrocells MAX 9000 PLD 5V | Altera
The Altera EPM9560GM280-15 is a high-density CMOS EEPROM-based Programmable Logic Device (PLD) from the MAX 9000 family, providing 560 macrocells, 772 flip-flops, and 216 user I/O pins in a 280-ball FineLine BGA (GM) package. It operates from a nominal 5.0V supply with an absolute maximum of 5.5V and supports 3.3V or 5V I/O operation for mixed-voltage system interfacing. Background: A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the end user rather than the device manufacturer. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which combines the high density of FPGAs with the non-volatility of EEPROM storage. Within the broader taxonomy, PLDs sit under programmable logic, alongside FPGAs and CPLDs, and are used to implement glue logic, bus interfacing, and state machines without the cost of an ASIC. The 'EE' prefix indicates electrically erasable (EEPROM-based) configuration, enabling in-system programmability (ISP) via the IEEE Std 1149.1 JTAG interface. Key features include 560 macrocells, 216 programmable I/O pins, 5V in-system programmability through JTAG, and a 15ns pin-to-pin propagation delay (the '-15' speed grade). The device is implemented in 0.35 µm CMOS EEPROM technology, retains its configuration without external memory, and supports MultiVolt I/O for seamless interfacing between 5V and 3.3V logic domains. Boundary-scan testability is provided through full JTAG (IEEE 1149.1) compliance. Architecturally, the MAX 9560 organises logic into Logic Array Blocks (LABs) of 16 macrocells each, interconnected by a programmable interconnect array. Each macrocell contains a programmable AND/OR array, a configurable flip-flop, and product-term allocation logic. The EEPROM cell stores configuration, eliminating the need for a separate boot PROM at power-up. This combination of high logic density, deterministic timing, and non-volatile storage made the MAX 9560 popular for prototyping and low-volume glue-logic replacement. Typical applications include telecommunications line cards, industrial control glue logic, bus-interface bridges (PCI, ISA, VME), and high-density state machines. The wide 216-I/O count and JTAG-based ISP made the GM280 package particularly suitable for space-constrained designs requiring live in-field reconfiguration. When designing with this device, observe the 5.5V absolute maximum supply rating and ensure JTAG chain integrity for ISP. For new designs, consider the MAX II or MAX V family as a lower-power, lower-cost modern alternative; for legacy boards, ensure firmware and Quartus support files are archived. This page synthesises distributor stock, drop-in package alternatives from the MAX 9000 family, and design notes that go beyond the manufacturer datasheet, including power estimation and JTAG programming guidance.
EPM9560R1208-20 - MAX 9000 CPLD 6k Gates 1208-pin | Altera
The Altera EPM9560R1208-20 is a member of the MAX 9000 family of high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on Altera's third-generation Multiple Array MatriX (MAX) architecture. The device provides 6,000 usable gates, a 20 ns propagation delay grade, and is housed in a 1208-pin R-package (R-prefix, ball-grid array) suitable for surface-mount assembly. It supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, eliminating the need for a separate programmer. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that integrates multiple PAL/GAL-style logic blocks with a programmable interconnect matrix. CPLDs sit between discrete logic ICs (74-series glue logic) and FPGAs in the programmable-logic hierarchy, providing deterministic timing, predictable I/O behavior, and instant power-on logic without external boot memory. The MAX 9000 family is widely used for decoder, counter, state-machine, bus-interface, and glue-logic applications where deterministic pin-to-pin timing is more important than raw gate count. Key features of the EPM9560R1208-20 include 560 macrocells, a maximum operating frequency of 125 MHz, 212 user I/O pins, a tPD of 20 ns, and an industrial 0C to +70C operating temperature range. The device includes a JTAG-compliant boundary-scan test interface, four dedicated input pins, global clock networks, and open-drain or programmable output structures. Power consumption is typically 200 mA at 5.0 V VCC, with low-power standby modes for battery-backed applications. Architecturally, the MAX 9000 family uses a Logic Array Block (LAB) structure composed of 16 macrocells each, interconnected by a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR/flip-flop chain, allowing implementation of sum-of-products combinatorial or registered sequential logic in a single device. The on-chip EEPROM cells retain configuration permanently without external memory. Typical applications for the EPM9560R1208-20 include bus-interface bridging, address decoding, FIFO control, glue logic for microprocessor systems, peripheral interface adaptation, and high-density state-machine replacement. The 1208-ball package is suitable for high-I/O-count designs where many signal pins must be brought off-chip simultaneously. Compared to FPGAs in the same era, MAX 9000 devices offer instant-on behavior and deterministic timing ideal for control-path logic. When designing with the EPM9560R1208-20, ensure that the 5.0 V supply is well decoupled with 0.1 uF and 10 uF capacitors placed close to the VCC pins. Use the JTAG pins (TCK, TMS, TDI, TDO, and TRST) for in-system programming and boundary-scan test, and follow Altera's recommended PCB layout for fine-pitch BGA packages to maintain signal integrity at high toggle rates. This page synthesizes distributor stock, Altera MAX 9000 family datasheet extracts, and drop-in compatible CPLD variants from the EPM9560 series - practical sourcing and engineering data not consolidated on any single manufacturer or distributor page.
EPM9560RC-10 - MAX 9000 CPLD, 560 Macrocells, 240-pin PGA | Intel
The Intel (formerly Altera) EPM9560RC-10 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 560 macrocells, approximately 12,000 usable gates, and a 10 ns pin-to-pin propagation delay. It is housed in a 240-pin ceramic Pin Grid Array (PGA) package designated by the 'RC' suffix and operates over the commercial 0C to +70C temperature range. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells on a single chip, providing deterministic timing and instant-on behavior. Within the broader programmable logic hierarchy, the MAX 9000 series sits between classic PLDs (PAL/GAL) and FPGAs, offering glue-logic integration, bus decoding, state-machine encoding, and peripheral interface bridging. It is part of the wider semiconductor category of programmable logic ICs, which includes CPLDs, FPGAs, and SPLDs. Key features of the EPM9560RC-10 include 16 Logic Array Blocks (LABs) interconnected by the third-generation Multiple Array Matrix (MAX) programmable interconnect, 212 user I/O pins, 5.0 V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, and built-in boundary-scan test support. The architecture supports each macrocell with up to 32 product terms and a programmable register, enabling efficient implementation of wide combinational and registered logic functions. Typical applications include high-performance bus-interface bridging, processor glue logic, peripheral controllers, and state-machine implementation in telecommunications, industrial automation, and military/aerospace systems. The 240-pin PGA package also makes the EPM9560RC-10 a strong fit for prototyping and through-hole industrial backplane designs where socketed replacement is preferred over surface-mount rework. When designing with this device, observe the maximum I/O current ratings and provide proper decoupling on every VCCINT and VCCIO pin pair. The device is non-volatile, so configuration is loaded at power-up with zero boot latency, which simplifies board-level power sequencing compared with SRAM-based FPGAs.