10AS032H2F35E1HG - Arria 10 SX 320K LE SoC FPGA | Intel | 1152-FBGA
MPN: 10AS032H2F35E1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2085.14 | $2,085.14 |
| 10 | $1876.63 | $18,766.30 |
| 100 | $1668.12 | $166,812.00 |
| 500 | $1463.1 | $731,550.00 |
| 1,000 | $1293 | $1,293,000.00 |
Drop-in alternatives for 10AS032H2F35E1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS032H2F35I1HG
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View Datasheet →10AS032H2F35E1HG Maximum Ratings & Electrical Characteristics
| Device Family | Arria 10 SX SoC FPGA |
| Product Type | System-on-Chip (SoC) FPGA |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 320,000 |
| User I/Os | 384 |
| Package | 1152-ball FCBGA (35 x 35 mm) |
| Operating Temperature Grade | Industrial (E1) |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| Configuration | Serial (E1 suffix) |
| Hard Processor System | HPS with Cortex-A9 dual core, L1/L2 cache, peripherals |
10AS032H2F35E1HG 1152-ball fcbga (35 x 35 mm) Pin Configuration Guide
Complete pinout information for 10AS032H2F35E1HG (1152-ball fcbga (35 x 35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS032H2F35E1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H2F35E1HG is suitable for 6 applications: Industrial Machine Vision Systems, Software-Defined Radio (SDR) Platforms, Test and Measurement Equipment, Medical Imaging (Ultrasound / CT Front-End), Broadcast Video Processing, Industrial Motor Control and Drives.
Industrial Machine Vision Systems
The 10AS032H2F35E1HG is well-suited to industrial machine vision platforms where the dual ARM Cortex-A9 HPS runs Linux for vision stack orchestration (OpenCV, GStreamer) while the FPGA fabric implements real-time image processing pipelines at line rate. The 320K logic elements handle Bayer demosaic, color correction, and edge detection at full Camera Link or CoaXPress bandwidth without dropping frames. The 1.5 GHz transceiver rate supports CoaXPress 2.0 and 10 GigE Vision uplinks for multi-camera inspection lines, while 384 user I/Os accommodate parallel sensor interfaces, lighting triggers, and encoder feedback. Industrial temperature screening (E1) allows deployment in factory-floor enclosures without additional thermal margin, and the 1152-ball FCBGA package consolidates all high-speed serial, memory, and HPS I/O on a single footprint.
Recommended
Software-Defined Radio (SDR) Platforms
The 10AS032H2F35E1HG's 1.5 GHz transceiver rate and 20 high-speed serial channels make it a strong fit for wideband SDR baseband processing in defense, public-safety, and 5G test equipment. The FPGA fabric implements DDC/DUC, FFT, and channelizer logic in variable-precision DSP blocks at rates exceeding 200 MHz, while the dual Cortex-A9 HPS handles the GNU Radio / UHD host stack, network I/O, and operator GUI. The 384 user I/Os interface to RF front-end daughter cards via FMC+ HPC connectors, and the 1152-ball FCBGA package supports the dense power and ground distribution required for sustained fabric utilization. Industrial temperature screening enables deployment in outdoor or vehicle-mounted SDR enclosures.
Recommended
Test and Measurement Equipment
The 10AS032H2F35E1HG suits high-end oscilloscope, protocol analyzer, and bit-error-rate tester designs where deterministic FPGA latency and HPS-side user interface combine in a single device. The 320K LE fabric implements real-time protocol decoding (PCIe Gen3, USB 3.1, SATA) and trigger logic, while the dual ARM Cortex-A9 HPS runs a touch-screen UI, network services, and acquisition scripting. The 1.5 GHz transceivers accept high-speed serial test inputs directly, eliminating external muxing. The 384 user I/Os connect to front-panel probe interfaces, GPIO, and display peripherals. Industrial temperature screening (E1) supports benchtop and portable instrument form factors.
Recommended
Medical Imaging (Ultrasound / CT Front-End)
The 10AS032H2F35E1HG serves as the central processing device in mid-range ultrasound and CT front-end systems where the dual Cortex-A9 HPS manages the patient-interface GUI and DICOM network stack, while the FPGA fabric performs beamforming, envelope detection, and image reconstruction at real-time rates. The 320K logic elements support 64-128 channel beamformers with sample rates up to 40 MHz per channel, and the 1.5 GHz transceivers aggregate digitized RF data from front-end ADCs over high-speed serial links (JESD204B/C). The 384 user I/Os connect to transducer arrays, operator controls, and medical-grade displays. The industrial temperature grade supports hospital-room ambient conditions.
Recommended
Broadcast Video Processing
The 10AS032H2F35E1HG handles broadcast video routing, format conversion, and overlay processing in studio and outside-broadcast equipment. The FPGA fabric implements SDI de-embed/embed, color space conversion, frame-rate conversion, and logo insertion at 12G-SDI rates, while the dual Cortex-A9 HPS manages SNMP, control plane, and redundancy switching. The 1.5 GHz transceivers accept 12G-SDI, SMPTE 2110, and quad-link 3G-SDI inputs without external muxes, and the 384 user I/Os interface to GPIO for tally, intercom, and ancillary data. Industrial temperature screening supports 24/7 studio rack environments.
Recommended
Industrial Motor Control and Drives
The 10AS032H2F35E1HG integrates the deterministic FPGA fabric and Cortex-A9 HPS needed for high-end industrial servo drives and CNC controllers. The FPGA fabric runs field-oriented control (FOC) loops for multi-axis motor control at sub-microsecond PWM update rates, while the dual Cortex-A9 HPS executes motion planning, EtherCAT/Profinet slave stacks, and HMI logic. The 384 user I/Os accommodate encoder feedback (EnDat, BiSS, SSI), resolver inputs, PWM outputs, and fieldbus connectivity. The 1.5 GHz transceivers support EtherCAT gigabit and Profinet IRT. The 1152-ball FCBGA package and industrial temperature grade suit industrial cabinet deployment.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H2F35E1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H2F35I1HG | 10AS032H1F35E1HG | 10AS032H2F34I2SG | 10AS032H2F34E2SG |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (35x35 mm) | 1152-ball FCBGA (35x35 mm) - same | 1152-ball FCBGA (35x35 mm) - same | 1152-ball FCBGA (35x35 mm) - same | 1152-ball FCBGA (35x35 mm) - same |
| Logic Elements | 320,000 | 320,000 | 320,000 | 320,000 | 320,000 |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Transceiver Channels | 20 | 20 | 20 | 18 (F34) | 18 (F34) |
| Max Transceiver Data Rate | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Temperature Grade | Industrial (E1) | Industrial Extended (I1) | Industrial (E1) | Industrial Extended (I2) | Industrial (E2) |
| Power Tier | H2 (10W typical) | H2 (10W typical) | H1 (8W typical) - lower | H2 (10W typical) | H2 (10W typical) |
| User I/Os | 384 | 384 | 384 | 384 | 384 |
Key Differentiators
- Industrial temperature grade for factory-floor deployment (vs 10AS032H2F35I1HG)
- 20 transceiver channels at 1.5 GHz for high-bandwidth serial I/O (vs 10AS032H2F34E2SG)
- Standard 10W H2 power tier versus lower-power H1 variant (vs 10AS032H1F35E1HG)
Design Notes
The 1152-ball FCBGA package dissipates 10-25 W depending on logic utilization and transceiver activity. Attach a heatsink with thermal interface material (TIM) rated for at least 0.5 C/W junction-to-ambient, and provide a forced-air airflow of 200 LFM minimum for industrial ambient up to +85C. Monitor the on-chip temperature diode via the Arria 10 TempSense IP and implement thermal throttling in FPGA firmware if junction temperature exceeds 100C.
Allocate at least 12 PCB layers for the 10AS032H2F35E1HG design to break out all 1152 BGA balls. Use 100-ohm differential routing for all 20 transceiver channels with skew matching within 5 ps, and follow Intel's Arria 10 High-Speed Serial Interface PCB Design Guidelines for via structure and length matching. The DDR3/4 external memory interface requires strict fly-by topology with length-matched address/command traces.
Series-couple each transceiver channel with 0.1 uF AC-coupling capacitors rated for the line-rate frequency band, and route transceiver power (XCVR_VCC, XCVR_VCCR) from a dedicated LDO with output noise below 10 mVrms. Isolate HPS clocks from FPGA fabric clocks with separate clock buffers to prevent jitter coupling into DDR interfaces.
Do not assume the 10AS032E4F29E3LG (Arria 10 GX, no HPS, 780-ball 29x29 mm FBGA) is drop-in compatible with the 10AS032H2F35E1HG - they differ in HPS presence, package, and I/O count, requiring PCB redesign. Always verify the suffix code (H2 vs H1 vs E4, F35 vs F34, E1 vs E2 vs I1) against the Arria 10 ordering information PDF before substitution.
Compliance Information
RoHS and lead-free compliance per Intel Arria 10 product family declarations. AEC-Q100 not applicable - this is a high-end industrial/embedded SoC FPGA, not an automotive-grade IC. Verify conflict-minerals status via Intel's latest CMRT/CMCo filings.
