10AS057K1F35E1HG - Arria 10 SX SoC FPGA 570K LE | Intel
MPN: 10AS057K1F35E1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1725 | $17,250.00 |
| 100 | $1580 | $158,000.00 |
| 500 | $1410 | $705,000.00 |
| 1,000 | $1280 | $1,280,000.00 |
Drop-in alternatives for 10AS057K1F35E1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35E1HG
✅ Drop-In✓ In Stock
$1995 / Unit
View Datasheet →10AS057K1F35E1SG
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10AS057K3F35E1HG
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10AS048K1F35E1HG
✅ Drop-In✓ In Stock
$3850 / Unit
View Datasheet →10AS066K1F35E1HG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
Contact for price
View Datasheet →10AS057H1F35E1HG
✅ Drop-In📋 Reference alternative (not in catalog)
10AS057K1F35E1HG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Device Variant | 10AS057 |
| Logic Elements | 570,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Processor Frequency | 1.5 GHz |
| Package | 1152-ball FC-BGA (35x35 mm) |
| Speed Grade | -1 (F35) |
| Temperature Grade | Extended (E) |
| Transceivers | Up to 24 channels |
| Maximum Transceiver Data Rate | 17.4 Gbps |
| Memory Interfaces | DDR4 / DDR3 with hard controllers |
| HPS Peripherals | USB 2.0, Gigabit Ethernet, UART, SPI, I2C, SD/eMMC |
| Process Node | 20 nm |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS057K1F35E1HG 1152-ball fc-bga (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS057K1F35E1HG (1152-ball fc-bga (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K1F35E1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K1F35E1HG is suitable for 6 applications: Software-Defined Radio (SDR) Baseband, Radar and Electronic Warfare Front Ends, Industrial Machine Vision and Inference, Medical Imaging Accelerators, High-Speed Data Acquisition and Instrumentation, Motor Control and Industrial Drives.
Software-Defined Radio (SDR) Baseband
The 10AS057K1F35E1HG is well suited to software-defined radio baseband processing where ARM Cortex-A9 handles the Linux/RTOS control plane, run-time waveform configuration, and Ethernet management, while the FPGA fabric executes parallel FFT/fir/decimator pipelines in dedicated DSP blocks. With up to 17.4 Gbps transceivers, the device can directly interface CPRI, JESD204B, and 10 GbE to ADC/DAC front ends without external PHY glue, reducing BOM count. The HPS-FPGA bridge allows low-latency shared memory between HPS and FPGA for sample streaming, a key advantage for cognitive-radio scenarios requiring sub-millisecond reconfiguration.
Recommended
Radar and Electronic Warfare Front Ends
For radar and electronic-warfare systems, the 10AS057K1F35E1HG combines 570K logic elements and 384 DSP blocks (per Arria 10 family data) to implement pulse compression, MTI filtering, and direction-finding algorithms in real time. The dual ARM Cortex-A9 MPCore runs the system health monitor, calibration tables, and target tracking classifier, offloading those tasks from the FPGA fabric for higher data throughput. Hard DDR4 controllers with ECC make the device suitable for long coherent-integration buffers required by modern SAR and AESA radar modes. The 20 nm process and extended temperature grade support deployment in airborne, shipboard, and ground-mobile platforms.
Recommended
Industrial Machine Vision and Inference
The 10AS057K1F35E1HG is well matched to high-end industrial machine vision where the FPGA fabric accelerates convolutional neural network inference or ISP pipelines, while the ARM Cortex-A9 subsystem runs the application layer, the PLC/Modbus interface, and the HMI. The HPS-FPGA shared memory bridge lets a Linux-side process post images to the FPGA and receive classification results with sub-frame latency, simplifying software architecture. The 1.5 GHz Cortex-A9 plus NEON engine can also run a fallback CPU-only inference path for low-power idle states. The 1152-ball FC-BGA provides enough I/O for 4-8 camera link or CoaXPress channels when paired with external PHYs.
Recommended
Medical Imaging Accelerators
Medical imaging systems such as ultrasound, CT, and MRI reconstruction accelerators use the 10AS057K1F35E1HG to process raw ADC data into displayable images. The 570K logic elements support a complete beamformer plus image-processing chain for cart-based ultrasound, while the dual ARM Cortex-A9 runs the user interface, DICOM stack, and patient database. Hard floating-point DSP blocks accelerate back-projection and compressed-sensing reconstruction on CT scanners, and the 17.4 Gbps transceivers stream raw data from the analog front end without bottlenecks. The 20 nm Arria 10 long-lifecycle commitment is a key advantage for FDA-cleared medical devices.
Recommended
High-Speed Data Acquisition and Instrumentation
The 10AS057K1F35E1HG is ideal for multi-channel data-acquisition and instrumentation platforms where the FPGA fabric aggregates ADC samples at rates of 5-10 GSPS per channel, performs real-time FFT, triggering, and decimation, and forwards qualified data to the ARM subsystem for storage, display, and protocol conversion. Up to 24 transceivers at 17.4 Gbps provide ample connectivity to high-end JESD204B ADCs and to host systems via 10 GbE or PCIe Gen3. The hard DDR4 controller with ECC supports deep capture memory for transient-recording applications. The extended temperature grade is suitable for outdoor and industrial test environments.
Recommended
Motor Control and Industrial Drives
The 10AS057K1F35E1HG fits high-end industrial motor control and servo-drive platforms where the ARM Cortex-A9 runs the safety PLC, EtherCAT/EtherNetIP master, and motion controller, while the FPGA fabric executes deterministic PWM generation, encoder interface, and field-oriented-control loops at sub-microsecond cycle times. The dual-core HPS plus the HPS-FPGA bridge allow Linux-side non-real-time tasks to coexist with hard-real-time FPGA logic on a single chip, eliminating the need for a separate MCU. The 1.5 GHz ARM provides ample processing for the kinematics, vibration analysis, and predictive maintenance algorithms common in modern servo drives.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K1F35E1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35E1HG | 10AS057K1F35E1SG | 10AS057K3F35E1HG | 10AS048K1F35E1HG | 10AS066K1F35E1HG | 10AS057H1F35E1HG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FC-BGA (35x35 mm) | 1152-ball FC-BGA (35x35 mm) - same | 1152-ball FC-BGA (35x35 mm) - same | 1152-ball FC-BGA (35x35 mm) - same | 1152-ball FC-BGA (35x35 mm) - same | 1152-ball FC-BGA (35x35 mm) - same | 1152-ball FC-BGA (35x35 mm) - same |
| Family | Arria 10 SX SoC | Arria 10 SX SoC | Arria 10 SX SoC | Arria 10 SX SoC | Arria 10 SX SoC | Arria 10 SX SoC | Arria 10 SX SoC |
| Logic Elements | 570,000 | 570,000 | 570,000 | 570,000 | 480,000 (-16%) | 660,000 (+16%) | 570,000 |
| Speed Grade | -1 | -2 | -1 | -3 | -1 | -1 | -1 |
| Temperature Grade | Extended (E) | Extended (E) | Industrial (I) | Extended (E) | Extended (E) | Extended (E) | Extended (E) |
| Hard Processor System | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz |
| Transceiver Rate (max) | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
| Drop-in Compatible | Yes (reference) | Yes - speed grade change only | Yes - temperature grade change only | Yes - speed grade change only | Yes if design fits 480K LE (-16%) | Yes if design scales to 660K LE (+16%) | Yes - same bin label, H vs K letter |
Key Differentiators
- Highest mid-density Arria 10 SX SoC with 17.4 Gbps transceivers in F35 BGA (vs 10AS048K1F35E1HG (480K LE))
- Identical 1152-ball F35 BGA pin/ball map vs 10AS066 (660K LE) and 10AS048 (480K LE) (vs Xilinx Zynq-7000 XC7Z045)
- 20 nm process with 1.5 GHz ARM Cortex-A9 and DDR4 hard controller (vs 10AS057K2F35E1HG (-2 speed grade))
Design Notes
The 10AS057K1F35E1HG requires multiple independent supply rails (VCC, VCCP, VCCPT, VCCERAM, VCCBAT, VCCA_PLL, transceiver supplies, and HPS supplies) with strict power-up and power-down sequencing. Follow the Arria 10 pin connection guidelines to implement the POR and sequencing circuit, and route analog PLL supplies through a ferrite bead plus a low-noise LDO. Estimated: total in-rush current on a fully populated design can exceed 4 A on the 0.95 V core rail - size the Power Management IC (such as LTM4677 or ISL68201) for transient response, not just steady-state current.
Although the 1152-ball FC-BGA has a moderate junction-to-ambient thermal resistance, the 20 nm Arria 10 SX SoC dissipates 15-25 W in typical SoC workloads, and high transceiver utilization can push this above 30 W. Use a high-Tg multilayer PCB with at least 12 thermal vias in the BGA center array connecting to a solid inner-plane copper pour. For chassis-mounted industrial applications, an aluminum heat spreader or low-profile heatsink is recommended. Estimated: at 25 C ambient with no airflow, theta-JA of 4-6 C/W for a 35x35 FC-BGA gives a 100-150 C junction rise at 20 W dissipation - airflow is usually required.
The 1152-ball FC-BGA uses a 1.0 mm ball pitch with a 35x35 mm body, requiring at least an 8-layer PCB with 0.4-0.5 mm laser-drilled microvias and 1 oz copper. Escape routing for the 24 transceivers demands continuous reference-plane stack-up for the upper layers; never route a high-speed serial lane across a plane split. Use the Intel Arria 10 PCB design guidelines (formerly AN 528) to validate the stack-up, and follow the length-matching tables for the DDR4 interface, which can require 25-50 mil total length matching across byte groups.
Common pitfalls on 10AS057K1F35E1HG designs include: (1) omitting the configuration device (EPCQ-L or compatible) - the SoC HPS does not auto-load the FPGA bitstream; (2) forgetting the HPS cold-reset and warm-reset circuit - the HPS boot ROM requires proper reset timing; (3) not populating the JTAG header for both HPS and FPGA chains - the HPS debug access port (DAP) is a separate TAP; (4) ignoring the VREFP_ADC and VREFN_ADC pins, which must be tied to analog ground for unused HPS ADC inputs. Each of these has caused field failures in early Arria 10 SX designs.
Place the 10AS057K1F35E1HG centrally on the board to minimize DDR4 trace length and to keep transceiver lanes short and balanced. Decoupling capacitors (100 nF and 4.7 uF) must be placed within 100 mil of the relevant supply balls, with vias in the BGA escape array. Route HPS Ethernet and USB differential pairs with 90 ohm differential impedance and 2-3 W spacing rules; route transceivers per the Intel LVDS and Transceiver layout guidelines. Estimated: a 6-layer PCB with 1-oz copper and 0.2 mm dielectric can support DDR4-2400 to the HPS at 1.5 GHz.
Compliance Information
RoHS and REACH compliance per Intel/Altera product page. The 10AS057K1F35E1HG is not AEC-Q100 qualified; this is an industrial-grade SoC FPGA not intended for automotive safety applications.
