EP1810LI-35 - 35ns Classic EPLD, 48 Macrocells, PLCC-68 | Altera
MPN: EP1810LI-35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $130.08 | $130.08 |
| 10 | $117.07 | $1,170.70 |
| 100 | $104.06 | $10,406.00 |
| 500 | $91.06 | $45,530.00 |
| 1,000 | $78.05 | $78,050.00 |
Drop-in alternatives for EP1810LI-35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LI-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810LC-35
β Drop-Inβ In Stock
$49.2 / Unit
View Datasheet βEP1810LC-45
β Drop-Inβ In Stock
$49.9 / Unit
View Datasheet βEP1810LC-25
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810JC-35
β Drop-Inβ In Stock
$5.48 / Unit
View Datasheet βEP1810JI-35
β Drop-Inβ In Stock
$18.6 / Unit
View Datasheet βEP1810LI-35 Maximum Ratings & Electrical Characteristics
| Manufacturer | Rochester Electronics, LLC (original Altera design) |
| Part Family | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 48 |
| Propagation Delay (tPD) | 35 ns |
| Speed Grade | 35 (slowest in EP1810L family) |
| Package | 68-pin PLCC (J-Lead, plastic) |
| Pin/Package Code | PLCC-68 / PQCC68 |
| Technology | CMOS, UV-erasable EPROM configuration cell |
| Supply Voltage | 5 V (TTL-compatible I/O) |
| Operating Temperature | -40 C to +85 C (industrial, 'I' suffix) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | IEEE 1149.1 compliant |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
EP1810LI-35 Pin Configuration
| Pin 1 | I/O β Macrocell I/O pin (input or bidirectional) |
| Pin 2 | I/O β Macrocell I/O pin |
| Pin 3 | I/O β Macrocell I/O pin |
| Pin 4 | I/O β Macrocell I/O pin |
| Pin 5 | I/O β Macrocell I/O pin |
| Pin 6 | I/O β Macrocell I/O pin |
| Pin 7 | I/O β Macrocell I/O pin |
| Pin 8 | I/O β Macrocell I/O pin |
| Pin 9 | I/O β Macrocell I/O pin |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Macrocell I/O pin |
| Pin 12 | I/O β Macrocell I/O pin |
| Pin 13 | I/O β Macrocell I/O pin |
| Pin 14 | I/O β Macrocell I/O pin |
| Pin 15 | I/O β Macrocell I/O pin |
| Pin 16 | I/O β Macrocell I/O pin |
| Pin 17 | I/O β Macrocell I/O pin |
| Pin 18 | I/O β Macrocell I/O pin |
| Pin 19 | I/O β Macrocell I/O pin |
| Pin 20 | I/O β Macrocell I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β Macrocell I/O pin |
| Pin 23 | I/O β Macrocell I/O pin |
| Pin 24 | I/O β Macrocell I/O pin |
| Pin 25 | I/O β Macrocell I/O pin |
| Pin 26 | I/O β Macrocell I/O pin |
| Pin 27 | I/O β Macrocell I/O pin |
| Pin 28 | I/O β Macrocell I/O pin |
| Pin 29 | INPUT β Dedicated input pin |
| Pin 30 | INPUT β Dedicated input pin |
| Pin 31 | GND β Ground |
| Pin 32 | INPUT β Dedicated input pin |
| Pin 33 | INPUT β Dedicated input pin |
| Pin 34 | INPUT β Dedicated input pin |
| Pin 35 | INPUT β Dedicated input pin |
| Pin 36 | INPUT β Dedicated input pin |
| Pin 37 | INPUT β Dedicated input pin |
| Pin 38 | INPUT β Dedicated input pin |
| Pin 39 | INPUT β Dedicated input pin |
| Pin 40 | GND β Ground |
| Pin 41 | INPUT β Dedicated input pin |
| Pin 42 | INPUT β Dedicated input pin |
| Pin 43 | INPUT β Dedicated input pin |
| Pin 44 | INPUT β Dedicated input pin |
| Pin 45 | INPUT β Dedicated input pin |
| Pin 46 | INPUT β Dedicated input pin |
| Pin 47 | INPUT β Dedicated input pin |
| Pin 48 | TMS β JTAG Test Mode Select |
| Pin 49 | TCK β JTAG Test Clock |
| Pin 50 | TDO β JTAG Test Data Out |
| Pin 51 | TDI β JTAG Test Data In |
| Pin 52 | VCC β +5 V supply |
| Pin 53 | I/O β Macrocell I/O pin |
| Pin 54 | I/O β Macrocell I/O pin |
| Pin 55 | I/O β Macrocell I/O pin |
| Pin 56 | I/O β Macrocell I/O pin |
| Pin 57 | I/O β Macrocell I/O pin |
| Pin 58 | I/O β Macrocell I/O pin |
| Pin 59 | I/O β Macrocell I/O pin |
| Pin 60 | VCC β +5 V supply |
| Pin 61 | I/O β Macrocell I/O pin |
| Pin 62 | I/O β Macrocell I/O pin |
| Pin 63 | I/O β Macrocell I/O pin |
| Pin 64 | I/O β Macrocell I/O pin |
| Pin 65 | I/O β Macrocell I/O pin |
| Pin 66 | I/O β Macrocell I/O pin |
| Pin 67 | I/O β Macrocell I/O pin |
| Pin 68 | I/O β Macrocell I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LI-35 is suitable for 6 applications: Microprocessor Address Decoding, TTL Glue Logic Consolidation, Industrial Control State Machines, Legacy Peripheral Bus Interface, Data Acquisition Front-End Control, Avionics & Defense Legacy Systems.
Microprocessor Address Decoding
The EP1810LI-35 is widely used as a 5 V address decoder for 16-bit and 32-bit microprocessor and DSP systems where it replaces multiple 74LS138/74LS139 decoder ICs with a single non-volatile PLD. Its 48 macrocells provide enough AND-OR logic to implement full address-space decoding with chip-select gating for memory banks, peripheral controllers, and boot ROM, while the 35 ns tPD adds at most one wait state on legacy 8-25 MHz bus cycles. Place the EP1810LI-35 between the CPU address bus and the peripheral CS pins, power it from the same 5 V rail as the CPU, and add 0.1 uF decoupling on every VCC pin to suppress switching noise. The advantage over a discrete decoder tree is single-chip integration, instant-on configuration, and the ability to redesign decode maps without board rework.
Recommended
TTL Glue Logic Consolidation
Engineers replace boards stuffed with dozens of 74LS00 / 74LS04 / 74LS138 / 74LS151 / 74LS374 packages by integrating the equivalent logic into a single EP1810LI-35. Each macrocell implements one combinational or registered function, so 48 macrocells typically absorb 15-30 SSI/MSI packages and free substantial board area for other functions. The 5 V TTL-compatible I/O and industrial -40 C to +85 C operating range match legacy through-hole and surface-mount TTL designs one-for-one. Insert the EPLD with a PLCC-68 socket so it can be reprogrammed or replaced; add a 0.1 uF ceramic on each VCC pin and a 10 uF bulk cap near the power pins. Compared to discrete TTL, the EP1810LI-35 cuts power, board area, and assembly cost while preserving the deterministic timing engineers expect from classic logic.
Recommended
Industrial Control State Machines
The EP1810LI-35's 48 macrocells, JTAG boundary-scan, and non-volatile EPROM cells make it a workhorse for implementing deterministic Moore/Mealy state machines in PLCs, motor controllers, and process-control front ends. Designers can encode 8-16 state controllers with combinational outputs in a single device, achieving cycle times in the 40-50 ns range when accounting for the 35 ns tPD plus flip-flop setup. The industrial -40 C to +85 C temperature rating covers factory-floor environments, and the EPROM configuration cell retains state machine definitions across power cycles without external boot memory. Place the EPLD close to the sensors/actuators it controls, route all clocks to the dedicated global clock pin, and use the JTAG port for in-system test and field firmware updates.
Recommended
Legacy Peripheral Bus Interface
The EP1810LI-35 is commonly deployed as a bus-interface bridge between an ISA, PC/104, VME, or STD-bus backplane and a downstream peripheral controller, handling address-latch, data-buffer, and interrupt-acknowledge logic in a single chip. Its 16 dedicated inputs and 48 I/O pins map cleanly onto a 16-bit address bus plus 8/16-bit data bus plus control signals, leaving macrocells free for state-machine glue. The 35 ns tPD adds minimal wait-state penalty on 8-16 MHz legacy buses, and the TTL-compatible thresholds interface directly with 74LS/74ALS/74F peripherals without level shifters. Socket the EPLD, add 0.1 uF + 10 uF decoupling, and program the JTAG chain to share boundary-scan with neighbouring bus devices.
Recommended
Data Acquisition Front-End Control
In 5 V data-acquisition front ends (A/D converters, sample-and-hold amplifiers, analog multiplexers), the EP1810LI-35 supplies precise timing-and-control logic: it generates A/D start-convert pulses, multiplexer channel-select patterns, FIFO write strobes, and end-of-conversion interrupt vectors. Its deterministic 35 ns tPD provides a stable, jitter-free control path that critical for high-resolution successive-approximation ADCs, and the 48 macrocells can fan out 8-16 channel-select lines plus timing/handshake signals in a single device. The EPROM-based configuration keeps the timing pattern locked once programmed, eliminating the start-up latency seen with SRAM FPGAs. Power the EPLD from a clean 5 V analog/digital split rail with a ferrite bead and 0.1 uF decoupling to prevent logic noise from coupling into the analog front end.
Recommended
Avionics & Defense Legacy Systems
Defense and aerospace platforms with long service lives (20-40 years) rely on the EP1810LI-35 and its Mil-temp / 883B-screened siblings (EP1810GM883B, EP1810GM/883B) for flight-control glue logic, MIL-STD-1553 bus interfaces, radar timing generators, and panel-control decoders. The industrial/military temperature grades and ceramic-package options on the same EP1810L die family allow drop-in upgrades from commercial to Mil-spec without PCB changes. Rochester Electronics' authorized Altera legacy manufacturing sustains long-term supply for these programs. Use the JTAG port for in-system test per IEEE 1149.1, route critical clocks to the global clock pin, and follow the Altera Classic EPLD design guide for derating rules in high-vibration environments.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LI-35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LI-25 | EP1810LC-35 | EP1810LC-45 | EP1810LC-25 | EP1810JC-35 | EP1810JI-35 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-68 | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | 25 ns (-29%) | 35 ns (identical) | 45 ns (+29%) | 25 ns (-29%) | 35 ns (identical) | 35 ns (identical) |
| Temperature Grade | Industrial (-40 C to +85 C) | Industrial | Commercial/ceramic | Commercial/ceramic | Commercial/ceramic | Commercial/ceramic windowed | Industrial windowed ceramic |
| Package Type | PLCC (plastic) | PLCC (plastic) | Ceramic (windowed) | Ceramic | Ceramic (windowed) | Ceramic windowed | Ceramic windowed industrial |
| JTAG Support | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes | Yes |
| Supply Voltage | 5 V TTL | 5 V TTL | 5 V TTL | 5 V TTL | 5 V TTL | 5 V TTL | 5 V TTL |
| Architecture | Altera Classic EPLD | Altera Classic EPLD | Altera Classic EPLD | Altera Classic EPLD | Altera Classic EPLD | Altera Classic EPLD | Altera Classic EPLD |
Key Differentiators
- Authorized Altera legacy source with sustainable supply (vs EP1810LI-35 (Rochester) vs grey-market EP1810L clones)
- Industrial-grade operating temperature window vs commercial-only ceramic variants (vs EP1810LI-35 vs EP1810LC-35)
- Plastic PLCC-68 vs ceramic-windowed packages (vs EP1810LI-35 vs EP1810JC-35)
Design Notes
Estimated: The EP1810LI-35 draws 50-150 mA typical quiescent current from a 5 V supply, depending on output loading and toggle frequency. Place one 0.1 uF ceramic decoupling capacitor within 5 mm of every VCC/ground pin pair (4 caps total: pins 10, 21, 31, 40 ground; pins 52, 60 VCC) and add a single 10 uF tantalum bulk capacitor near the power-entry point. Route a star-ground topology from the EPLD to the system ground to avoid ground-bounce coupling into adjacent analog sections. The EP1810L 'L' suffix denotes the low-power CMOS variant, so no special heatsinking is required at typical 5 V/100 mA operating points.
Use a PLCC-68 through-hole socket (e.g., Aries 68-6543-10 or equivalent) so the EP1810LI-35 can be removed for reprogramming, replacement, or upgrade to a faster variant (EP1810LI-25). Keep all 16 dedicated inputs and 48 I/O traces short (<50 mm) and route global-clock signals (GCLK, GCLRn) on a dedicated inner layer with a continuous ground plane beneath them to control impedance. Avoid running I/O traces parallel to clock traces for more than 25 mm to minimize crosstalk. The PLCC-68 J-lead footprint tolerates hand-soldering for prototype rework, but production assembly should use a reflow profile with peak temperature 235-245 C per J-STD-020.
Estimated: Three common pitfalls when designing with the EP1810LI-35: (1) exceeding the 5 V supply absolute-maximum rating (6.0 V) during hot-plug events β add a 5.6 V TVS clamp and an RC inrush limiter if the card is field-swappable; (2) using EP1810LC-xx (ceramic) and EP1810LI-35 (plastic) interchangeably on the same BOM without verifying that the ceramic variant's thermal-mass reflow profile matches the plastic variant's β the ceramic package requires a slower cool-down ramp; (3) leaving unused input pins floating β the EP1810L inputs have internal weak pull-ups but TTL noise can still cause spurious transitions; tie all unused inputs to VCC or GND through a 10 kohm resistor. Also note that the '35' speed grade is the slowest in the EP1810L family; do not select it for designs requiring >25 MHz toggle rates on internal feedback paths.
Estimated: The EP1810LI-35 outputs have a typical rise/fall time of 3-5 ns at 50 pF load, which can produce ground-bounce of 0.5-1.0 V on a poorly-decoupled board. To preserve signal integrity, place 47 ohm series damping resistors on outputs driving long traces (>75 mm) or more than 2-3 standard TTL loads, and keep clock-output traces on the inner layer with adjacent ground traces. When interfacing to high-speed memories or microprocessors, add 22-33 ohm damping resistors at the EPLD output to match the controlled-impedance transmission line and suppress ringing. For JTAG chains, ensure TMS and TDI are pulled up to VCC through 10 kohm resistors at the chain-end device, and that TCK is properly terminated if the chain exceeds 100 mm.
Compliance Information
RoHS/REACH compliance not stated in verified distributor data. Original Altera Classic EPLD family pre-dates widespread RoHS adoption; Rochester Electronics' legacy manufacturing typically offers both lead-free and SnPb finish options per customer requirement. AEC-Q100 not applicable (programmable logic, not a discrete automotive IC). Mil-temp / 883B variants exist in the same EP1810L die family (EP1810GM883B, EP1810GM/883B) for defense applications.
