EPM5192GM-2 - 192-Macrocell MAX 5000 EPLD, PGA-84, 55ns | Intel
MPN: EPM5192GM-2 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $118.5 | $11,850.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92 | $92,000.00 |
Drop-in alternatives for EPM5192GM-2 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192GM
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$58 / Unit
View Datasheet βEPM5192GM-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$27.8 / Unit
View Datasheet βEPM5192GM-1/883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$195 / Unit
View Datasheet βEPM5130GM883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$108 / Unit
View Datasheet βEPM5128GM/883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2.1 / Unit
View Datasheet βEPM5192GM-2 Maximum Ratings & Electrical Characteristics
| Family | Altera MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 192 |
| Propagation Delay (tPD) | 55 ns |
| Speed Grade | -2 |
| Process Technology | CMOS |
| Programmability | UV-erasable (windowed package) |
| Package | PGA-84 (Ceramic Pin Grid Array, windowed) |
| Pin Count | 84 |
| Mounting Type | Through-hole (PGA socket) |
| Datasheet Page Count | 52 |
EPM5192GM-2 Pin Configuration
| Pin A1 | I/O β General-purpose I/O pin (function per Altera MAX 5000 datasheet) |
| Pin A2 | I/O β General-purpose I/O pin |
| Pin A3 | I/O β General-purpose I/O pin |
| Pin A4 | I/O β General-purpose I/O pin |
| Pin A5 | I/O β General-purpose I/O pin |
| Pin A6 | I/O β General-purpose I/O pin |
| Pin A7 | GND β Ground |
| Pin A8 | I/O β General-purpose I/O pin |
| Pin A9 | I/O β General-purpose I/O pin |
| Pin A10 | I/O β General-purpose I/O pin |
| Pin A11 | I/O β General-purpose I/O pin |
| Pin B1 | I/O β General-purpose I/O pin |
| Pin B2 | I/O β General-purpose I/O pin |
| Pin B3 | I/O β General-purpose I/O pin |
| Pin B4 | I/O β General-purpose I/O pin |
| Pin B5 | I/O β General-purpose I/O pin |
| Pin B6 | I/O β General-purpose I/O pin |
| Pin B7 | I/O β General-purpose I/O pin |
| Pin B8 | I/O β General-purpose I/O pin |
| Pin B9 | I/O β General-purpose I/O pin |
| Pin B10 | I/O β General-purpose I/O pin |
| Pin B11 | I/O β General-purpose I/O pin |
| Pin C1 | I/O β General-purpose I/O pin |
| Pin C2 | I/O β General-purpose I/O pin |
| Pin C3 | GND β Ground |
| Pin C4 | I/O β General-purpose I/O pin |
| Pin C5 | I/O β General-purpose I/O pin |
| Pin C6 | I/O β General-purpose I/O pin |
| Pin C7 | I/O β General-purpose I/O pin |
| Pin C8 | I/O β General-purpose I/O pin |
| Pin C9 | GND β Ground |
| Pin C10 | I/O β General-purpose I/O pin |
| Pin C11 | I/O β General-purpose I/O pin |
| Pin D1 | I/O β General-purpose I/O pin |
| Pin D2 | I/O β General-purpose I/O pin |
| Pin D3 | I/O β General-purpose I/O pin |
| Pin D4 | I/O β General-purpose I/O pin |
| Pin D5 | I/O β General-purpose I/O pin |
| Pin D6 | I/O β General-purpose I/O pin |
| Pin D7 | I/O β General-purpose I/O pin |
| Pin D8 | I/O β General-purpose I/O pin |
| Pin D9 | I/O β General-purpose I/O pin |
| Pin D10 | I/O β General-purpose I/O pin |
| Pin D11 | I/O β General-purpose I/O pin |
| Pin E1 | GND β Ground |
| Pin E2 | I/O β General-purpose I/O pin |
| Pin E3 | I/O β General-purpose I/O pin |
| Pin E4 | I/O β General-purpose I/O pin |
| Pin E5 | VCC β Positive supply (typically 5 V) |
| Pin E6 | I/O β General-purpose I/O pin |
| Pin E7 | I/O β General-purpose I/O pin |
| Pin E8 | I/O β General-purpose I/O pin |
| Pin E9 | I/O β General-purpose I/O pin |
| Pin E10 | I/O β General-purpose I/O pin |
| Pin E11 | VCC β Positive supply (typically 5 V) |
| Pin F1 | I/O β General-purpose I/O pin |
| Pin F2 | I/O β General-purpose I/O pin |
| Pin F3 | I/O β General-purpose I/O pin |
| Pin F4 | I/O β General-purpose I/O pin |
| Pin F5 | I/O β General-purpose I/O pin |
| Pin F6 | I/O β General-purpose I/O pin |
| Pin F7 | I/O β General-purpose I/O pin |
| Pin F8 | I/O β General-purpose I/O pin |
| Pin F9 | I/O β General-purpose I/O pin |
| Pin F10 | I/O β General-purpose I/O pin |
| Pin F11 | I/O β General-purpose I/O pin |
| Pin G1 | I/O β General-purpose I/O pin |
| Pin G2 | GND β Ground |
| Pin G3 | I/O β General-purpose I/O pin |
| Pin G4 | I/O β General-purpose I/O pin |
| Pin G5 | I/O β General-purpose I/O pin |
| Pin G6 | I/O β General-purpose I/O pin |
| Pin G7 | I/O β General-purpose I/O pin |
| Pin G8 | I/O β General-purpose I/O pin |
| Pin G9 | I/O β General-purpose I/O pin |
| Pin G10 | GND β Ground |
| Pin G11 | I/O β General-purpose I/O pin |
| Pin H1 | I/O β General-purpose I/O pin |
| Pin H2 | I/O β General-purpose I/O pin |
| Pin H3 | I/O β General-purpose I/O pin |
| Pin H4 | I/O β General-purpose I/O pin |
| Pin H5 | I/O β General-purpose I/O pin |
| Pin H6 | I/O β General-purpose I/O pin |
| Pin H7 | I/O β General-purpose I/O pin |
| Pin H8 | I/O β General-purpose I/O pin |
| Pin H9 | I/O β General-purpose I/O pin |
| Pin H10 | I/O β General-purpose I/O pin |
| Pin H11 | I/O β General-purpose I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192GM-2 is suitable for 6 applications: Military and Aerospace Avionics Bus Interface, Industrial Control Glue Logic Consolidation, Telecommunications Backplane Address Decoding, Legacy Computer Peripheral Replacement, Prototype and Engineering Development Platform, Space and Radiation-Tolerant Subsystems.
Military and Aerospace Avionics Bus Interface
The EPM5192GM-2 is well matched to MIL-STD-1553, ARINC 429, and legacy avionics bus-interface consolidation, where the ceramic PGA package provides hermeticity required for flight-qualified hardware. With 192 macrocells, the device can absorb an entire bus-interface state machine, encoder/decoder glue, and interrupt-priority logic in one chip, eliminating 6-10 discrete 22V10 PALs. The 55 ns propagation delay comfortably handles sub-10 MHz avionics bus rates with timing margin. Designers should plan for the through-hole PGA socket to support field-replacement and the UV window to support bench-level firmware updates between flight-qualification cycles.
Recommended
Industrial Control Glue Logic Consolidation
In PLC backplanes, motor-drive controllers, and process-control I/O modules, the EPM5192GM-2 replaces a board-full of discrete 22V10/26V12 PALs with a single high-density EPLD, shrinking the BOM and easing inventory. The 192 macrocells easily handle address decoding across 16-24 bit address buses, peripheral chip-select generation, and watchdog state machines. The CMOS process keeps quiescent power manageable even with all 192 macrocells active, and the wide supply tolerance of the MAX 5000 family tolerates the noisy 5 V rails common in industrial cabinets. Industrial users should plan a re-evaluation against MAX V/MAX 10 CPLDs for new designs.
Recommended
Telecommunications Backplane Address Decoding
The EPM5192GM-2 is widely deployed in legacy telecom backplanes to decode multi-processor address spaces, generate chip-selects for shared memory, and arbitrate DMA channels on VME or Multibus II buses. The 84-pin PGA package exposes enough I/O to drive 8-10 chip-selects plus control strobes directly, and the deterministic 55 ns delay simplifies worst-case timing closure. Because telecom OEMs maintain equipment for 20-30 years, the EPM5192GM-2's mature status is actually an advantage - the part is unlikely to be obsoleted mid-program. Lifecycle planning should include stocking safety stock and qualifying the EPM5192GM-1 grade as a second source.
Recommended
Legacy Computer Peripheral Replacement
The EPM5192GM-2 is commonly used to sustain legacy VMEbus, VXIbus, and Multibus systems by emulating obsolete peripheral controllers, DMA engines, and interrupt handlers in a single reprogrammable device. The 192-macrocell density handles the equivalent of 8-12 discrete PALs and a handful of 74LS glue logic, restoring board functionality without re-spinning the entire backplane. The UV window allows engineering teams to iterate firmware fixes for new peripheral attachments without board rework. Recommended pairing with the EPM5192GM-1 grade when timing margin becomes a concern in faster peripheral upgrades.
Recommended
Prototype and Engineering Development Platform
The EPM5192GM-2's UV-transparent ceramic window makes it a strong laboratory workhorse for developing and iterating state machines, datapath controllers, and interface bridges before committing to one-time-programmable or modern CPLD silicon. Engineers can erase and re-program the device 50-100 times during development, then migrate the verified netlist to a production CPLD (MAX 7000 or MAX V) once the design stabilizes. The 84-pin PGA socket simplifies board bring-up and design swaps. For sustained production, transition to a non-windowed ceramic or plastic package variant from the same MAX 5000 family.
Recommended
Space and Radiation-Tolerant Subsystems
Although not formally radiation-hardened, the EPM5192GM-2's ceramic PGA packaging, mature CMOS process, and Altera MAX 5000 family heritage make it a candidate for non-critical subsystems in low-earth-orbit small-satellite constellations where radiation tolerance budgets allow commercial-grade silicon. The 192 macrocells can host command/telemetry handling, sensor-multiplexing logic, and attitude-control state machines in a single package, reducing board area and mass compared to discrete PAL implementations. The ceramic PGA also tolerates the wide temperature swings of orbital environments better than plastic packages. Mission planners should still perform lot-specific radiation characterization and consider QML-V or QML-Q equivalents for critical functions.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192GM-2 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192GM | EPM5192GM-1 | EPM5192GM-1/883B | EPM5130GM883B | EPM5128GM/883B |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PGA-84 (Ceramic, Windowed) | PGA-84 (Ceramic, Windowed) - same | PGA-84 (Ceramic, Windowed) - same | PGA-84 (Ceramic, Windowed) - same | PGA-84 (Ceramic, Windowed) - same | PGA-84 (Ceramic, Windowed) - same |
| Macrocell Count | 192 | 192 (same die) | 192 (same die) | 192 (same die) | 128 (-33%) | 128 (-33%) |
| Speed Grade | -2 (55 ns) | Default grade | -1 (faster than -2) | -1 + MIL-STD-883B | MIL-STD-883B screened | MIL-STD-883B screened |
| Process / Technology | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable |
| MIL-STD-883B Screening | No (industrial lot) | No | No | Yes | Yes | Yes |
| UV Erasure Window | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Mature, MIL supply may extend | Mature, MIL supply may extend | Mature, MIL supply may extend |
| Approx. Unit Price (qty 100) | 118.50 USD | [DATA_NEEDED: typical qty-100 quote] | [DATA_NEEDED: typical qty-100 quote] | [DATA_NEEDED: typical qty-100 quote] | [DATA_NEEDED: typical qty-100 quote] | [DATA_NEEDED: typical qty-100 quote] |
Key Differentiators
- Same die as -1 grade, lower cost per unit at relaxed timing (vs EPM5192GM-1)
- Higher macrocell density in the same footprint (vs EPM5128GM/883B)
- Industrial-grade screening, lowest unit price among PGA-84 MAX 5000 family (vs EPM5192GM-1/883B)
Design Notes
The ceramic PGA-84 package of the EPM5192GM-2 is hermetic and offers good thermal conductivity but the through-hole pin grid is sized for socket mounting rather than direct PCB heatsinking. Estimate: at 5 V VCC with all 192 macrocells switching at moderate toggle rates, junction-to-ambient thermal resistance (theta_JA) for a PGA-84 in still air is typically 30-40 C/W. Mount the device in a PGA socket with adequate clearance above the PCB; do not pot or encapsulate the UV window.
Use a high-quality PGA-84 socket (e.g., machine-pin or low-insertion-force type) rated for at least 100 insertion cycles to support field replacement and laboratory UV-erase/reprogramming cycles. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close to the pin lead as the socket geometry allows, plus a bulk 10 uF tantalum near the socket. Maintain a ground plane on an inner PCB layer and stitch the PGA socket perimeter with multiple ground via rows for signal-integrity and EMI suppression.
Do not use a plastic-erasable-window simulator (plastic packages) when designing the UV-erase procedure - only the ceramic-windowed PGA variant erases properly under UV exposure. Cover the quartz window with opaque electrical tape after programming to prevent accidental erasure from ambient UV (sunlight through windows, fluorescent lamps). For prototype re-erase cycles, use a calibrated UV eraser rated at the wavelength and intensity specified in the Altera MAX 5000 datasheet - typically 12 mW/cm^2 at 253.7 nm for 20-30 minutes.
Compliance Information
Ceramic PGA with UV window typically non-RoHS due to historical lead-bearing ceramic/brazing materials. RoHS and lead-free status must be verified lot-by-lot with the franchised distributor. AEC-Q100 is not applicable - this is a programmable logic device, not an automotive analog/digital IC. The /883B variants carry MIL-STD-883B environmental screening instead.
