10AS032H2F35I1HG - Arria 10 SX SoC, 320K LE, 1152-FBGA | Altera
MPN: 10AS032H2F35I1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4200 | $4,200.00 |
| 10 | $3890 | $38,900.00 |
| 50 | $3550 | $177,500.00 |
| 100 | $3200 | $320,000.00 |
| 250 | $2890 | $722,500.00 |
Drop-in alternatives for 10AS032H2F35I1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS032H2F35I2SG
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View Datasheet →10AS032H1F35I1HG
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View Datasheet →10AS032H2F35E1HG
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View Datasheet →10AS032H2F35E2SG
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View Datasheet →10AS032H1F35E1HG
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View Datasheet →10AS032H2F35I1HG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 SX |
| Architecture | SoC FPGA (FPGA + Dual ARM Cortex-A9 MPCore HPS) |
| Logic Elements | 320K |
| Processor Subsystem | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Hard Memory Controllers | DDR3/DDR4 with ECC (HPS and FPGA fabric) |
| User I/Os | 384 |
| Transceivers | Up to 24 channels, up to 12.5 Gbps |
| Speed Grade | H2 (mid-performance) |
| Package | 1152-FBGA, FC (35 mm x 35 mm) |
| Package Code | F35 |
| Temperature Grade | Industrial (-40C to +100C) |
| Mounting Type | Surface Mount (FCBGA, lead-free) |
| HPS Clock Frequency | Up to 1.5 GHz (per family datasheet) |
| Configuration | QSPI flash, SD card, JTAG (HPS-driven or fabric-driven) |
| RoHS Status | Compliant (per distributor product page) |
10AS032H2F35I1HG f35 Pin Configuration Guide
Complete pinout information for 10AS032H2F35I1HG (f35 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS032H2F35I1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H2F35I1HG is suitable for 6 applications: Industrial Motor Control and Drives, Machine Vision and Industrial Inspection, Software-Defined Radio Baseband, Broadcast Video Processing, Medical Imaging Pre-Processing, Military and Aerospace Signal Processing.
Industrial Motor Control and Drives
The 10AS032H2F35I1HG fits industrial motor control because the dual-core ARM Cortex-A9 hard processor system runs real-time protocols (EtherCAT, Profinet, CANopen) while the 320K logic-element FPGA fabric implements deterministic current-loop control, PWM generation, and encoder decoding in hardware. The 12.5 Gbps transceivers support high-bandwidth fieldbus and resolver feedback, and the industrial temperature grade (-40C to +100C) covers factory-floor cabinets. Designers typically offload torque-loop computation to the FPGA fabric to achieve sub-microsecond loop times that a software-only controller cannot match.
Recommended
Machine Vision and Industrial Inspection
The 10AS032H2F35I1HG suits high-speed machine vision because the FPGA fabric delivers parallel pixel processing at line rate for Camera Link or CoaXPress interfaces, while the dual-core ARM Cortex-A9 handles host communication (GigE Vision, USB3 Vision) and inspection orchestration. The 320K logic elements support multiple image-processing pipelines simultaneously, and the hardened DDR4 controller with ECC enables reliable handling of large frame buffers. Industrial temperature rating ensures consistent performance in factory inspection cells.
Recommended
Software-Defined Radio Baseband
The 10AS032H2F35I1HG is well matched to software-defined radio baseband because the 24 transceiver channels at up to 12.5 Gbps aggregate multi-band RF data into the FPGA, where digital down-conversion, channelization, and demodulation run in fabric. The ARM Cortex-A9 cores then handle higher-layer protocol stack, encryption, and IP packetization. The 320K logic elements and approximately 1.6 Mbits of embedded memory (M20K blocks) are sufficient for LTE small-cell or tactical-radio workloads, while industrial temperature rating supports outdoor deployments.
Recommended
Broadcast Video Processing
The 10AS032H2F35I1HG serves broadcast video processing because the FPGA fabric implements multi-channel SD/HD/3G-SDI and emerging 12G-SDI interfaces with on-the-fly scaling, de-interlacing, and overlay. The ARM Cortex-A9 subsystem manages IP-based studio workflows (SMPTE 2022, NDI, SMPTE 2110) and metadata. The 384 user I/Os and 24 high-speed transceivers provide ample connectivity for ingest, processing, and playout channels in a single chip, reducing bill-of-materials cost versus discrete FPGA plus external processor designs.
Recommended
Medical Imaging Pre-Processing
The 10AS032H2F35I1HG is a strong fit for medical imaging front-ends (ultrasound beamforming, CT reconstruction preprocessing, endoscopy video processing) because the FPGA fabric executes beamforming or filter-back-projection kernels deterministically and in parallel, while the ARM Cortex-A9 cores manage DICOM networking, user interface, and patient-data encryption. The DDR4 controller with ECC protects image-data integrity, and the industrial temperature grade supports operating-room equipment that must remain within spec during extended procedures.
Recommended
Military and Aerospace Signal Processing
The 10AS032H2F35I1HG applies to defense and aerospace signal processing where the FPGA fabric implements high-throughput DSP chains (radar pulse compression, electronic-warfare channelization, satellite-comm modem functions) and the ARM Cortex-A9 subsystem handles mission management and secure communications. The industrial temperature grade supports avionics bays and ground-mobile platforms, while the 1152-ball FCBGA package provides robust board-level reliability. Conduction-cooled chassis designs commonly use this part for its balance of logic density and HPS integration.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H2F35I1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H2F35I2SG | 10AS032H1F35I1HG | 10AS032H2F35E1HG | 10AS032H2F35E2SG | 10AS032H1F35E1HG |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA, F35 (35 mm) | 1152-FBGA, F35 (35 mm) - same | 1152-FBGA, F35 (35 mm) - same | 1152-FBGA, F35 (35 mm) - same | 1152-FBGA, F35 (35 mm) - same | 1152-FBGA, F35 (35 mm) - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Series | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX | Arria 10 SX |
| Logic Elements | 320K | 320K | 320K | 320K | 320K | 320K |
| Speed Grade | H2 | H2 | H1 (slower) | H2 | H2 | H1 (slower) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| HPS (ARM Cortex-A9) | Dual-core | Dual-core | Dual-core | Dual-core | Dual-core | Dual-core |
| Transceivers | Up to 24 channels, 12.5 Gbps | Up to 24 channels, 12.5 Gbps | Up to 24 channels, 12.5 Gbps | Up to 24 channels, 12.5 Gbps | Up to 24 channels, 12.5 Gbps | Up to 24 channels, 12.5 Gbps |
Key Differentiators
- Industrial temperature grade with hard ARM Cortex-A9 HPS (vs 10AS032H2F35E1HG)
- Higher speed grade for timing closure margin (vs 10AS032H1F35I1HG)
- Mid-range SoC FPGA with hardened peripherals (vs Cyclone V SoC (e.g. 5CSEBA6U23I7))
Design Notes
Estimated: at typical SoC FPGA utilization (~70% logic, HPS active, transceiver banks active), the 10AS032H2F35I1HG dissipates approximately 15 to 25 W. The 1152-ball FCBGA package requires a thermal management strategy combining an exposed-die heat spreader, thermal interface material, and a heatsink with adequate airflow. Designers should use the Arria 10 thermal model in Quartus Prime PowerPlay to compute junction temperature for their specific activity profile. Industrial deployments must keep Tj below 100C even at 70C ambient.
The 1152-FBGA F35 package uses 1.0 mm ball pitch with flip-chip mounting, requiring a high-layer-count PCB (typically 12 to 16 layers) with stacked microvia (HDI) construction. All transceiver lanes must be length-matched within the tolerances specified in the Arria 10 device handbook, and the DDR4 interface should route on inner layers with reference planes on both sides. Power distribution requires multiple decoupling capacitors placed as close to the balls as via-in-pad geometry allows, with separate rails for HPS, fabric, and transceiver supplies.
Do not confuse the F35 (35 mm) FCBGA with the smaller F29 (29 mm) or F34 (34 mm) FCBGA variants in the Arria 10 SX family - the ball maps are not pin-compatible. Verify the speed grade (H1 vs H2) before final BOM lock, because downgrading to H1 may cause timing closure failures on designs that rely on H2 margins. Also confirm the HPS boot configuration (QSPI vs SD vs NAND) matches the production firmware, as boot-mode straps are sampled on reset and cannot be changed in software.
Arria 10 SX transceiver channels up to 12.5 Gbps require strict impedance control (typically 100 ohm differential with 85 ohm common-mode for some protocols) and continuous reference planes beneath the lanes. AC-coupling capacitors must be placed within the spacing limits defined by the protocol (PCIe, CPRI, 10 GbE) - missing or misplaced AC caps are a common cause of link-training failures. Use the Arria 10 transceiver toolkit in Quartus Prime to pre-emphasize and pre-tune the SerDes settings for your backplane or cable plant.
Compliance Information
RoHS compliance inferred from Altera/Intel PSG product family statements and distributor listings. AEC-Q100 not applicable for industrial-grade FPGA (different qualification standard). Halogen-free status not explicitly confirmed in available web data - set to unknown.
