10AS057K3F35I2SG - Arria 10 SX 570K LE SoC FPGA | Intel
MPN: 10AS057K3F35I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3566.65 | $3,566.65 |
| 10 | $3388.32 | $33,883.20 |
| 100 | $3210 | $321,000.00 |
| 500 | $3031.65 | $1,515,825.00 |
| 1,000 | $2853.32 | $2,853,320.00 |
Drop-in alternatives for 10AS057K3F35I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS057K3F35I2LG
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View Datasheet →10AS057K3F35I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Device Variant | 10AS057 |
| Logic Elements | 570K |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| User I/O Count | 396 |
| Package | 1152-FBGA, FC (35x35 mm) |
| Speed Grade | K3 |
| Operating Temperature | -40C to +100C (Industrial, I2) |
| Process Technology | 20nm |
| Memory Controller | Hard DDR3/4 controller in HPS and FPGA fabric |
| Transceivers | Multi-gigabit transceivers (per Arria 10 SX family datasheet) |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| RoHS Status | Compliant (per Altera product page) |
| Product Type | SoC FPGA - Embedded System on Chip |
10AS057K3F35I2SG 1152-fbga, fc (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS057K3F35I2SG (1152-fbga, fc (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K3F35I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K3F35I2SG is suitable for 6 applications: Industrial Machine Vision, Software Defined Radio (SDR) Baseband, Medical Imaging Systems, Military and Aerospace Signal Processing, Video Broadcast Processing, High-Performance Embedded Computing.
Industrial Machine Vision
The 10AS057K3F35I2SG's 570K logic elements and 396 user I/O pins make it well suited for multi-camera machine vision systems where deterministic frame processing is required. The dual-core ARM Cortex-A9 HPS at 1.5 GHz runs the Linux-based vision stack, OpenCV pipelines, and GigE Vision/USB3 camera management, while the FPGA fabric accelerates Bayer demosaicing, lens distortion correction, and CNN inference at line rate. The 1152-FBGA package supports the multi-gigabit transceivers needed for CoaXPress or 10 GigE camera links. Industrial temperature grade (-40C to +100C) ensures reliable operation on factory floors.
Recommended
Software Defined Radio (SDR) Baseband
The 10AS057K3F35I2SG integrates the high DSP block count and multi-gigabit transceivers required for SDR baseband processing. The FPGA fabric implements wideband digital down-conversion, channelization, and modulation/demodulation in real time, while the Cortex-A9 HPS handles the MAC layer, network stack, and configuration management. The 1.5 GHz HPS frequency supports LTE and 5G NR L2/L3 processing for small-cell and tactical radio applications. Industrial temperature operation suits outdoor base station and military radio deployments.
Recommended
Medical Imaging Systems
The 10AS057K3F35I2SG's combination of 570K logic elements, dual ARM Cortex-A9 cores, and 396 user I/O makes it a strong fit for ultrasound, CT, and MRI front-end processing. The FPGA fabric performs beamforming, FFT-based image reconstruction, and real-time filtering on high-channel-count data streams, while the HPS runs the user interface, DICOM stack, and patient database connectivity. The Arria 10 SX 20nm process provides the thermal headroom needed for fan-less medical enclosures, and the industrial temperature rating supports clinical environments.
Recommended
Military and Aerospace Signal Processing
The 10AS057K3F35I2SG meets industrial temperature range requirements for military signal processing applications including electronic warfare, radar front-end processing, and avionics display systems. The 570K LE fabric implements high-throughput FFT, pulse compression, and digital beamforming for phased-array radar, while the Cortex-A9 HPS runs mission software and sensor fusion. The ruggedized 1152-FBGA flip-chip BGA package withstands vibration and thermal cycling typical of aerospace platforms.
Recommended
Video Broadcast Processing
The 10AS057K3F35I2SG's 570K logic elements and multi-gigabit transceivers support professional video broadcast workflows including 4K/UHD HEVC encoding, HDR processing, and SDI/HDMI bridging. The FPGA fabric handles real-time video scaling, color space conversion, and overlay composition, while the Cortex-A9 HPS manages IP streaming, SNMP, and front-panel control. The 396 user I/O provides the high pin count needed for parallel video interfaces, 12G-SDI transceivers, and PCIe Gen2/3 host connectivity in broadcast studio equipment.
Recommended
High-Performance Embedded Computing
The 10AS057K3F35I2SG is well matched to high-performance embedded computing platforms such as VPX, OpenVPX, and CompactPCI Serial cards where deterministic FPGA acceleration plus a Linux-capable host processor are required. The dual-core ARM Cortex-A9 at 1.5 GHz provides ample headroom for payload software, while the 570K LE fabric accelerates sensor I/O, protocol termination, and DSP. The 1152-FBGA package and industrial temperature rating suit deployed embedded systems in transportation, energy, and industrial automation.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K3F35I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K3F35I2LG | 10AS057K3F35E2SG | 10AS057K2F35I2SG | 10AS057K2F35I1HG | 10AS057K2F35E1HG |
|---|---|---|---|---|---|---|
| Package | 1152-FBGA, FC (35x35 mm) | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | K3 | K3 | K3 | K2 (slower) | K2 (slower) | K2 (slower) |
| Temperature Grade | Industrial I2 (-40C to +100C) | Industrial I2 | Commercial E2 (0C to +100C) | Industrial I2 | Industrial I1 | Commercial E1 |
| Logic Elements | 570K | 570K | 570K | 570K | 570K | 570K |
| HPS Core | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz | Dual ARM Cortex-A9 1.5 GHz |
| User I/O | 396 | 396 | 396 | 396 | 396 | 396 |
| Lead-Free | Yes (per SG suffix convention) | Yes (LG suffix) | Yes (SG suffix) | Yes (SG suffix) | Yes (HG suffix) | Yes (HG suffix) |
Key Differentiators
- K3 speed grade balances performance and power for mid-range embedded designs (vs 10AS057K2F35I2SG)
- Industrial -40C to +100C temperature range (vs 10AS057K3F35E2SG)
- Dual-core ARM Cortex-A9 HPS with CoreSight debug (vs Cyclone V SoC (5CSEBA6U23I7))
Design Notes
The 1152-FBGA flip-chip package (35x35 mm) can dissipate significant power under sustained 570K LE fabric utilization. Estimated: at typical Arria 10 SX utilization of 70 percent fabric and 1.5 GHz HPS, total power can reach 25-30 W. The exposed die flip-chip BGA requires a thermal interface material and either a heatsink or chassis thermal path. Refer to the Intel Arria 10 SX PowerPlay Early Power Estimator before final PCB layout.
Use a minimum 12-layer PCB stack-up with dedicated ground and power planes to maintain signal integrity for the multi-gigabit transceivers and DDR3/4 interfaces. Place 0.1 uF decoupling capacitors on every power pin within 100 mils of the BGA pad, and add bulk 47 uF and 220 uF capacitors near the package perimeter. Matched-length routing is required for the HPS DDR controller and FPGA memory interfaces per the Arria 10 SX pin connection guidelines.
Do not attempt to boot the HPS without populating the QSPI flash and configuring the boot mode straps correctly. Ensure the MSEL pins are set to the correct AS x4 or QSPI mode for your chosen boot source. The configuration flash (EPCQ-L) must match the bitstream compression and encryption settings. Refer to the Intel Arria 10 SX Configuration User Guide and the Golden System Reference Design (GSRD) on RocketBoards.org for the validated boot flow.
Route the high-speed transceiver channels on the top layers with reference ground plane directly beneath, using microstrip or stripline as required by the data rate. Maintain 100 ohm differential impedance and use AC-coupling capacitors at the FPGA transmitter pins. Keep the transceiver reference clock lines short and well-isolated from noisy digital signals. The HPS RGMII interface to an external PHY also requires length-matched routing and proper source termination.
Compliance Information
RoHS and lead-free status inferred from Altera product page and 'G' suffix convention. AEC-Q100 not applicable (industrial FPGA, not automotive-qualified). REACH compliance assumed per Intel product policy.
