10AX090S3F45I2LG - Arria 10 GX 900K LE FPGA, 1932-FCBGA | Intel / Altera
MPN: 10AX090S3F45I2LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4380 | $438,000.00 |
| 250 | $4200 | $1,050,000.00 |
| 500 | $4050 | $2,025,000.00 |
Drop-in alternatives for 10AX090S3F45I2LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AX090S2F45I2LG
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View Datasheet β10AX090S3F45I2LG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory | 59,234,304 bits (1,830 M20K blocks) |
| DSP Blocks | 759 (variable-precision, hardened 27x27 multipliers) |
| User I/O Count | 624 |
| Transceivers | Up to 24.0 Gbps (GX family) |
| PCIe Hard IP | PCI Express Gen3 x8 (hardened) |
| Memory Interface Hard IP | DDR4 / LPDDR4 / DDR3 up to 2666 Mbps |
| Package | 1932-ball FCBGA (F45, 45x45 mm) |
| Speed Grade | -I2 (industrial) |
| Operating Temperature | -40C to +100C (industrial Tj) |
| Process Technology | 20nm Tri-Gate |
| Configuration | Partial reconfiguration, AES-256 bitstream encryption |
| Supply Voltage (Core) | 0.85 V (nominal VCORE) |
| Mounting Type | Surface Mount (BGA) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
10AX090S3F45I2LG Pin Configuration
| Pin B2 | VCC β Core supply voltage (0.85 V typical) |
| Pin B4 | GND β Ground reference |
| Pin B5 | GXB_TX_p β Transceiver differential transmit (positive) |
| Pin B6 | GXB_TX_n β Transceiver differential transmit (negative) |
| Pin C3 | GXB_RX_p β Transceiver differential receive (positive) |
| Pin C4 | GXB_RX_n β Transceiver differential receive (negative) |
| Pin D2 | IO_BANK_3A β I/O bank 3A (LVDS/SSTL/HSTL) |
| Pin E2 | IO_BANK_4A β I/O bank 4A (LVDS/SSTL/HSTL) |
| Pin F3 | REFCLK_p β Reference clock input (positive) |
| Pin F4 | REFCLK_n β Reference clock input (negative) |
| Pin G2 | TCK β JTAG test clock |
| Pin G3 | TMS β JTAG test mode select |
| Pin H2 | TDI β JTAG test data in |
| Pin H3 | TDO β JTAG test data out |
| Pin J2 | nCONFIG β Configuration control (active low) |
| Pin J3 | nSTATUS β Configuration status (active low) |
| Pin K2 | DCLK β Configuration clock |
| Pin K3 | DATA0 β Configuration data input |
| Pin L2 | MSEL0 β Configuration mode select bit 0 |
| Pin L3 | MSEL1 β Configuration mode select bit 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090S3F45I2LG is suitable for 7 applications: 4K UHD Broadcast Video Processing, 100G Ethernet MAC Bridging and Aggregation, Software-Defined Radio (SDR) Baseband Processing, Radar Front-End Preprocessing (AESA / Phased Array), High-Performance Medical Imaging (CT / MRI Reconstruction), 5G Fronthaul / CPRI / eCPRI Aggregation, Industrial Vision and Machine Learning Inference.
4K UHD Broadcast Video Processing
The 10AX090S3F45I2LG is well-suited for 4K UHD broadcast encoders and decoders requiring simultaneous multi-stream processing. With 900K logic elements and 1,830 M20K memory blocks (59.2 Mbits), the FPGA can hold multiple line buffers for deinterlacing, scaling, and color-space conversion at 60 fps without external DDR. The 12 hardened 24.0 Gbps transceivers handle SDI (3G-SDI/12G-SDI), SMPTE 2110 IP, and HDMI 2.0 interfaces, eliminating external serializer/deserializer ICs. Its 759 variable-precision DSP blocks accelerate HEVC/H.265 motion estimation and rate-distortion optimization, while the -I2 industrial speed grade maintains deterministic latency over the full 0C to +100C junction temperature range required for outdoor broadcast enclosures.
Recommended
100G Ethernet MAC Bridging and Aggregation
In 100 Gigabit Ethernet aggregation line cards, the 10AX090S3F45I2LG serves as the MAC-layer bridge between multiple 25G/40G/100G uplinks. Its 12 transceivers running at 25.78 Gbps can bond into one 100G link or fan out into four 25G KR/CR interfaces, while the embedded 100G MAC IP core (free with Quartus Prime) handles frame parsing, CRC, and statistics. The hard PCIe Gen3 x8 IP enables direct attachment to host CPUs or switching ASICs, and the 759 DSP blocks accelerate tunnel encapsulation (VxLAN, Geneve) and congestion-control algorithms. Industrial -I2 grading ensures reliability in carrier-grade central-office deployments where ambient temperatures can reach 70C.
Recommended
Software-Defined Radio (SDR) Baseband Processing
Military and commercial SDR systems use the 10AX090S3F45I2LG as the digital baseband processor between the RF front-end and the host CPU. Its high DSP count (759 variable-precision blocks) supports wideband waveform demodulation, channelization, and adaptive filtering at baseband bandwidths up to 200 MHz per channel. The 24.0 Gbps transceivers interface directly to wideband ADCs and DACs via JESD204B/C, while the hard memory controllers support DDR4/LPDDR4 at 2666 Mbps for fast sample buffering. Partial reconfiguration enables waveform swapping on-the-fly (e.g., switching from wideband SATCOM to narrowband LOS), and AES-256 bitstream encryption protects IP against reverse engineering in deployed field units.
Recommended
Radar Front-End Preprocessing (AESA / Phased Array)
Active Electronically Scanned Array (AESA) radar systems leverage the 10AX090S3F45I2LG for pulse compression, digital beamforming, and Doppler filtering across thousands of receiver channels. The 24.0 Gbps transceivers accept digitized sub-array data from multiple analog front-ends, while the 759 DSP blocks compute FFTs, matched filters, and space-time adaptive processing (STAP) kernels. The 59.2 Mbit embedded M20K memory holds beam-weight tables and adaptive coefficient matrices without external access stalls, and the PCIe Gen3 x8 hard IP streams processed tracks to the radar controller. Industrial -I2 speed grade guarantees operation across the full military temperature range required for airborne and shipboard radar installations.
Recommended
High-Performance Medical Imaging (CT / MRI Reconstruction)
In CT and MRI imaging systems, the 10AX090S3F45I2LG accelerates image reconstruction algorithms such as filtered back-projection and iterative reconstruction. The 900K logic elements and 759 hardened floating-point DSP blocks enable real-time cone-beam CT reconstruction at 30 fps with sub-millimeter resolution, while 59.2 Mbit embedded memory holds intermediate sinogram and image slices. The 12 transceivers aggregate data from 32-128 channel detector arrays, and the hard DDR4 controller feeds a multi-gigabyte external image buffer. Industrial temperature grading ensures 24/7 reliability in the heated environment of an MRI machine room, and AES-256 bitstream encryption protects patient-data-processing IP from tampering.
Recommended
5G Fronthaul / CPRI / eCPRI Aggregation
The 10AX090S3F45I2LG is ideal for 5G fronthaul aggregation hubs that bridge eCPRI/CPRI traffic between radio units (RUs) and distributed units (DUs). With 12 transceivers at up to 24.0 Gbps, the FPGA can aggregate multiple 10.1G/24.3G CPRI links or 25G eCPRI links while the embedded 759 DSP blocks handle optional LDPC/Polar FEC encoding/decoding and packet header compression. The hard PCIe Gen3 x8 IP connects to a baseband processor card, and partial reconfiguration allows operators to load new fronthaul protocols (CPRI v7.0, eCPRI v2.0) without hardware replacement. The -I2 industrial speed grade is critical for outdoor small-cell deployments where junction temperatures can swing from -40C to +95C.
Recommended
Industrial Vision and Machine Learning Inference
High-throughput machine-vision systems use the 10AX090S3F45I2LG to accelerate convolutional neural network (CNN) inference at the edge for defect detection and quality control. The 759 variable-precision DSP blocks implement INT8/INT16 tensor operations, while the 900K logic elements hold weight buffers and activation maps for popular CNN architectures (ResNet-50, MobileNet). The 12 transceivers aggregate data from multiple CoaXPress or Camera Link cameras at up to 12.5 Gbps per link, and PCIe Gen3 x8 streams inference results to a PLC or industrial PC. Hardened Secure Device Manager prevents IP theft of trained model weights via bitstream encryption, and the industrial -I2 speed grade supports operation in factory-floor enclosures.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090S3F45I2LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090S2F45I2LG | 10AX090S2F45I2SG | 10AX090S2F45I1SG | 10AX090S3F45E2SG | 10AX090S3F45E2LG |
|---|---|---|---|---|---|---|
| Package | 1932-FCBGA (F45) | 1932-FCBGA (F45) - same | 1932-FCBGA (F45) - same | 1932-FCBGA (F45) - same | 1932-FCBGA (F45) - same | 1932-FCBGA (F45) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Speed Grade | -I3 (industrial, fastest) | -I2 | -I2 | -I1 | -E2 (extended temp) | -E2 (extended temp) |
| Operating Temperature | -40C to +100C Tj | -40C to +100C Tj | -40C to +100C Tj | -40C to +100C Tj | 0C to +100C Tj | 0C to +100C Tj |
| Embedded Memory | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit |
| DSP Blocks | 759 | 759 | 759 | 759 | 759 | 759 |
| Max Transceiver Rate | 24.0 Gbps | 24.0 Gbps | 24.0 Gbps | 24.0 Gbps | 24.0 Gbps | 24.0 Gbps |
| User I/O | 624 | 624 | 624 | 624 | 624 | 624 |
| Approximate Qty-1 Price (USD) | $4,850 (as of 2026-09-05) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest industrial speed grade (-I3) in the Arria 10 GX 900K-LE F45 package (vs 10AX090S2F45I2LG)
- Hardened 24.0 Gbps transceiver IP eliminates external SerDes ICs (vs 10AX090S3F45E2SG)
- Industrial -40C to +100C Tj vs extended 0C to +100C Tj (vs 10AX090S3F45E2LG)
Design Notes
At full transceiver utilization with 12 channels active at 14 Gbps plus 80% logic utilization, the 10AX090S3F45I2LG typically dissipates 35-45W. The 1932-FCBGA package requires a high-performance heatsink with theta_JA below 1.0 C/W and adequate airflow (>=200 LFM) to keep Tj below 100C. Use the Altera PowerPlay Early Power Estimator before PCB layout to size your VCORE (0.85V), VCCR (1.0V), and VCCT (1.0V) rails. Estimated: peak power 45W at 200 LFM requires a 6mm-fin heatsink rated at 0.5 C/W.
The 1932-FCBGA package requires a 1.0 mm pitch BGA fanout with microvia stack-ups on a >=16-layer PCB. Use low-Dk/Df laminates (e.g., Isola I-Tera MT40 or Panasonic MEGTRON 6) to control channel loss on the 24 Gbps transceiver pairs. Route all GXB_TX/RX pairs as length-matched, impedance-controlled differential pairs with reference planes on adjacent layers. The Altera Arria 10 device handbook provides full PCB stack-up guidelines and via-stub recommendations.
The 10AX090S3F45I2LG requires multiple supply rails: VCORE (0.85V, ~25A peak), VCCR (1.0V for transceiver receiver, ~8A), VCCT (1.0V for transceiver transmitter, ~8A), VCCAUX (1.8V, ~2A), and VCCIO (1.2V/1.5V/1.8V per bank, ~3A total). Use a multi-phase PWM controller such as the ISL6367 or IR35201 with per-rail inductors <100 nH. Decoupling: place 220 nF and 100 nF X7R 0402/0201 capacitors directly under the BGA escape vias. Estimated: total decoupling capacitor count for a full 1932-FCBGA is approximately 400-500 capacitors across the bottom layer.
Do NOT confuse the 10AX090S3F45I2LG (Arria 10 GX) with the 10AX090U2F45I2LG (Arria 10 GT) or 10AT090S3F45I2LG (Arria 10 SX SoC variant with ARM Cortex-A9). The GXB transceiver rate is hard-limited to 24.0 Gbps on the GX family; reaching 28.1 Gbps requires the GT family. Partial reconfiguration requires Quartus Prime Pro and a separate PR region in your floorplan. Configuration via JTAG requires the USB-Blaster II; older USB-Blaster cables do not support Arria 10.
Compliance Information
RoHS compliant per Altera product page material attributes. Halogen-free per JEDEC JS709B. Conflict-mineral (3TG) declarations available via Intel Altera supplier portal. Not AEC-Q100 qualified (FPGA is not an automotive-grade part).
