10AX090S3F45E2LG - Arria 10 GX FPGA 900K LE, 1932-FCBGA | Intel
MPN: 10AX090S3F45E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $15820 | $15,820.00 |
| 10 | $14950 | $149,500.00 |
| 100 | $14100 | $1,410,000.00 |
| 500 | $13250 | $6,625,000.00 |
| 1,000 | $12480 | $12,480,000.00 |
Drop-in alternatives for 10AX090S3F45E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX090S2F45E2LG
✅ Drop-In✓ In Stock
$3750 / Unit
View Datasheet →10AX090S2F45E2SG
✅ Drop-In✓ In Stock
$2050 / Unit
View Datasheet →10AX090S2F45E1SG
✅ Drop-In✓ In Stock
$4890 / Unit
View Datasheet →10AX090S1F45E1SG
✅ Drop-In✓ In Stock
$8200 / Unit
View Datasheet →10AX090R4F40E3LG
✅ Drop-In✓ In Stock
$4415.91 / Unit
View Datasheet →10AX090R3F40E2LG
✅ Drop-In✓ In Stock
$5750 / Unit
View Datasheet →10AX090S3F45E2LG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Logic Elements | 900,000 |
| Adaptive Logic Modules (ALMs) | 339,620 |
| Embedded Memory (bits) | 59,234,304 |
| DSP Blocks | 1,518 |
| Transceivers | 624 (per package aggregate channels) |
| Maximum Transceiver Data Rate | 17.4 Gbps (GX variant, datasheet ceiling up to 25.78 Gbps on GT) |
| Package | 1932-ball FCBGA (F45, 45mm flip-chip BGA) |
| Process Node | TSMC 20nm |
| Core Voltage (nominal) | 0.9 V |
| User I/O Banks | 12 |
| Maximum User I/O | 624 |
| Operating Temperature Range | 0C to 100C (E2 commercial) |
| Speed Grade | S3 (-2 speed grade equivalent) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Memory Interfaces | DDR4 up to 2666 MT/s, DDR3, QDR IV, RLDRAM 3 |
10AX090S3F45E2LG 1932-ball fcbga (f45, 45mm flip-chip bga) Pin Configuration Guide
Complete pinout information for 10AX090S3F45E2LG (1932-ball fcbga (f45, 45mm flip-chip bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090S3F45E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090S3F45E2LG is suitable for 8 applications: 10G/25G Optical Transport Networking, Wireless Baseband and CPRI Processing, Phased-Array Radar Signal Processing, Medical Imaging and Diagnostic Equipment, High-Performance Compute Acceleration, Broadcast Video Processing and 4K/8K Routing, Test and Measurement Instrumentation, Industrial Factory Automation and Machine Vision.
10G/25G Optical Transport Networking
The 10AX090S3F45E2LG fits 10G and 25G optical transport line cards because of its 624 high-speed transceivers operating up to 17.4 Gbps per lane (and up to 25.78 Gbps on GT channels) and its integrated hard IP for 10G/25G Ethernet, Interlaken, and CPRI. Placed as the central switching/forwarding engine, it aggregates multiple SFP+/SFP28 optical modules and feeds a backplane or fabric ASIC. The 900K logic elements plus 1,518 hardened floating-point DSP blocks deliver wire-speed packet processing, MAC/PCS offload, and OTN framer functions without external ASSPs. Power consumption typically sits in the 20-35W range at full utilization, requiring a heatsink.
Recommended
Wireless Baseband and CPRI Processing
The 10AX090S3F45E2LG is well-matched to 4G/5G baseband units where CPRI and eCPRI links between BBU and RRU must be processed in real time. The device's transceivers support up to 24 Gbps data rates, sufficient for 8x CPRI 9.8G or 4x 25G eCPRI aggregation. The hardened floating-point DSP blocks accelerate FFT, channel estimation, and turbo/Polar decoding while freeing logic for custom MAC scheduling. A typical board uses 2-4 transceivers per sector on a 4T4R radio, so the 624-channel budget covers multiple sectors with headroom. Designers rely on the Arria 10 DDR4 controller to buffer IQ samples.
Recommended
Phased-Array Radar Signal Processing
For military and commercial phased-array radar front-ends, the 10AX090S3F45E2LG provides the wide bandwidth and DSP density required for beamforming and pulse compression. Each transmit/receive channel runs at hundreds of MSPS through ADCs, and the device's parallel DSP fabric performs FFT, windowing, and Doppler processing across thousands of channels. The 900K LE and 59 Mb of embedded memory hold sample buffers and twiddle tables without external SRAM. Operating at commercial temperature, this part suits ground-based and shipboard radar enclosures with controlled cooling.
Recommended
Medical Imaging and Diagnostic Equipment
The 10AX090S3F45E2LG is suitable for high-end medical imaging modalities including ultrasound, CT, and MRI reconstruction. Ultrasound beamforming in particular requires hundreds of parallel multiply-accumulate operations per sample, which the 1,518 hardened floating-point DSP blocks execute efficiently. Compliance with IEC 60601-1 and IEC 62304 is the integrator's responsibility; the part itself is non-medical-grade silicon. Low-latency parallel signal paths reduce image-acquisition latency and enable real-time elastography or 3D rendering. Use the Arria 10 DDR4 controller to stream raw sample data to host processors.
Recommended
High-Performance Compute Acceleration
The 10AX090S3F45E2LG acts as a hardware accelerator for HPC workloads such as genomics, financial Monte Carlo simulation, and machine-learning inference. PCIe Gen3 x8 hard IP provides low-latency host attachment, while multiple transceivers enable direct links to NVMe-over-Fabric or proprietary fabric fabrics. OpenCL and Intel FPGA SDK for OpenCL let developers compile kernels from C/C++ instead of RTL, shortening time-to-results. Sustained floating-point throughput above 1 TFLOP/s is achievable with full DSP utilization, making the device competitive with mid-range GPUs on per-watt metrics.
Recommended
Broadcast Video Processing and 4K/8K Routing
Broadcast video routers and processing frames need multi-gigabit serial links for SDI (up to 12G-SDI) and parallel interfaces for 4K/8K video streams. The 10AX090S3F45E2LG's transceivers convert SDI to packet-based formats while the logic fabric handles format conversion, frame synchronization, and chroma resampling. A typical 8K processing card uses four 12G-SDI inputs feeding the FPGA, with output to HDMI 2.1 or DisplayPort via external bridge chips. The DDR4 memory controller buffers multi-frame stores for processing.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, protocol analyzers, and arbitrary waveform generators use the 10AX090S3F45E2LG for real-time DSP, FFT analysis, and protocol-aware triggering. The 900K LE allow very deep capture memory and complex trigger sequencers running in parallel without missing events. Transceivers are repurposed as digital serial analyzer inputs for PCI Express, USB, and Ethernet compliance testing. The large logic budget also supports customer-definable custom protocols through soft IP, providing a future-proof platform for emerging standards.
Recommended
Industrial Factory Automation and Machine Vision
Multi-camera machine vision systems with real-time inference use the 10AX090S3F45E2LG to aggregate Camera Link, CoaXPress, or GigE Vision streams and run defect-detection classifiers. The hardened floating-point DSP accelerates image preprocessing (filtering, color conversion) while custom logic performs decision-making at line rate. Transceivers enable long-reach CoaXPress links up to 13 Gbps per cable, allowing flexible factory layouts. Industrial temperature variants of this die (10AX090S2F45I2LG or 10AX090S3F45I2SG) extend the operating envelope to -40C to +100C for harsh environments.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090S3F45E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090S2F45E2LG | 10AX090S2F45E2SG | 10AX090S2F45E1SG | 10AX090S1F45E1SG | 10AX090R4F40E3LG | 10AX090R3F40E2LG |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F40) - same ball count, F40 variant | 1932-ball FCBGA (F40) - same ball count, F40 variant |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Speed Grade | S3 (-2) | S2 (-3, faster) | S2 (-3, faster) | S2 (-1, slowest) | S1 (-1, slowest, lower power) | R4 (-3, fastest) | R3 (-2) |
| Operating Temperature | 0C to 100C (E2 commercial) | 0C to 100C (E2 commercial) | -40C to 100C (I2 industrial) | -40C to 100C (I1 industrial) | -40C to 100C (I1 industrial) | 0C to 100C (E3 commercial) | 0C to 100C (E2 commercial) |
| Embedded Memory (Mb) | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 |
| DSP Blocks | 1,518 | 1,518 | 1,518 | 1,518 | 1,518 | 1,518 | 1,518 |
| Transceivers (max) | 624 (up to 17.4 Gbps) | 624 (up to 17.4 Gbps) | 624 (up to 17.4 Gbps) | 624 (up to 17.4 Gbps) | 624 (up to 17.4 Gbps) | 24 transceivers (F40 package reduces count) | 24 transceivers (F40 package reduces count) |
| Typical Price (1 pc, USD) | 15,820 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Lifecycle Status | Active | Active | Active | Active | Active | Active | Active |
Key Differentiators
- Highest density in Arria 10 family with 900K LEs and 624 transceiver channels (vs 10AS066K3F35E2LG)
- Same-package speed-grade flexibility without re-layout (vs 10AX090R4F40E3LG (F40 package))
- Hardened floating-point DSP blocks (vs 10AS057K4F35I3SG)
Design Notes
The 1932-ball F45 FCBGA at full 900K-LE utilization typically dissipates 25-40 W depending on toggle rate and DSP activity. Use the Arria 10 PowerPlay Early Power Estimator before final layout to size the heatsink. A minimum 8-layer PCB stackup with a dedicated inner ground/power plane and an array of thermal vias under the central die area is required. Forced airflow of 200-400 LFM is recommended in chassis with no convection.
Place decoupling capacitors on the bottom side of the PCB directly beneath their associated package balls using microvias. The Intel Arria 10 documentation specifies 0.1 uF X7R ceramics at every power pin group, plus bulk 22-47 uF tantalum or polymer caps at the voltage regulator footprints. Maintain 100 ohm differential impedance for high-speed transceiver channels up to 17.4 Gbps and 85 ohm for lower-speed LVDS. Use length-matching within 0.13 mm for transceiver pairs.
Keep transceiver channels on the package edge, using the shortest possible breakout length. Series coupling capacitors for transceiver TX must be placed within 25 mm of the BGA ball. Avoid crossing transceiver lanes to keep crosstalk below -40 dB. Reference each transceiver RX/TX pair to a continuous ground plane, never split power. Use IBM/Intel reference designators for the lane-to-pin mapping when designing your schematic symbol.
Run pre-layout signal-integrity simulation using the IBIS-AMI models from Intel for every DDR4 byte lane. After board fab, perform post-layout extraction with the same models to verify the timing margins are at least 50 ps for clocks and 30 ps for DQ. For 10G-KR/25G-KR backplanes, use the Arria 10 adaptive equalization (AEQ) blocks to compensate for channel loss. Note that AEQ requires training sequences at startup, which may extend link-up time.
Common design pitfalls: (1) forget to apply SmartVID enable pins - the device will not regulate core voltage if the VID pins are floating; (2) mis-assign the JTAG TCK/TMS pull-downs - the configuration will fail to load if these are not pulled; (3) over-provision PLL reference clocks - the fractional-N PLL will not lock if the reference is unstable; (4) leave configuration mode pins floating - configure them to AS or JTAG mode explicitly before board bring-up.
Compliance Information
RoHS compliance confirmed via Richard Electronics and Altera product page; per the package code BGA1932,44X44,40 description. AEC-Q100 is not applicable to FPGAs (commercial/industrial temperature grades only).
