10AS066H2F34I2SG - Arria 10 SX SoC FPGA 660K LE | Intel
MPN: 10AS066H2F34I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4300 | $430,000.00 |
| 500 | $3920 | $1,960,000.00 |
| 1,000 | $3550 | $3,550,000.00 |
Drop-in alternatives for 10AS066H2F34I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS066H2F34I2LG
✅ Drop-In✓ In Stock
$11050 / Unit
View Datasheet →10AS066H2F34I1HG
✅ Drop-In✓ In Stock
$3500 / Unit
View Datasheet →10AS066H2F34E2SG
✅ Drop-In✓ In Stock
$2400 / Unit
View Datasheet →10AS066H2F34E2LG
✅ Drop-In✓ In Stock
$3250 / Unit
View Datasheet →10AS066H1F34I1HG
✅ Drop-In✓ In Stock
$3720 / Unit
View Datasheet →10AS066H1F34E1HG
✅ Drop-In✓ In Stock
$3900 / Unit
View Datasheet →10AS066H2F34I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Device Name | 10AS066 |
| Logic Elements | 660,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Process Technology | 20 nm |
| Core Voltage | 0.87 V to 0.93 V |
| Maximum Fabric Frequency | 1.5 GHz |
| Number of Terminals | 1152 |
| Package | FC-FBGA-1152 (F34), 35 mm x 35 mm |
| Mounting Type | Surface Mount (BGA) |
| User I/O | 492 inputs / 492 outputs |
| Operating Temperature | -40 °C to +100 °C (Industrial) |
| Temperature Grade | Industrial |
| RoHS Compliance | RoHS Compliant |
| Configuration | FPGA + SoC integrated |
10AS066H2F34I2SG fc-fbga-1152 (f34), 35 mm x 35 mm Pin Configuration Guide
Complete pinout information for 10AS066H2F34I2SG (fc-fbga-1152 (f34), 35 mm x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066H2F34I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066H2F34I2SG is suitable for 7 applications: Wireless Baseband Processing, Broadcast Video Infrastructure, Military Radar Signal Processing, Medical Imaging Equipment, Industrial Motor Control, Test and Measurement Instrumentation, Aerospace Communication Systems.
Wireless Baseband Processing
The 10AS066H2F34I2SG's 660K logic elements and integrated ARM Cortex-A9 HPS make it ideal for wireless baseband processing in 4G/LTE small cells and 5G fronthaul units. The 1.5 GHz fabric Fmax supports real-time FFT/IFFT, channel estimation, and digital predistortion algorithms, while the dual Cortex-A9 cores handle MAC-layer protocol stack and OS-level scheduling. Industrial-grade qualification suits outdoor baseband units.
Recommended
Broadcast Video Infrastructure
The 10AS066H2F34I2SG handles 4K UHD video processing, JPEG2000 encoding/decoding, and SDI/HDMI bridge functions for broadcast studio equipment. Its 660K LEs provide parallel pixel pipelines running at hundreds of MHz, and the HPS runs Linux for control-plane management, SNMP, and IP-based studio routing. Industrial temperature grade suits 24/7 rack operations.
Recommended
Military Radar Signal Processing
With 660K LEs and 1.5 GHz fabric, the 10AS066H2F34I2SG performs pulse-Doppler FFT, MTI filtering, and CFAR detection for ground-based and naval radar systems. Industrial temperature and ruggedized packaging support defense applications. The HPS handles track management and display rendering. Designers should pair with high-speed ADC companion parts.
Recommended
Medical Imaging Equipment
The 10AS066H2F34I2SG accelerates CT, MRI, and ultrasound beamforming by running parallel FIR filtering, back-projection, and image reconstruction pipelines. The dual ARM Cortex-A9 HPS manages patient interface, DICOM networking, and operator console. Industrial temperature and reliability suit medical-grade compliance paths.
Recommended
Industrial Motor Control
The 10AS066H2F34I2SG runs high-FOV field-oriented control (FOC) loops for multi-axis servo drives and industrial robots. The FPGA fabric delivers sub-microsecond current-loop cycles while the HPS Cortex-A9 handles EtherCAT, PROFINET, and motion planning. Industrial temperature grade suits factory floor operation.
Recommended
Test and Measurement Instrumentation
The 10AS066H2F34I2SG's high logic density and ARM HPS make it well suited to benchtop oscilloscopes, logic analyzers, and protocol analyzers. FPGA fabric handles multi-Gbps serial protocol decoding (PCIe Gen3, USB 3.1, SATA) while the HPS runs Linux for UI, networking, and remote control. Industrial grade suits lab/production test environments.
Recommended
Aerospace Communication Systems
The 10AS066H2F34I2SG serves as the central processing element in airborne and UAV communication gateways, where it implements software-defined radio (SDR) waveforms and crypto acceleration. The 660K LEs and Cortex-A9 HPS support multi-band, multi-protocol operation, and the industrial temperature grade suits avionics bay environments.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066H2F34I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066H2F34I2LG | 10AS066H2F34I1HG | 10AS066H2F34E2SG | 10AS066H2F34E2LG |
|---|---|---|---|---|---|
| Package | FC-FBGA-1152 (F34) | FC-FBGA-1152 (F34) | FC-FBGA-1152 (F34) | FC-FBGA-1152 (F34) | FC-FBGA-1152 (F34) |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Speed Grade | -2 (H2) | -2L (H2) | -1 (H2) | -2 (H2) | -2L (H2) |
| Temperature Grade | Industrial (-40 to +100 °C) | Industrial (-40 to +100 °C) | Industrial (-40 to +100 °C) | Commercial (0 to +100 °C) | Commercial (0 to +100 °C) |
| Core Voltage | 0.87-0.93 V | 0.87-0.93 V | 0.87-0.93 V | 0.87-0.93 V | 0.87-0.93 V |
| User I/O | 492 | 492 | 492 | 492 | 492 |
Key Differentiators
- Highest speed grade (-2 H2) in the 10AS066 F34 family (vs 10AS066H2F34I1HG)
- Industrial temperature grade for harsh-environment deployments (vs 10AS066H2F34E2SG)
- Pin-compatible with full 10AS066 F34 family for flexible sourcing (vs 10AS032H4F35I3SG (smaller die))
Design Notes
The 35x35 mm FC-FBGA-1152 package dissipates up to ~30 W in worst-case use (full 660K LE utilization at 1.5 GHz with HPS active). Intel recommends a 12-layer PCB with thermal vias under the central BGA ball array and a heat sink with thermal interface material. At industrial temperature (100 °C junction), implement thermal monitoring via the Arria 10 internal temperature sensor and clock-throttle or shutdown on over-temperature.
Use 1.0 mm ball pitch BGA layout with 0.5 mm pad design per Intel BGA guidelines. Power planes should be placed on layers 2 and 5 (just below and above the signal layer where BGA breakouts exit) to provide low-inductance current return paths. DDR3/DDR4 fly-by routing must follow the JEDEC specification; maximum 5 ps skew tolerance on byte lanes. All transceiver channels require AC-coupling capacitors placed within 1 cm of the package ball.
The HPS reset and configuration pins must be sequenced according to the Arria 10 SoC boot sequence; failure to assert the proper POR sequence can leave the Cortex-A9 in an undefined state. Confirmed JTAG pin assignments (TCK/TMS/TDO/TDI) differ from legacy Cyclone designs - always re-check the F34 pinout file. Multi-voltage rails (0.9 V core, 1.1 V HPS, 1.5 V/1.8 V/2.5 V/3.3 V I/O) require careful power-rail sequencing; missing sequencing causes latch-up.
Decouple the 0.9 V core rail with 0402 ceramic capacitors (10 µF + 100 nF per region) placed within 1 mm of every BGA power/ground ball pair. For receiver (RX) data signals, maintain 100 Ω differential impedance and length-match within 5 mil across the entire pre-emphasis path. Place configuration EPCQ flash close to the FPGA MSEL/ASDATA pins to avoid boot failures.
Compliance Information
RoHS compliance confirmed per Intel/Altera product page; AEC-Q100 not applicable (industrial temperature, not automotive). REACH and halogen-free status not directly stated in available data; consult Intel product declaration for full compliance documentation.
