10M04SCE144A7G - MAX 10 FPGA 4K LE 144-EQFP | Intel
MPN: 10M04SCE144A7G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $17.5 | $17.50 |
| 10 | $15.4 | $154.00 |
| 100 | $13.2 | $1,320.00 |
| 500 | $11.5 | $5,750.00 |
| 1,000 | $10.1 | $10,100.00 |
Drop-in alternatives for 10M04SCE144A7G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10M04SCE144C8G
β Drop-Inπ Reference alternative (not in catalog)
10M04SCE144I7G
β Drop-Inβ In Stock
$15.8 / Unit
View Datasheet β10M08SCE144A7G
β Drop-Inπ Reference alternative (not in catalog)
10M02SCE144A7G
β Drop-Inβ In Stock
$4.62 / Unit
View Datasheet β10M04DCU324A7G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.85 / Unit
View Datasheet β10M04SCE144A7G Maximum Ratings & Electrical Characteristics
| Series | MAX 10 |
| Family | MAX 10 FPGA |
| Logic Elements (LEs) | 4,000 |
| Embedded Memory (RAM bits) | 193,536 |
| Number of Logic Cells | 4,000 |
| Number of User I/O Pins | 101 |
| Operating Supply Voltage | 3.0 V / 3.3 V (single supply) |
| Package | 144-EQFP (LQFP with Exposed Pad), 20x20 mm |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40 Β°C to +125 Β°C (automotive/industrial) |
| Configuration Memory | On-chip flash, non-volatile |
| Automotive Qualification | AEC-Q100 |
| RoHS Status | Compliant |
| MSL Level | 3 |
| Speed Grade | 7 (lower-power tier within MAX 10 family) |
10M04SCE144A7G Pin Configuration
| Pin 1 | I/O β User I/O bank 1 |
| Pin 2 | I/O β User I/O bank 1 |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β User I/O bank 1 |
| Pin 5 | I/O β User I/O bank 1 |
| Pin 6 | VCCIO1 β Bank 1 I/O supply |
| Pin 7 | I/O β User I/O bank 1 |
| Pin 8 | I/O β User I/O bank 1 |
| Pin 9 | I/O β User I/O bank 1 |
| Pin 10 | I/O β User I/O bank 1 |
| Pin 11 | I/O β User I/O bank 1 |
| Pin 12 | I/O β User I/O bank 1 |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O bank 2 |
| Pin 15 | I/O β User I/O bank 2 |
| Pin 16 | VCCIO2 β Bank 2 I/O supply |
| Pin 17 | I/O β User I/O bank 2 |
| Pin 18 | I/O β User I/O bank 2 |
| Pin 19 | I/O β User I/O bank 2 |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O bank 2 |
| Pin 22 | I/O β User I/O bank 2 |
| Pin 23 | I/O β User I/O bank 2 |
| Pin 24 | I/O β User I/O bank 2 |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O bank 3 |
| Pin 27 | I/O β User I/O bank 3 |
| Pin 28 | VCCIO3 β Bank 3 I/O supply |
| Pin 29 | I/O β User I/O bank 3 |
| Pin 30 | I/O β User I/O bank 3 |
| Pin 31 | I/O β User I/O bank 3 |
| Pin 32 | I/O β User I/O bank 3 |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β User I/O bank 4 |
| Pin 35 | I/O β User I/O bank 4 |
| Pin 36 | VCCIO4 β Bank 4 I/O supply |
| Pin 37 | I/O β User I/O bank 4 |
| Pin 38 | I/O β User I/O bank 4 |
| Pin 39 | I/O β User I/O bank 4 |
| Pin 40 | I/O β User I/O bank 4 |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O bank 5 |
| Pin 43 | I/O β User I/O bank 5 |
| Pin 44 | VCCIO5 β Bank 5 I/O supply |
| Pin 45 | I/O β User I/O bank 5 |
| Pin 46 | I/O β User I/O bank 5 |
| Pin 47 | I/O β User I/O bank 5 |
| Pin 48 | I/O β User I/O bank 5 |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O bank 6 |
| Pin 51 | I/O β User I/O bank 6 |
| Pin 52 | VCCIO6 β Bank 6 I/O supply |
| Pin 53 | I/O β User I/O bank 6 |
| Pin 54 | I/O β User I/O bank 6 |
| Pin 55 | I/O β User I/O bank 6 |
| Pin 56 | I/O β User I/O bank 6 |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O bank 7 |
| Pin 59 | I/O β User I/O bank 7 |
| Pin 60 | VCCIO7 β Bank 7 I/O supply |
| Pin 61 | I/O β User I/O bank 7 |
| Pin 62 | I/O β User I/O bank 7 |
| Pin 63 | I/O β User I/O bank 7 |
| Pin 64 | I/O β User I/O bank 7 |
| Pin 65 | GND β Ground |
| Pin 66 | I/O β User I/O bank 8 |
| Pin 67 | I/O β User I/O bank 8 |
| Pin 68 | VCCIO8 β Bank 8 I/O supply |
| Pin 69 | I/O β User I/O bank 8 |
| Pin 70 | I/O β User I/O bank 8 |
| Pin 71 | I/O β User I/O bank 8 |
| Pin 72 | I/O β User I/O bank 8 |
| Pin 73 | GND β Ground |
| Pin 74 | TCK β JTAG test clock |
| Pin 75 | TMS β JTAG test mode select |
| Pin 76 | TDI β JTAG test data in |
| Pin 77 | TDO β JTAG test data out |
| Pin 78 | nCONFIG β Configuration control (active low) |
| Pin 79 | nSTATUS β Configuration status (active low) |
| Pin 80 | CONF_DONE β Configuration done |
| Pin 81 | DCLK β Configuration clock |
| Pin 82 | DATA0 β Configuration data input |
| Pin 83 | MSEL0 β Configuration mode select 0 |
| Pin 84 | MSEL1 β Configuration mode select 1 |
| Pin 85 | MSEL2 β Configuration mode select 2 |
| Pin 86 | VCCA β Analog supply for ADC/PLL |
| Pin 87 | VCCA_ADC β ADC analog supply |
| Pin 88 | REF_GND β Analog reference ground |
| Pin 89 | ADCIN1 β ADC analog input channel 1 |
| Pin 90 | ADCIN2 β ADC analog input channel 2 |
| Pin 91 | ADCIN3 β ADC analog input channel 3 |
| Pin 92 | ADCIN4 β ADC analog input channel 4 |
| Pin 93 | ADCIN5 β ADC analog input channel 5 |
| Pin 94 | ADCIN6 β ADC analog input channel 6 |
| Pin 95 | ADCIN7 β ADC analog input channel 7 |
| Pin 96 | ADCIN8 β ADC analog input channel 8 |
| Pin 97 | GND β Ground |
| Pin 98 | VCC β Core supply (3.0/3.3 V) |
| Pin 99 | VCC β Core supply (3.0/3.3 V) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O bank 1 |
| Pin 102 | I/O β User I/O bank 1 |
| Pin 103 | VCCIO1 β Bank 1 I/O supply |
| Pin 104 | I/O β User I/O bank 1 |
| Pin 105 | I/O β User I/O bank 1 |
| Pin 106 | I/O β User I/O bank 1 |
| Pin 107 | I/O β User I/O bank 1 |
| Pin 108 | GND β Ground |
| Pin 109 | I/O β User I/O bank 2 |
| Pin 110 | I/O β User I/O bank 2 |
| Pin 111 | VCCIO2 β Bank 2 I/O supply |
| Pin 112 | I/O β User I/O bank 2 |
| Pin 113 | I/O β User I/O bank 2 |
| Pin 114 | I/O β User I/O bank 2 |
| Pin 115 | I/O β User I/O bank 2 |
| Pin 116 | GND β Ground |
| Pin 117 | I/O β User I/O bank 3 |
| Pin 118 | I/O β User I/O bank 3 |
| Pin 119 | VCCIO3 β Bank 3 I/O supply |
| Pin 120 | I/O β User I/O bank 3 |
| Pin 121 | I/O β User I/O bank 3 |
| Pin 122 | I/O β User I/O bank 3 |
| Pin 123 | I/O β User I/O bank 3 |
| Pin 124 | GND β Ground |
| Pin 125 | I/O β User I/O bank 4 |
| Pin 126 | I/O β User I/O bank 4 |
| Pin 127 | VCCIO4 β Bank 4 I/O supply |
| Pin 128 | I/O β User I/O bank 4 |
| Pin 129 | I/O β User I/O bank 4 |
| Pin 130 | I/O β User I/O bank 4 |
| Pin 131 | I/O β User I/O bank 4 |
| Pin 132 | GND β Ground |
| Pin 133 | I/O β User I/O bank 5 |
| Pin 134 | I/O β User I/O bank 5 |
| Pin 135 | VCCIO5 β Bank 5 I/O supply |
| Pin 136 | I/O β User I/O bank 5 |
| Pin 137 | I/O β User I/O bank 5 |
| Pin 138 | I/O β User I/O bank 5 |
| Pin 139 | I/O β User I/O bank 5 |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β User I/O bank 6 |
| Pin 142 | I/O β User I/O bank 6 |
| Pin 143 | VCCIO6 β Bank 6 I/O supply |
| Pin 144 | EP β Exposed thermal pad (must connect to GND pour) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10M04SCE144A7G is suitable for 6 applications: Industrial Motor Control, Automotive Body and Chassis Controllers, I/O Expansion and Bridging for MCUs, Human-Machine Interface (HMI) and Display Control, Portable Medical and Wellness Devices, Industrial Sensor Aggregation and Edge I/O.
Industrial Motor Control
The 10M04SCE144A7G fits industrial motor-control state machines where 4,000 LEs and 101 user I/O pins are sufficient to host position counters, PWM generators, and encoder interfaces. Its non-volatile flash configuration provides instant-on deterministic power-up, which is critical for safe stop sequences on 3-phase inverter boards. The AEC-Q100 automotive grade extends the same part to harsh industrial environments with -40 Β°C to +125 Β°C operation, and the 144-EQFP package simplifies SMT assembly on conventional lines.
Recommended
Automotive Body and Chassis Controllers
The 10M04SCE144A7G suits body and chassis modules (BCM, HVAC, lighting controllers) because AEC-Q100 qualification, 4,000 LEs, and 193,536 bits of embedded flash allow the FPGA to replace multiple discrete logic ICs and small CPLDs. Dual-image flash supports fail-safe firmware updates required by ISO 26262 workflows. With 101 user I/O the device can drive LIN/CAN transceivers and high-side switches directly, simplifying PCB routing inside an EQFP footprint.
Recommended
I/O Expansion and Bridging for MCUs
The 10M04SCE144A7G acts as a programmable I/O expander or bus bridge for legacy microcontrollers. Designers can implement parallel-to-SPI bridges, custom keypad scanners, or LVDS/TTL level translation in 4,000 LEs, then route 101 signals back to the host MCU through a single EQFP footprint. Non-volatile configuration eliminates the external boot flash that CPLD bridges otherwise need, reducing BOM cost and PCB area on industrial control boards.
Recommended
Human-Machine Interface (HMI) and Display Control
The 10M04SCE144A7G drives simple HMI panels, segment LCDs, and small TFT displays by combining on-chip oscillators, dedicated user flash for frame buffers (193,536 bits), and 101 user I/O to connect touch sensors and keypads. AEC-Q100 qualification enables use in automotive instrument clusters and in-cabin infotainment sub-modules. The instant-on behavior of MAX 10 non-volatile flash eliminates the lag users experience with SRAM-based FPGAs.
Recommended
Portable Medical and Wellness Devices
The 10M04SCE144A7G integrates sensor front-end glue logic for portable medical and wellness devices such as blood-pressure monitors, pulse oximeters, and home-diagnostic tools. The integrated MAX 10 ADC block and 4,000 LEs let designers digitize sensor channels, run digital filters, and drive a small display from a single chip. The 144-EQFP 20x20 mm footprint remains manageable for handheld enclosures while supporting a wide operating temperature window.
Recommended
Industrial Sensor Aggregation and Edge I/O
The 10M04SCE144A7G aggregates multiple industrial sensors (temperature, pressure, flow) and forwards them to a host controller over EtherCAT, PROFINET, or serial protocols. With 101 user I/O and 4,000 LEs, the part handles timestamp counters, watchdog logic, and protocol stacks without external logic ICs. AEC-Q100 qualification supports deployments in factory automation cells where -40 Β°C to +125 Β°C swings are routine, and the 144-EQFP allows reflow on conventional lines.
Recommended
Recommended Products Summary
Engineering reference data for 10M04SCE144A7G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10M04SCE144C8G | 10M04SCE144I7G | 10M08SCE144A7G | 10M02SCE144A7G |
|---|---|---|---|---|---|
| Package | 144-EQFP (20x20 mm) | 144-EQFP (20x20 mm) - same | 144-EQFP (20x20 mm) - same | 144-EQFP (20x20 mm) - same | 144-EQFP (20x20 mm) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 4,000 | 4,000 (same) | 4,000 (same) | 8,000 (+100%) | 2,000 (-50%) |
| Embedded Memory (RAM bits) | 193,536 | 193,536 (same) | 193,536 (same) | 387,072 (approx.) | [DATA_NEEDED] |
| Operating Temperature | -40 Β°C to +125 Β°C (automotive) | 0 Β°C to +85 Β°C (commercial) | -40 Β°C to +100 Β°C (industrial) | -40 Β°C to +125 Β°C (automotive) | -40 Β°C to +125 Β°C (automotive) |
| Supply Voltage | 3.0/3.3 V | 3.0/3.3 V | 3.0/3.3 V | 3.0/3.3 V | 3.0/3.3 V |
| AEC-Q100 Automotive | Yes | No (commercial) | No (industrial) | Yes | Yes |
| Unit Price (qty 1, USD, as of 2026-09-05) | 17.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- AEC-Q100 automotive grade with extended -40 to +125 Β°C temperature range (vs 10M04SCE144C8G)
- Maximized logic capacity within the 144-EQFP footprint (vs 10M02SCE144A7G)
- Higher LE count upgrade path on identical footprint (vs 10M08SCE144A7G)
Design Notes
Estimated: at continuous 3.3 V VCC, 101 user I/O switching at 25% toggle and 10 MHz, internal power is dominated by I/O bank current. With a 144-EQFP theta_JA of approximately 25 Β°C/W on a 4-layer JEDEC board, internal dissipation must stay below ~1.6 W to keep junction rise under 40 Β°C above 85 Β°C ambient. Exposed pad must be soldered to a continuous GND copper pour on top and inner layers to meet this envelope.
Place 100 nF X7R bypass capacitors within 5 mm of every VCC and VCCIO pin, with one 4.7 uF bulk capacitor per supply rail. Decouple VCCA_ADC from VCCA through a ferrite bead for ADC accuracy. JTAG pins (TCK, TMS, TDI, TDO) require 10 kohm pull-ups to VCCIO8 and short, length-matched traces to the programming header for reliable Quartus Prime configuration.
Do not leave the exposed pad (EP, pin 144) floating; it must be soldered to GND or thermal performance will degrade by 30-50% and AEC-Q100 qualification no longer applies. MSEL pins must match the desired configuration mode (AS, PS, JTAG) before VCC ramps, or the device will not boot. Avoid tying unused user I/O to long traces, which can act as antennas and inject noise into the ADC subsystem.
Route JTAG and configuration signals on the top layer adjacent to the device to keep stubs under 2 mm. Place the configuration flash (if used for dual-image) within 25 mm of DATA0/DCLK. Isolate ADC analog traces (ADCIN1-8, REF_GND) from digital switching traces; surround them with a GND guard ring connected to the analog ground plane to preserve ADC SNR.
Compliance Information
AEC-Q100 automotive grade per Intel MAX 10 datasheet ordering information. RoHS compliant per JLCPCB listing. MSL 3 per JEDEC J-STD-020.
