BSZ096N10LS5ATMA1 - 100V 9.6mΩ OptiMOS 5 N-Channel MOSFET | Infineon
MPN: BSZ096N10LS5ATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.15 | $2.15 |
| 10 | $1.93 | $19.30 |
| 100 | $1.62 | $162.00 |
| 500 | $1.34 | $670.00 |
| 1,000 | $1.12 | $1,120.00 |
| 5,000 | $0.94 | $4,700.00 |
Drop-in alternatives for BSZ096N10LS5ATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
BSZ0901NSATMA1
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BSC094N06LS5ATMA1
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View Datasheet →BSZ110N08NS5ATMA1
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View Datasheet →ISC080N10NM6ATMA1
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View Datasheet →IAUCN10S7N021ATMA1
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$2.05 / Unit
View Datasheet →NTMFS5C612N
✅ Drop-In📋 Reference alternative (not in catalog)
SiRA18DP
✅ Drop-In📋 Reference alternative (not in catalog)
BSZ096N10LS5ATMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Product Family | OptiMOS 5 |
| Polarity | N-Channel |
| Drain-Source Voltage (VDS max) | 100 V |
| Gate-Source Voltage (VGS max) | 20 V (typical) |
| Continuous Drain Current (ID, TC=25 °C) | 40 A |
| Maximum Silicon Drain Current (ID max) | 62 A |
| Pulse Drain Current (ID,pulse) | 160 A |
| On-Resistance RDS(on) max | 9.6 mΩ at VGS=10 V |
| Total Power Dissipation (Ptot, TC=25 °C) | 69 W |
| Gate Threshold Voltage VGS(th) | Logic-level (low single-volt range) |
| Diode Continuous Forward Current (IS) | 40 A (TC=25 °C) |
| Diode Forward Voltage (VSD) | 0.85 V typ, 1.2 V max at IF=20 A |
| Package | PG-TSDSON-8-FL (PQFN 3.3 x 3.3 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -55 °C to +150 °C (junction) |
| Technology | OptiMOS 5 trench MOSFET |
| Gate Drive | Logic-level compatible |
| ESD Protection | Yes (gate-integrated) |
| RoHS Status | Compliant |
| Packaging Code | ATMA1 (tape and reel) |
BSZ096N10LS5ATMA1 Pin Configuration
| Pin 1 | Source — Source terminal (low-side) |
| Pin 2 | Source — Source terminal (low-side) |
| Pin 3 | Source — Source terminal (low-side) |
| Pin 4 | Gate — Gate drive input (logic-level) |
| Pin 5 | Drain — Drain terminal (high-side) |
| Pin 6 | Drain — Drain terminal (high-side) |
| Pin 7 | Drain — Drain terminal (high-side) |
| Pin 8 | Source — Source terminal (low-side) |
Safe Operating Area (DC, TC=25 °C)
Typical Applications
BSZ096N10LS5ATMA1 is suitable for 7 applications: Synchronous Rectification in 48 V Telecom DC-DC Converters, Hot-Swap and OR-ing in 48 V Power Distribution, Motor Drive Half-Bridge in Industrial Automation, High-Side Load Switch in USB-PD Adapters, Wireless Charging Power Stage, Telecom Adapter and SMPS Primary-Side Switch, Battery Management and Protection in Power Tools.
Synchronous Rectification in 48 V Telecom DC-DC Converters
The BSZ096N10LS5ATMA1 is well-suited as a synchronous rectifier in 48 V telecom bus converters where 100 V VDS rating easily absorbs worst-case transient spikes (typically 80 V) and the 9.6 mΩ RDS(on) minimises conduction loss at high current. Its OptiMOS 5 trench technology gives low Qg and Qoss, reducing switching loss at the 100-300 kHz switching frequencies typical of intermediate-bus converters feeding 12 V POL stages. The logic-level gate drive allows direct control from a PWM controller IC without an external gate-driver supply, simplifying the BOM. In a typical 48 V-to-12 V buck, two BSZ096N10LS5ATMA1 parts in a half-bridge can deliver >30 A with >97% efficiency. The PG-TSDSON-8-FL package's central thermal pad, soldered to a 1 oz copper pour with thermal vias, keeps junction temperature within safe limits at full load. Designers should still derate against ambient and consider synchronous-rectifier dead-time to limit body-diode conduction.
Recommended
Hot-Swap and OR-ing in 48 V Power Distribution
Hot-swap and OR-ing controllers in 48 V distribution rails require MOSFETs that combine high VDS margin, low RDS(on) for minimal steady-state loss, and controlled turn-on behaviour for inrush limiting. The BSZ096N10LS5ATMA1's 100 V VDS rating comfortably exceeds the 48 V rail plus transient margin, while its 9.6 mΩ RDS(on) at full enhancement keeps OR-ing conduction loss low — for example, dissipating only ~3.6 W at 20 A continuous. The logic-level gate enables direct interface with hot-swap controller ICs (e.g., TPS2490-class devices) without level shifting. The package's central thermal pad supports the high steady-state dissipation that occurs during continuous OR-ing. SOA must be evaluated against the worst-case inrush load profile; the device's large silicon die (ID max 62 A) provides robust linear-mode capability. Designers should size gate resistors to control dv/dt and EMI during hot-plug events.
Recommended
Motor Drive Half-Bridge in Industrial Automation
Industrial motor drives operating from 24-48 V bus rails use N-channel MOSFETs in half-bridge or three-phase inverter topologies. The BSZ096N10LS5ATMA1's 100 V rating provides margin against the back-EMF spikes of brushed DC and small BLDC motors, while its low RDS(on) reduces I²R heating during the high-current conduction phase of PWM modulation. The OptiMOS 5 technology's low Qg simplifies gate-driver design — a single bootstrap gate driver such as the IR2104 class can drive the high-side switch directly. Logic-level gate threshold eliminates the need for a 12 V gate-drive rail, simplifying the auxiliary supply. In a 10 A motor-drive half-bridge, each BSZ096N10LS5ATMA1 dissipates under 1 W, allowing fanless PCB designs. PCB layout must minimise high-side-to-low-side loop inductance to limit drain-voltage ringing above 100 V.
Recommended
High-Side Load Switch in USB-PD Adapters
USB-PD adapters delivering 100 W or more must switch 20 V output rails under load, with the protection MOSFET carrying continuous load current and dissipating power proportional to RDS(on). The BSZ096N10LS5ATMA1's 100 V VDS rating covers USB-PD's 20-28 V output range plus inductive transients, and its 9.6 mΩ RDS(on) keeps conduction loss to roughly 0.4 W at 5 A — well within adapter thermal budgets. The logic-level gate allows direct control from the PD controller's GPIO without a charge pump. In a typical 65 W adapter, using BSZ096N10LS5ATMA1 as the output load switch reduces adapter surface temperature by 5-10 °C versus a higher-RDS(on) part, enabling thinner enclosures. The PQFN 3.3 x 3.3 footprint occupies minimal PCB area, freeing space for magnetics and bulk capacitors.
Recommended
Wireless Charging Power Stage
Wireless-charging transmitter power stages operate as resonant half-bridges or full-bridges driving the LC tank at 100-200 kHz. The BSZ096N10LS5ATMA1 is highlighted by Infineon as a recommended OptiMOS 5 device for wireless charging due to its combination of low RDS(on), low Qgd/Qgs ratio, and small package. The PQFN 3.3 x 3.3 footprint allows placement adjacent to the resonant coil, minimising parasitic loop inductance that would otherwise ring the drain voltage. Logic-level gate drive simplifies interface with wireless-charging transmitter controllers. In a Qi-class 15 W transmitter, using BSZ096N10LS5ATMA1 in the full-bridge delivers >95% efficiency at typical coupling distances. Designers should size gate resistors to control turn-on speed and EMI while staying within the 100 V VDS envelope during tank resonance peaks.
Recommended
Telecom Adapter and SMPS Primary-Side Switch
AC-DC adapters for telecom equipment (typically 48 V output at 100-200 W) use the BSZ096N10LS5ATMA1 as the primary-side switch in flyback or active-clamp topologies operating from a 400 V PFC bus. While the device's 100 V VDS is well below the 400 V bus, it is widely used in the secondary-side synchronous rectification stage of telecom adapters where 100 V margin comfortably covers the 48 V output plus reflective voltage spikes from the transformer leakage inductance. Its 9.6 mΩ RDS(on) keeps synchronous-rectifier conduction loss below 1 W at 15 A, allowing adapter designs to meet 80+ Titanium efficiency targets. The PG-TSDSON-8-FL package's central thermal pad interfaces directly with the adapter's inner copper plane, avoiding the need for an external heatsink. Designers must observe the diode forward voltage (0.85 V typ, 1.2 V max) when sizing dead-time to limit body-diode conduction.
Recommended
Battery Management and Protection in Power Tools
Cordless power tools running on 5S-10S Li-ion packs (18-36 V nominal) require low-side protection MOSFETs with very low RDS(on) to minimise voltage drop during high discharge currents (up to 30 A continuous, 100 A pulse). The BSZ096N10LS5ATMA1's 100 V VDS rating provides margin above the 42 V maximum charge voltage of a 10S pack, and its 9.6 mΩ RDS(on) keeps discharge path voltage drop under 0.3 V at 30 A. The logic-level gate enables direct interface with battery-management ICs operating from the pack voltage. The PQFN 3.3 x 3.3 footprint allows a compact battery pack PCB. The device's robust SOA (62 A silicon-limited ID max) handles the high transient currents of motor startup. Designers should parallel two BSZ096N10LS5ATMA1 parts for very-high-current tools, halving the effective RDS(on) and improving thermal distribution.
Recommended
Recommended Products Summary
Engineering reference data for BSZ096N10LS5ATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | BSZ0901NSATMA1 | BSC094N06LS5ATMA1 | BSZ110N08NS5ATMA1 | ISC080N10NM6ATMA1 | NTMFS5C612N | SiRA18DP |
|---|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | onsemi | Vishay Intertechnology |
| Package | PQFN 3.3 x 3.3 (TSDSON-8-FL) | PQFN 3.3 x 3.3 (TSDSON-8-FL) | PQFN 3.3 x 3.3 (TSDSON-8-FL) | PQFN 3.3 x 3.3 (TSDSON-8-FL) | PQFN 3.3 x 3.3 (TSDSON-8-FL) | PQFN 3.3 x 3.3 (u8FL) | PQFN 3.3 x 3.3 (PowerPAK 1212) |
| VDS max (V) | 100 | 100 | 60 | 80 | 100 | 100 | 100 |
| RDS(on) max at 10 V (mΩ) | 9.6 | ≈6 | ≈9.4 (at VGS=10 V) | ≈11 | ≈8 | ≈9.8 | ≈10 |
| Continuous ID at TC=25 °C (A) | 40 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Technology | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 6 | onsemi Trench | Vishay TrenchFET |
| Gate Drive | Logic-level | Logic-level | Logic-level | Logic-level | Logic-level | Logic-level | Logic-level |
| RoHS / Lead-Free | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Typical Application Fit | Sync rect, OR-ing, motor drive | Higher-current sync rect | Sub-60 V buck stages | Cost-optimised 80 V apps | Higher-frequency upgrade | Cross-brand sync rect | Cross-brand OR-ing |
Key Differentiators
- Industry-leading 9.6 mΩ RDS(on) max at 100 V in PQFN 3.3 x 3.3 (vs BSZ110N08NS5ATMA1)
- Higher VDS rating with the same OptiMOS 5 platform (vs BSC094N06LS5ATMA1)
- Logic-level gate drive simplifies BOM (vs NTMFS5C612N (onsemi))
- Central thermal pad supports higher continuous current (vs SiRA18DP (Vishay PowerPAK 1212))
- Established OptiMOS 5 supply chain with broad Infineon cross-reference (vs Newer OptiMOS 6 ISC080N10NM6ATMA1)
Design Notes
Estimated: at continuous drain current of 20 A and RDS(on)=9.6 mΩ, conduction loss is approximately I²·R = 20² × 0.0096 = 3.84 W. The PG-TSDSON-8-FL package dissipates this through the central thermal pad into the PCB copper pour; thermal resistance to ambient is highly dependent on copper area and thermal vias. With a 1 oz copper pour of 25 x 25 mm and 0.3 mm thermal vias, theta_JA is typically 30-40 °C/W, giving a junction-temperature rise of 115-150 °C above ambient. Derate current to keep Tj below 125 °C for reliable long-term operation, or parallel two BSZ096N10LS5ATMA1 parts to halve effective RDS(on) and improve thermal distribution.
The PG-TSDSON-8-FL package central thermal pad MUST be soldered to a PCB land pattern matching the datasheet's recommended footprint, with an array of 0.3 mm thermal vias connecting to inner copper planes to carry heat away from the die. The gate pin (pin 4) should be routed away from the drain switching node to minimise dv/dt-induced gate coupling. Place a 100 nF ceramic bypass capacitor close to the gate-driver supply pin if an external gate driver is used. For half-bridge layouts, minimise the high-side-to-low-side source-inductance loop to limit drain-voltage ringing and overshoot above the 100 V VDS rating — keep the high-side drain copper and low-side source copper on adjacent layers with minimal loop area.
Estimated: switching loss at 200 kHz with VDS=48 V and ID=10 A is approximately 0.5 × VDS × ID × (trise+tfall) × fsw. With OptiMOS 5 typical rise/fall times of 5-10 ns, switching loss is on the order of 2-4 W — comparable to conduction loss at this operating point. To minimise switching loss, size the gate resistor for a turn-on time of 10-20 ns and ensure the gate-driver has sufficient peak current capability (>2 A) to charge/discharge the gate quickly. Snubber circuits or RC dampers across the drain-source may be required if drain-voltage ringing exceeds 90 V peak.
Do not exceed the 100 V VDS rating under any operating condition — inductive load switching can produce voltage spikes well above the bus rail. Verify that the chosen gate-drive voltage does not exceed the VGS maximum rating (typically ±20 V); exceeding VGS even briefly can rupture the gate oxide. The body diode's reverse recovery charge (Qrr) is non-zero, so for hard-switched bridge topologies, add sufficient dead-time (50-100 ns) and consider an external Schottky diode if reverse-recovery losses are significant. Finally, confirm that the ATMA1 tape-and-reel packaging code is compatible with the PCB assembly line's pick-and-place feeders.
The high dv/dt of the drain node during switching can inject noise into adjacent traces via capacitive coupling — keep sensitive analog signal traces and the gate-drive trace routed away from the drain copper pour. For motor-drive and OR-ing applications, place a small RC snubber (10-100 Ω, 1-10 nF) across the drain-source to damp high-frequency ringing. Gate-source pull-down resistor (10-100 kΩ) prevents accidental turn-on from leakage currents during PCB handling or when the gate driver is in high-impedance state. For very high-frequency switching (>500 kHz), consider adding a small ferrite bead in series with the gate to suppress parasitic oscillations.
Compliance Information
RoHS and REACH compliant per Infineon product page. Standard commercial-grade part (not AEC-Q100 qualified); for automotive applications refer to Infineon's automotive-grade OptiMOS 5 portfolio. ATMA1 packaging code denotes lead-free tape and reel.
