EP1M120B484C5 - Mercury FPGA, 120K Gates, BGA-484 | Intel / Altera
MPN: EP1M120B484C5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88.5 | $885.00 |
| 100 | $78 | $7,800.00 |
| 250 | $72 | $18,000.00 |
| 500 | $65 | $32,500.00 |
Drop-in alternatives for EP1M120B484C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1M120B484C5 Maximum Ratings & Electrical Characteristics
| Family | Mercury (EP1M) |
| Logic Elements | 4,800 |
| Typical Gates | 120,000 |
| Maximum User I/O | 303 |
| Package | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) |
| Operating Temperature | 0C to +85C (commercial) |
| Speed Grade | 5 (slowest) |
| Core Voltage | 1.8 V |
| Process Technology | 0.18 um CMOS |
| PLLs | 4 |
| Embedded RAM Bits | 49,152 |
| True LVDS Channels | Up to 34 pairs |
| Maximum LVDS Data Rate | 840 Mbps per channel |
| Configuration Scheme | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG |
| Peak Reflow Temperature | 220 C |
| Lead-Free / RoHS | SnPb ball finish (non-RoHS by default) |
| Multipliers | Embedded in system blocks for DSP |
| Mounting Type | Surface Mount |
EP1M120B484C5 fineline bga-484 (19 mm x 19 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for EP1M120B484C5 (fineline bga-484 (19 mm x 19 mm, 1.0 mm pitch) package) with 48 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1M120B484C5.
Refer to the datasheet for full pin configuration.
Estimated pin count: 48 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1M120B484C5 is suitable for 6 applications: SONET/SDH Framer Card, High-Speed ADC Data Capture, DSP Co-Processor for Baseband, Network Switch Fabric Interface, Industrial Test Instrumentation, Aerospace and Defense Avionics Bus.
SONET/SDH Framer Card
The EP1M120B484C5 fits SONET/SDH framer designs because of its true-LVDS channels at 840 Mbps per pair and its 4 PLLs that synthesize the multiple clock domains required by STS-1/STM-1 payload mapping. Its 4,800 logic elements and 49,152 bits of embedded dual-port RAM provide buffering for payload pointers and overhead bytes without external memory in many line-card designs. The 303 user I/O pins accommodate the 16-bit LVDS framer bus plus overhead serial links and backplane interfaces.
Recommended
High-Speed ADC Data Capture
The EP1M120B484C5 is well matched to 12-14 bit ADC capture boards sampling at 100-200 MSPS, where the LVDS pairs deliver serialized ADC data directly into the embedded system blocks. The 4 PLLs generate per-channel sampling clocks with programmable phase shift, and the dual-port RAM blocks act as deep FIFOs to absorb bus bursts into a downstream processor. Estimated: at 200 MSPS across 8 LVDS pairs (1.6 Gbps aggregate), the FPGA's 4,800 logic elements sustain simple digital down-conversion and triggering.
Recommended
DSP Co-Processor for Baseband
Embedded multiplier blocks in the EP1M120B484C5 support single-cycle MAC operations for FIR filters, correlators, and QAM demodulators, making the device a useful baseband co-processor paired with a host DSP or PowerPC. The 120K-gate capacity allows multi-channel equalization for narrowband radio links, and the LVDS I/O streams digitised IF data from front-end ADCs at line rates up to 840 Mbps. The 4 PLLs provide independent sampling and symbol clocks for synchronous demodulation.
Recommended
Network Switch Fabric Interface
The EP1M120B484C5 sits well between a network switch ASIC and its line cards, handling serial-to-parallel conversion, ingress/egress buffering, and link-layer management. With up to 34 LVDS pairs at 840 Mbps, the device can aggregate multiple gigabit Ethernet or RapidIO channels onto a wider switch fabric bus. The 49,152 bits of embedded RAM serve as packet buffers for cut-through or store-and-forward switching modes.
Recommended
Industrial Test Instrumentation
The EP1M120B484C5's combination of LVDS, multipliers, and 303 user I/O suits multi-channel test instruments such as logic analyzers, protocol testers, and ATE pin electronics. Engineers can route stimulus patterns to dozens of DUT pins while acquiring high-speed response waveforms through the LVDS pairs. Industrial temperature variants (suffix I5) extend operation to -40C to +100C, enabling deployment in factory-floor and outdoor test fixtures.
Recommended
Aerospace and Defense Avionics Bus
The EP1M120B484C5 supports legacy avionics databuses such as MIL-STD-1553 and ARINC 429 bridges, ARINC 664 (AFDX) packetizers, and Fibre Channel recorders where the LVDS pairs map directly to high-speed serial links. Industrial/extended temperature grades and the rugged BGA-484 package are favored for vibration-prone airframes. The Mercury family's long-term support program makes it attractive for avionics platforms with 20-30 year service lifetimes.
Recommended
Recommended Products Summary
Engineering reference data for EP1M120B484C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M120F484C5 | EP1M120F484I5 | EP1M120F484C6 | EP1K100FI484-2 | EP1K100FC484-2 |
|---|---|---|---|---|---|---|
| Package | BGA-484 | BGA-484 - same | BGA-484 - same | BGA-484 - same | BGA-484 - same | BGA-484 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | Mercury (EP1M) | Mercury (EP1M) | Mercury (EP1M) | Mercury (EP1M) | ACEX 1K | ACEX 1K |
| Typical Gates | 120,000 | 120,000 | 120,000 | 120,000 | 100,000 | 100,000 |
| Logic Elements | 4,800 | 4,800 | 4,800 | 4,800 | 4,992 | 4,992 |
| Maximum User I/O | 303 | 303 | 303 | 303 | 333 | 333 |
| Speed Grade | 5 (slowest) | 5 | 5 | 6 | -2 | -2 |
| Embedded Multipliers | Yes (system blocks) | Yes (system blocks) | Yes (system blocks) | Yes (system blocks) | No | No |
| True LVDS | Yes (840 Mbps) | Yes (840 Mbps) | Yes (840 Mbps) | Yes (840 Mbps) | Limited (311 Mbps) | Limited (311 Mbps) |
| Operating Temperature | 0C to +85C | 0C to +85C | -40C to +100C | 0C to +85C | -40C to +100C | 0C to +85C |
Key Differentiators
- Speed grade -5 (slowest) vs faster Mercury siblings (vs EP1M120F484C5)
- Mercury true-LVDS at 840 Mbps vs ACEX 1K limited LVDS (vs EP1K100FI484-2)
- Embedded multipliers for DSP (vs EP1K100FC484-2)
- BGA-484 footprint shared across Mercury family (vs EP1M120F484I5)
Design Notes
Estimated: at typical 1.8 V core and 100 MHz operation with 50% logic utilization, the EP1M120B484C5 dissipates roughly 1.0-1.5 W. The BGA-484 package's small footprint limits convection cooling, so use a 4-layer PCB with an unbroken ground plane directly under the package and stitch the thermal balls (VCCINT GND) to inner planes with 8-12 vias each. For sealed industrial enclosures, consider a small clip-on heatsink or thermal pad interface material.
Use 1.0 mm-pitch BGA fan-out with microvia technology (laser-drilled 0.1 mm vias) on a high-Tg FR-4 or low-loss PCB material. Escape the inner balls on the top layer with dog-bone fan-out, then route signals on inner layers referenced to solid ground/power planes. Maintain 50 ohm single-ended and 100 ohm differential impedance for LVDS pairs; length-match within 150 mil to preserve 840 Mbps signal integrity.
Do not hot-plug the EP1M120B484C5 - always sequence VCCINT (1.8 V) before VCCIO (1.5/1.8/2.5/3.3 V) to prevent I/O latch-up. Configure unused user I/O pins as tri-stated inputs with weak pull-ups via the Quartus II device options. For JTAG programming, ensure TCK has a 1-10 kohm pull-down and TMS has a 1-10 kohm pull-up to avoid spurious configuration during board reset.
Place decoupling capacitors on the bottom side of the BGA directly under adjacent power/ground balls, using 0.1 uF X7R ceramics for high-frequency and 10 uF tantalum or polymer capacitors for bulk. Estimated: target 1 bulk cap per 4 power pins and 1 high-frequency cap per 2 power pins. Keep the PLL analog supply (VCC_PLL) isolated with a ferrite bead and decoupled with 0.1 uF and 10 uF caps for low-jitter operation.
Compliance Information
Mercury family ships with SnPb (tin-lead) BGA balls by default, making standard parts non-RoHS. A Pb-free variant may be available by special order. REACH compliance status inferred from Intel product stewardship disclosures; verify with the manufacturer before EU-market shipment.
