EP20K1000CB652I9 - APEX 20KC FPGA 1M Gates 250MHz | Altera
MPN: EP20K1000CB652I9 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $180 | $180.00 |
| 10 | $162 | $1,620.00 |
| 100 | $145 | $14,500.00 |
| 500 | $128 | $64,000.00 |
| 1,000 | $115 | $115,000.00 |
Drop-in alternatives for EP20K1000CB652I9 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP20K1000CB652I8
β Drop-Inβ In Stock
$218 / Unit
View Datasheet βEP20K1000CB652C9ES
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$99.5 / Unit
View Datasheet βEP20K1000CB652C8ES
β Drop-Inβ In Stock
$220 / Unit
View Datasheet βEP20K1000CB652C7NJ
β Drop-Inβ In Stock
$175 / Unit
View Datasheet βEP20K1000CB652C7ES
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP20K1000CB652I9 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Logic Elements | 38,400 |
| System Gates | 1,000,000 |
| Maximum User I/O | 488 |
| Technology | 0.15 Β΅m CMOS |
| Maximum Frequency | 250 MHz |
| Core Voltage | 1.8 V (nominal, 1.71 V β 1.89 V) |
| Supply Voltage Range | 1.71 V to 1.89 V |
| Package | 652-ball FCBGA / LBGA |
| Ball Pitch | 1.27 mm |
| Terminal Form | Ball |
| Macrocell Output Function | Yes (configurable I/O) |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial grade) |
| Mounting Type | Surface Mount |
| RoHS Status | unknown (legacy product) |
| Lead-Free | unknown |
EP20K1000CB652I9 Pin Configuration
| Pin 1 | VCCIO_1 β I/O bank 1 supply voltage |
| Pin 2 | IO_1A0 β User I/O (bank 1, group A, bit 0) |
| Pin 3 | IO_1A1 β User I/O (bank 1, group A, bit 1) |
| Pin 4 | GND β Ground reference |
| Pin 5 | IO_1A2 β User I/O (bank 1, group A, bit 2) |
| Pin 6 | VCCINT β Core 1.8 V supply voltage |
| Pin 7 | IO_1A3 β User I/O (bank 1, group A, bit 3) |
| Pin 8 | GND β Ground reference |
| Pin 9 | IO_1A4 β User I/O (bank 1, group A, bit 4) |
| Pin 10 | VCCIO_1 β I/O bank 1 supply voltage |
| Pin 11 | IO_1A5 β User I/O (bank 1, group A, bit 5) |
| Pin 12 | MSEL0 β Configuration mode select bit 0 |
| Pin 13 | MSEL1 β Configuration mode select bit 1 |
| Pin 14 | MSEL2 β Configuration mode select bit 2 |
| Pin 15 | nCONFIG β Configuration control (active low) |
| Pin 16 | nSTATUS β Configuration status (active low) |
| Pin 17 | CONFIG_DONE β Configuration complete (active high) |
| Pin 18 | DCLK β Configuration clock |
| Pin 19 | DATA0 β Configuration data input bit 0 |
| Pin 20 | DATA1 β Configuration data input bit 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K1000CB652I9 is suitable for 6 applications: Telecommunications Line-Card Glue Logic, Multi-Channel Serial-Deserializer Bridge, Industrial Motor-Control State Machine, High-Speed Instrumentation Front-End, Multi-Port Network Switch Backplane, Legacy Industrial PLC Controller.
Telecommunications Line-Card Glue Logic
The EP20K1000CB652I9 fits telecommunications line-card glue logic because it provides 1M system gates and 488 user I/Os, sufficient to bridge a network processor (NPU) to multiple PHYs, framers and SERDES devices. Industrial temperature rating (-40 Β°C to +100 Β°C) lets the same part serve outdoor-mounted DSLAM, GPON OLT, and 4G/LTE base-station line cards. The 250 MHz core supports glue-logic state machines running on every line card. Used between an NPU and SFP/SFP+ cages with SSTL2/HSTL I/O; the 652-ball FCBGA provides 488 I/Os but only ~300 are bonded out, leaving headroom for PCB BGA escape routing.
Recommended
Multi-Channel Serial-Deserializer Bridge
The EP20K1000CB652I9 is well suited to multi-channel serializer/deserializer bridging because it has 1M gates and 488 I/Os to interface between high-speed transceivers and parallel backplanes. The 250 MHz core supports 8B/10B encoding, scrambling, and protocol conversion for legacy telecom and storage systems. Industrial temperature grade enables deployment in outside-plant cabinets. The LVDS, LVPECL and HSTL I/O standards support direct connection to 1.25 Gbps SERDES devices. Placed between PHY SERDES and a parallel backplane; supports 4-8 channels of protocol conversion at 250 MHz.
Recommended
Industrial Motor-Control State Machine
The EP20K1000CB652I9 fits industrial motor-control state machines because its 1M gates can host multi-axis field-oriented-control (FOC) loops, encoder interfaces, and safety gating in one device. The 488 I/Os are sufficient for parallel encoder inputs (QEP / SSI / BiSS), PWM outputs to IGBT bridges, and SPI/I2C management of gate drivers. Industrial -40 Β°C to +100 Β°C rating meets IEC 60068-2 cold-start requirements for outdoor drives. The APEX 20KC embedded system blocks (ESBs) provide the dual-port RAM needed for data logging. Used as the central motor controller with 6-axis FOC and 50 kHz PWM loop update; dissipates ~3-5 W at full utilisation.
Recommended
High-Speed Instrumentation Front-End
The EP20K1000CB652I9 supports high-speed instrumentation front-ends because it can capture and process parallel ADC data at sample rates up to 250 MHz while performing real-time DSP. Its 488 I/Os accept wide parallel LVDS buses from multi-channel ADCs, and the embedded system blocks store deep FIFO buffers. The industrial temperature grade supports outdoor / aerospace instrumentation racks. The MultiCore architecture lets designers separate timing-critical logic from bulk DSP. Placed between a 16-bit 200 MSPS ADC and a backplane controller; processes 4 channels in parallel with 1024-tap FIR filters.
Recommended
Multi-Port Network Switch Backplane
The EP20K1000CB652I9 fits multi-port network switch backplane aggregation because it has 488 I/Os and 1M gates to bridge between switch ASICs and backplane SERDES. Industrial temperature rating supports deployment in industrial Ethernet switches and outdoor telecom cabinets. The 250 MHz core allows deep packet inspection and rate-limiting logic. The LVCMOS I/O standards support direct connection to switch ASIC GMII/RGMII interfaces. Placed between a 24-port GbE switch ASIC and a 4-lane XAUI backplane; runs 200 MHz packet-processing pipeline.
Recommended
Legacy Industrial PLC Controller
The EP20K1000CB652I9 is well-suited to legacy PLC controllers because it provides enough logic for complex ladder-logic-to-state-machine translation and motion-control DSP in a single chip. The 488 I/Os support many digital inputs and outputs common in industrial PLC racks, and the industrial temperature rating matches IEC 61131-2 environmental requirements. Many legacy PLC systems were designed around the 20KC family and have validated Quartus MAX+plus II bitstreams that continue to function. Used as the central logic engine in 19-inch rack PLC chassis; dissipates 4-6 W with all I/Os toggling at 100 kHz.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000CB652I9 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000CB652I8 | EP20K1000CB652C9ES | EP20K1000CB652C8ES | EP20K1000CB652C7NJ | EP20K1000CB652C7ES |
|---|---|---|---|---|---|---|
| Package | 652-ball FCBGA / LBGA (1.27 mm pitch) | 652-ball FCBGA / LBGA - same | 652-ball FCBGA / LBGA - same | 652-ball FCBGA / LBGA - same | 652-ball FCBGA / LBGA - same | 652-ball FCBGA / LBGA - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Logic Elements | 38,400 | 38,400 - same | 38,400 - same | 38,400 - same | 38,400 - same | 38,400 - same |
| System Gates | 1,000,000 | 1,000,000 - same | 1,000,000 - same | 1,000,000 - same | 1,000,000 - same | 1,000,000 - same |
| Temperature Grade | Industrial (-40Β°C to +100Β°C) | Industrial (-40Β°C to +100Β°C) - same | Commercial (0Β°C to +85Β°C) | Commercial (0Β°C to +85Β°C) | Commercial (0Β°C to +85Β°C) | Commercial (0Β°C to +85Β°C) |
| Speed Grade | -9 (fastest) | -8 (~10% slower) | -9 (same) | -8 (~10% slower) | -7 (~20% slower) | -7 (~20% slower) |
| Core Voltage | 1.8 V Β±5% | 1.8 V Β±5% - same | 1.8 V Β±5% - same | 1.8 V Β±5% - same | 1.8 V Β±5% - same | 1.8 V Β±5% - same |
| Maximum Frequency | 250 MHz | ~225 MHz | 250 MHz - same | ~225 MHz | ~200 MHz | ~200 MHz |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade (-40Β°C to +100Β°C) (vs EP20K1000CB652C9ES)
- Speed grade -9 (fastest) (vs EP20K1000CB652C7NJ)
- 1M gates / 38,400 logic elements on a single die (vs EP20K1000CB652I8)
Design Notes
The EP20K1000CB652I9 requires two separate supplies: a 1.8 V Β±5% core supply (VCCINT) supplying the logic fabric and ESBs, and one or more VCCIO supplies (typically 2.5 V, 3.3 V, or 1.5 V SSTL) powering the I/O banks. Decouple each supply pin with a 0.1 Β΅F ceramic capacitor placed within 5 mm of the ball, and add a 10 Β΅F bulk tantalum or polymer capacitor per supply rail. Sequence VCCINT before VCCIO if I/O voltages exceed the core voltage, otherwise latch-up risk increases. Estimated core power at 250 MHz with 50% utilisation is approximately 2-3 W.
The 652-ball FCBGA package has a typical ΞΈJA of approximately 8-10 Β°C/W with adequate PCB thermal vias. The APEX 20KC datasheet recommends a 6Γ6 thermal-via array (0.3 mm pitch) directly under the die for industrial applications. Estimated power dissipation of 3-5 W at full I/O toggling produces a 25-50 Β°C junction rise above ambient - manageable but requires thermal vias for reliable industrial-temperature operation. A heatsink is not normally required for the 652-ball FCBGA.
Route all 8 layers of the PCB as stripline / microstrip with continuous ground planes adjacent to each signal layer. Match the 1.27 mm BGA pitch with 0.20 mm trace width and 0.20 mm spacing on inner layers; use 0.15 mm width / 0.15 mm spacing on outer layers for BGA fan-out. Apply via-in-pad with filled-and-capped microvias for the BGA breakout area to keep the fan-out within 4 routing layers. Maintain 100 Ξ© differential impedance for LVDS pairs and 50 Ξ© single-ended for general-purpose I/O.
Configure the EP20K1000CB652I9 using a JTAG chain through the TCK, TMS, TDI, TDO pins, or via a passive serial configuration PROM (EPC-1 or EPC-16). Set MSEL[2:0] pins to select the configuration mode. The CONFIG_DONE pin goes high after successful configuration; nSTATUS pulls low on error. Pull nCONFIG high through a 10 kΞ© resistor to VCCIO_1 and add a reset supervisor to drive nCONFIG low on power-up. Estimated configuration time from a 16-Mbit EPC-16 is approximately 80-120 ms.
Do not mix EP20K1000CB652I9 (industrial) and EP20K1000CB652C9 (commercial) temperature grades on the same board layout - although pin-compatible, they have different thermal derating curves. Always tie unused I/O pins to a defined logic level (not floating) per the APEX 20KC datasheet. Use Quartus MAX+plus II version 10.2 or earlier; newer Quartus Prime versions no longer support the APEX 20KC family and will reject design files silently.
Compliance Information
The EP20K1000CB652I9 is a legacy Altera product (0.15 Β΅m process, circa 2001) and pre-dates RoHS enforcement; RoHS compliance status is not stated in the verified web data. Altera / Intel's published conflict-minerals compliance statement covers all FPGA families including the APEX 20KC. AEC-Q100 is not applicable because this is a programmable logic device, not an automotive-qualified IC.
