EPM7256AETC144-5N - 256-Macrocell MAX 7000A CPLD | Altera | TQFP-144
MPN: EPM7256AETC144-5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM7256AETC144-5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM7256AETC144-5N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Logic Family | CMOS |
| Usable Gates | 5,000 |
| Macro Cells | 256 |
| Logic Blocks | 16 |
| User I/Os (Mouser listing) | 36 |
| User I/Os (DigChip listing) | 84 |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns |
| Maximum Internal Frequency | 227.3 MHz |
| Counter Speed | 172.4 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| Program Memory Type | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG) |
| Package | TQFP-144 (Plastic Thin Quad Flat Pack) |
| Lead-Free / RoHS | Yes (N suffix) |
| Speed Grade | -5 |
EPM7256AETC144-5N Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | GCLK1 — Global clock input 1 |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | VCCINT — Core supply voltage (3.3 V) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | GND — Ground |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 2) |
| Pin 14 | I/O — User I/O pin (bank 2) |
| Pin 15 | GCLK2 — Global clock input 2 |
| Pin 16 | I/O — User I/O pin (bank 2) |
| Pin 17 | I/O — User I/O pin (bank 2) |
| Pin 18 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 19 | I/O — User I/O pin (bank 2) |
| Pin 20 | I/O — User I/O pin (bank 2) |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | GND — Ground |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | OE1 — Global output enable 1 (active low) |
| Pin 28 | I/O — User I/O pin (bank 2) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | VCCINT — Core supply voltage (3.3 V) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | GCLK3 — Global clock input 3 |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 3) |
| Pin 35 | I/O — User I/O pin (bank 3) |
| Pin 36 | I/O — User I/O pin (bank 3) |
| Pin 37 | GND — Ground |
| Pin 38 | I/O — User I/O pin (bank 3) |
| Pin 39 | I/O — User I/O pin (bank 3) |
| Pin 40 | I/O — User I/O pin (bank 3) |
| Pin 41 | I/O — User I/O pin (bank 3) |
| Pin 42 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 43 | I/O — User I/O pin (bank 3) |
| Pin 44 | GCLK4 — Global clock input 4 |
| Pin 45 | I/O — User I/O pin (bank 3) |
| Pin 46 | I/O — User I/O pin (bank 3) |
| Pin 47 | I/O — User I/O pin (bank 3) |
| Pin 48 | I/O — User I/O pin (bank 3) |
| Pin 49 | OE2 — Global output enable 2 (active low) |
| Pin 50 | I/O — User I/O pin (bank 3) |
| Pin 51 | I/O — User I/O pin (bank 3) |
| Pin 52 | VCCINT — Core supply voltage (3.3 V) |
| Pin 53 | I/O — User I/O pin (bank 3) |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | I/O — User I/O pin (bank 4) |
| Pin 56 | I/O — User I/O pin (bank 4) |
| Pin 57 | GND — Ground |
| Pin 58 | I/O — User I/O pin (bank 4) |
| Pin 59 | I/O — User I/O pin (bank 4) |
| Pin 60 | I/O — User I/O pin (bank 4) |
| Pin 61 | I/O — User I/O pin (bank 4) |
| Pin 62 | I/O — User I/O pin (bank 4) |
| Pin 63 | I/O — User I/O pin (bank 4) |
| Pin 64 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 65 | I/O — User I/O pin (bank 4) |
| Pin 66 | I/O — User I/O pin (bank 4) |
| Pin 67 | I/O — User I/O pin (bank 4) |
| Pin 68 | I/O — User I/O pin (bank 4) |
| Pin 69 | I/O — User I/O pin (bank 4) |
| Pin 70 | I/O — User I/O pin (bank 4) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | I/O — User I/O pin (bank 4) |
| Pin 74 | TDI — JTAG Test Data In |
| Pin 75 | TMS — JTAG Test Mode Select |
| Pin 76 | TCK — JTAG Test Clock |
| Pin 77 | VCCINT — Core supply voltage (3.3 V) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | I/O — User I/O pin (bank 4) |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | I/O — User I/O pin (bank 4) |
| Pin 82 | I/O — User I/O pin (bank 4) |
| Pin 83 | I/O — User I/O pin (bank 4) |
| Pin 84 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 85 | I/O — User I/O pin (bank 4) |
| Pin 86 | I/O — User I/O pin (bank 4) |
| Pin 87 | I/O — User I/O pin (bank 4) |
| Pin 88 | I/O — User I/O pin (bank 4) |
| Pin 89 | I/O — User I/O pin (bank 4) |
| Pin 90 | I/O — User I/O pin (bank 4) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin (bank 4) |
| Pin 93 | I/O — User I/O pin (bank 4) |
| Pin 94 | TDO — JTAG Test Data Out |
| Pin 95 | I/O — User I/O pin (bank 4) |
| Pin 96 | I/O — User I/O pin (bank 4) |
| Pin 97 | VCCINT — Core supply voltage (3.3 V) |
| Pin 98 | I/O — User I/O pin (bank 4) |
| Pin 99 | I/O — User I/O pin (bank 4) |
| Pin 100 | I/O — User I/O pin (bank 4) |
| Pin 101 | I/O — User I/O pin (bank 4) |
| Pin 102 | I/O — User I/O pin (bank 4) |
| Pin 103 | I/O — User I/O pin (bank 4) |
| Pin 104 | VCCIO1 — I/O bank 1 supply voltage (alternate pin) |
| Pin 105 | I/O — User I/O pin (bank 1) |
| Pin 106 | I/O — User I/O pin (bank 1) |
| Pin 107 | I/O — User I/O pin (bank 1) |
| Pin 108 | I/O — User I/O pin (bank 1) |
| Pin 109 | I/O — User I/O pin (bank 1) |
| Pin 110 | I/O — User I/O pin (bank 1) |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — User I/O pin (bank 1) |
| Pin 113 | I/O — User I/O pin (bank 1) |
| Pin 114 | I/O — User I/O pin (bank 1) |
| Pin 115 | I/O — User I/O pin (bank 1) |
| Pin 116 | I/O — User I/O pin (bank 1) |
| Pin 117 | I/O — User I/O pin (bank 1) |
| Pin 118 | VCCINT — Core supply voltage (3.3 V) |
| Pin 119 | I/O — User I/O pin (bank 1) |
| Pin 120 | I/O — User I/O pin (bank 1) |
| Pin 121 | I/O — User I/O pin (bank 1) |
| Pin 122 | I/O — User I/O pin (bank 1) |
| Pin 123 | I/O — User I/O pin (bank 1) |
| Pin 124 | I/O — User I/O pin (bank 1) |
| Pin 125 | I/O — User I/O pin (bank 1) |
| Pin 126 | VCCIO2 — I/O bank 2 supply voltage (alternate pin) |
| Pin 127 | I/O — User I/O pin (bank 2) |
| Pin 128 | I/O — User I/O pin (bank 2) |
| Pin 129 | I/O — User I/O pin (bank 2) |
| Pin 130 | I/O — User I/O pin (bank 2) |
| Pin 131 | I/O — User I/O pin (bank 2) |
| Pin 132 | GND — Ground |
| Pin 133 | I/O — User I/O pin (bank 2) |
| Pin 134 | I/O — User I/O pin (bank 2) |
| Pin 135 | I/O — User I/O pin (bank 2) |
| Pin 136 | I/O — User I/O pin (bank 2) |
| Pin 137 | I/O — User I/O pin (bank 2) |
| Pin 138 | I/O — User I/O pin (bank 2) |
| Pin 139 | VCCINT — Core supply voltage (3.3 V) |
| Pin 140 | I/O — User I/O pin (bank 2) |
| Pin 141 | I/O — User I/O pin (bank 2) |
| Pin 142 | I/O — User I/O pin (bank 2) |
| Pin 143 | I/O — User I/O pin (bank 2) |
| Pin 144 | I/O — User I/O pin (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256AETC144-5N is suitable for 6 applications: Bus Interface Bridging, Address Decoding and Chip-Select Generation, Industrial Control and Factory Automation, Peripheral I/O Expansion, Legacy Microprocessor System Integration, Test and Measurement Equipment.
Bus Interface Bridging
The EPM7256AETC144-5N's 256 macro cells and 4.5 ns tPD make it ideal for bridging between legacy 8/16-bit microprocessor buses and modern 32-bit peripherals. The deterministic timing of the MAX 7000A architecture, combined with multi-voltage I/O banks (VCCIO at 1.8/2.5/3.3 V), allows direct connection between, for example, an 8051-style 5 V-tolerant interface and a 3.3 V ARM Cortex-M3 bus without external level shifters. With up to 84 user I/Os, the device can fan out address, data, and control signals to multiple peripherals while meeting ISA-style timing budgets. The 4.5 ns propagation delay fits comfortably within a 33 MHz bus cycle.
Recommended
Address Decoding and Chip-Select Generation
The EPM7256AETC144-5N is widely used to generate chip-select signals, address-strobe timing, and bank-switch windows for memory and peripheral arrays. Its 256 macro cells easily handle decoding of a 24-bit address space into 16 or more chip-select outputs, each individually programmable with wait-state insertion. The 4.5 ns tPD ensures clean, glitch-free outputs that meet synchronous memory tCO requirements. Because the MAX 7000A architecture is non-volatile (EEPROM), chip-select logic comes up instantly on power-on with no configuration delay, which is critical in boot-ROM and reset-path designs where the MCU waits for peripherals to be ready.
Recommended
Industrial Control and Factory Automation
The EPM7256AETC144-5N serves as a glue-logic and state-machine controller in industrial PLCs, motor drives, and process-control instruments. Its 256 macro cells can implement multiple parallel state machines (one per axis) plus encoder-interface logic, while the JTAG port allows in-system firmware updates during commissioning. For harsh environments, the industrial-grade variant EPM7256AETI144-7N offers -40C to +85C operation in the same TQFP-144 footprint. The CMOS EEPROM process delivers high noise immunity suitable for 24 V industrial bus environments with proper board-level filtering.
Recommended
Peripheral I/O Expansion
The EPM7256AETC144-5N can be used to expand the limited I/O count of microcontrollers and DSPs by offloading functions like PWM generation, quadrature decoding, and LED multiplexing. Its 16 LABs (logic array blocks) operate in parallel, so 16 independent PWM channels or 16 quadrature decoders can run simultaneously without contention. The MAX 7000A's deterministic 4.5 ns tPD allows tight control-loop timing in motor-control and robotics applications. Multi-voltage I/O banks let the same CPLD interface directly with 1.8 V DSPs and 3.3 V / 5 V sensors without external buffers.
Recommended
Legacy Microprocessor System Integration
Designers maintaining legacy 68k, x86, or MIPS-based systems often reach for the EPM7256AETC144-5N as a drop-in replacement for aging PAL/GAL-based glue logic. With 256 macro cells, a single device can replace an entire board of discrete programmable arrays, reducing component count and improving reliability. The EEPROM programming is one-time programmable (with JTAG re-programmability), avoiding the obsolescence risk of older UV-EPROM parts. The MAX 7000A family has been in continuous production since the late 1990s, ensuring long-term availability for industrial and aerospace programs with 10+ year lifecycles.
Recommended
Test and Measurement Equipment
The EPM7256AETC144-5N is well suited to test-and-measurement front-ends, where its 256 macro cells can implement timing generators, pulse-train controllers, and protocol decoders for instruments such as logic analyzers and bench-top protocol testers. The JTAG-supported boundary-scan (IEEE 1149.1) lets the CPLD assist in board-level interconnect testing, while the deterministic 4.5 ns tPD simplifies generation of precise timing edges. Multi-voltage I/O banks allow direct interfacing with both 1.8 V modern FPGAs and legacy 5 V measurement circuitry on the same board.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256AETC144-5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256AETC144-7N | EPM7256AETC144-10N | EPM7256AETI144-7N | EPM7256AEQC208-5N | EPM7128AETC144-7N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-208 - different | TQFP-144 - same |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000AE | MAX 7000A |
| Macro Cells | 256 | 256 | 256 | 256 | 256 | 128 |
| Speed Grade (tPD) | -5 (4.5 ns) | -7 (6.0 ns) | -10 (10.0 ns) | -7 (6.0 ns) | -5 (4.5 ns) | -7 (7.5 ns) |
| Counter Frequency | 227.3 MHz | 172.4 MHz | 125 MHz | 172.4 MHz | 227.3 MHz | 125 MHz |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | Commercial (0C to +70C) | Commercial | Commercial | Industrial (-40C to +85C) | Commercial | Commercial |
| JTAG / ISP | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Densest MAX 7000A device at -5 speed grade in TQFP-144 (vs EPM7256AETC144-7N)
- 256 macro cells - 2x the logic density (vs EPM7128AETC144-7N)
- Multi-voltage I/O banks for direct mixed-rail interfacing (vs EPM7192EQC160-20)
Design Notes
Each EPM7256AETC144-5N VCCINT pin must be decoupled with a 0.1 microfarad X7R ceramic capacitor placed within 5 mm of the package pin. The MAX 7000A datasheet recommends at least four VCCINT/GND pairs distributed around the TQFP-144 perimeter. Use a power plane for VCCINT (3.3 V) and a separate ground plane, with vias placed every two signal traces to maintain low-inductance return paths.
Route the four global clock inputs (GCLK1 to GCLK4) and JTAG pins (TCK, TMS, TDI, TDO) with controlled impedance and minimal stubs. Avoid routing clock signals adjacent to high-edge-rate I/O to prevent crosstalk. The dedicated OE1 and OE2 pins should be tied to logic low through a 10 kilohm resistor if not used, to prevent floating enable glitches during power-up.
Do not confuse the EPM7256AETC144-5N (commercial temperature, -5 speed grade) with the EPM7256AETI144-7N (industrial temperature, -7 speed grade); they share the TQFP-144 footprint but are NOT timing-identical. Estimated timing margin: the -7 grade is approximately 33% slower than the -5 grade. Always verify your design's worst-case tPD budget against the chosen speed grade before substitution. Also confirm VCCIO bank voltages match the driven peripherals, or use external series resistors for voltage mismatch.
Compliance Information
Lead-free (Pb-free) per the N suffix; RoHS and REACH compliant per Altera/Intel material declarations. AEC-Q100 not applicable for this commercial-grade CPLD. Halogen-free status not explicitly stated in available data - verify with manufacturer for halogen-free applications.
