EPM9560RC340-15 - MAX 9000 CPLD, 560 Macrocells, 15ns | Altera
MPN: EPM9560RC340-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38.5 | $385.00 |
| 100 | $32 | $3,200.00 |
| 500 | $27.5 | $13,750.00 |
| 1,000 | $24 | $24,000.00 |
Drop-in alternatives for EPM9560RC340-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC340-20
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9560RC340-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9560RC304-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.4 / Unit
View Datasheet βEPM9560RC304-20
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
Contact for price
View Datasheet βEPM9560RC304-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$17.6 / Unit
View Datasheet βEPM9560RC340-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) |
| User I/O Pins | 212 |
| Package | 340-RQFP (Reduced Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature (Commercial) | 0C to +70C |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation |
| Boundary Scan | IEEE Std. 1149.1 JTAG |
| Programming Technology | EEPROM (non-volatile, reprogrammable) |
EPM9560RC340-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (LAB signal, function assigned by MAX+PLUS II fitting) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | GND β Ground |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | VCC β 5.0V supply |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | VCC β 5.0V supply |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | VCC β 5.0V supply |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | GND β Ground |
| Pin 29 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 30 | TMS β JTAG Test Mode Select (IEEE 1149.1) |
| Pin 31 | TCK β JTAG Test Clock (IEEE 1149.1) |
| Pin 32 | TDO β JTAG Test Data Out (IEEE 1149.1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC340-15 is suitable for 6 applications: Microprocessor Bus Interface Bridging, High-Density Glue Logic Consolidation, Industrial Control State Machines, Telecommunications Equipment Logic, Replacement of Multiple PAL/GAL Devices, Legacy 5V System Design Support.
Microprocessor Bus Interface Bridging
The EPM9560RC340-15 is well suited to bus-bridging applications where 8-bit, 16-bit, and 32-bit microprocessor buses must be interfaced through custom address decoding and data steering logic. Its 560 macrocells can implement large state machines and combinational glue logic that would otherwise require a half-dozen discrete 22V10 or 16V8 PAL devices, while the 212 user I/Os accommodate the wide parallel buses common in legacy Intel 8086, Motorola 68k, and PowerPC designs. The 15 ns pin-to-pin delay ensures setup/hold timing margins are met at clock rates up to approximately 33 MHz without pipelining, and JTAG-based ISP enables late-stage design changes without reworking the PCB.
Recommended
High-Density Glue Logic Consolidation
Designers commonly use the EPM9560RC340-15 to consolidate dozens of discrete 74LS/74F-series glue-logic functions onto a single programmable device, dramatically simplifying PCB layout and reducing BOM cost. With 560 macrocells and 12,000 usable gates, the part can absorb address decoders, chip-select generators, interrupt arbiters, and reset sequencers that previously occupied four to eight standard logic ICs. The MAX architecture provides deterministic 15 ns propagation delay regardless of the implemented logic, simplifying worst-case timing analysis. EEPROM non-volatility means the design is retained through power cycles without external boot memory, a key advantage over SRAM-based FPGAs.
Recommended
Industrial Control State Machines
Industrial controllers frequently require large Mealy/Moore state machines with dozens of states and complex output sequencing. The EPM9560RC340-15's 560 macrocells support state machines with 64+ states plus parallel output decoding, while its 212 I/Os drive relay banks, sensor inputs, and HMI interfaces without external bus expanders. The 0C to +70C commercial operating range covers most factory-floor enclosure environments, and the 5V supply tolerance handles noisy industrial power rails. JTAG boundary-scan test access simplifies production-board fault diagnosis in mixed-signal industrial control assemblies.
Recommended
Telecommunications Equipment Logic
Legacy telecom infrastructure (T1/E1 framing, ATM segmentation, SONET overhead processors) requires deterministic, low-latency control logic that the EPM9560RC340-15 delivers with its 15 ns tPD specification. The 560-macrocell capacity accommodates HDLC controllers, framer sequencers, and alarm-monitoring state machines within a single device, while 212 I/Os interface to multi-drop backplanes. The 5.0V VCC tolerance aligns with legacy telecom line-card power rails, and JTAG ISP allows field upgrades through maintenance interfaces. For new telecom designs, however, the obsolete lifecycle status of this part makes modernization to MAX V or MAX 10 CPLDs prudent.
Recommended
Replacement of Multiple PAL/GAL Devices
The EPM9560RC340-15 is frequently specified as a one-for-one replacement for designs that grew beyond their original discrete-PAL implementation, where dozens of 16L8, 20V8, and 22V10 PALs filled the BOM. By consolidating 20+ legacy PALs into one 560-macrocell CPLD, designers reduce board area, power consumption, and the obsolescence risk associated with vintage PAL suppliers. The MAX 9000 architecture is JEDEC-compatible at the fuse-map level, easing porting of legacy PAL equations through MAX+PLUS II. With 212 user I/Os, the part can replicate the wiring density of a 20-PAL discrete design on a single chip.
Recommended
Legacy 5V System Design Support
Many aerospace, defense, and industrial systems still operate on 5V power rails that are incompatible with modern 3.3V or 1.8V CPLDs and FPGAs. The EPM9560RC340-15's 4.75V to 5.25V VCC tolerance makes it one of the few high-density programmable logic options still usable on these legacy 5V buses without external level translation. The 340-RQFP package provides robust mechanical and thermal performance for long-lifecycle industrial equipment. Designers maintaining such legacy systems can use this part for incremental upgrades without redesigning the entire 5V power architecture, though new designs should evaluate MAX V 5M240ZT100 or MAX 10 with onboard regulators.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC340-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC340-20 | EPM9560RC340-10 | EPM9560RC304-15 | EPM9560RC304-20 |
|---|---|---|---|---|---|
| Package | 340-RQFP | 340-RQFP - same | 340-RQFP - same | 304-RQFP - same family, different package | 304-RQFP - same family, different package |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 15 ns | 20 ns | 10 ns | 15 ns | 20 ns |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Supply Voltage | 5.0 V (4.75-5.25 V) | 5.0 V (4.75-5.25 V) | 5.0 V (4.75-5.25 V) | 5.0 V (4.75-5.25 V) | 5.0 V (4.75-5.25 V) |
| User I/O Pins | 212 | 212 | 212 | 212 | 212 |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Maximum I/O density in MAX 9000 family (vs EPM9560RC240-15)
- Mid-range speed grade for cost-sensitive designs (vs EPM9560RC340-10)
- Same-package compatibility with -20 and -10 speed grades (vs EPM9560RC340-20)
Design Notes
Estimated: at 5.0V VCC and 560 active macrocells switching at moderate toggle rates, supply current typically stays below 500 mA. Add a 100uF bulk capacitor plus 0.1uF ceramic decoupling per VCC pin (340-RQFP has multiple VCC/GND pairs). Place the bulk capacitor within 25mm of the package and decouple each VCC pin individually to minimize switching noise on the 5V rail.
The 340-RQFP package has a 0.5mm lead pitch and 32mm body size, requiring fine-pitch PCB layout capability. Maintain 50 ohm controlled impedance on JTAG signals (TDI, TMS, TCK, TDO) and route them away from switching I/O lines to prevent programming failures. Provide a JTAG header on the PCB even if not used during production, as it enables boundary-scan testing per IEEE Std. 1149.1 and in-field firmware updates.
The MAX 9000 family is supported only by the legacy MAX+PLUS II toolchain; Intel Quartus Prime does not target these devices. Before starting a new EPM9560RC340-15 design, verify that a working MAX+PLUS II license and installation are available. For new designs, prefer the MAX II, MAX V, or MAX 10 family with Quartus Prime support. Additionally, ensure unused I/O pins are configured as outputs driving low or as inputs with internal pull-ups, never left floating, to prevent shoot-through current.
Compliance Information
Compliance data not explicitly present in verified web data; marked unknown per Data Authenticity Rules. Not AEC-Q100 applicable - this is a commercial/industrial-grade CPLD, not an automotive-qualified part.
