IPD031N03LGATMA1 - 30V 90A OptiMOS 3 N-Channel MOSFET | Infineon
MPN: IPD031N03LGATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.92 | $0.92 |
| 10 | $0.78 | $7.80 |
| 100 | $0.65 | $65.00 |
| 500 | $0.55 | $275.00 |
| 1,000 | $0.48 | $480.00 |
| 3,000 | $0.41 | $1,230.00 |
Drop-in alternatives for IPD031N03LGATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →IPD031N03LGATMA1 Maximum Ratings & Electrical Characteristics
| FET Type | N-Channel |
| Technology | MOSFET (Metal Oxide), OptiMOS 3 |
| Drain-to-Source Voltage (Vdss) | 30 V |
| Continuous Drain Current (Id) @ 25 °C | 90 A (Tc) |
| Power Dissipation (Pd) | 94 W (Tc) |
| RDS(on) Max @ VGS=10V | 3.1 mΩ |
| Drive Voltage (Max RDS(on), Min RDS(on)) | 4.5 V, 10 V |
| Output Charge (Qoss) | Ultra low (per datasheet tagline) |
| Operating Temperature | -55 °C to +175 °C (junction) |
| Package | PG-TO252-3-11 (DPAK-2) |
| Mounting Type | Surface Mount |
| Mounting Tab | Drain (electrically connected) |
| Avalanche Energy Rated | Yes (per OptiMOS 3 datasheet family) |
| RoHS Status | Compliant |
| MSL Level | 1 |
IPD031N03LGATMA1 Pin Configuration
| Pin 1 | Gate — Gate control input; logic-level compatible (4.5 V Vgs for full enhancement) |
| Pin 2 | Drain (Tab) — Drain terminal, electrically bonded to mounting tab for thermal dissipation |
| Pin 3 | Source — Source terminal; return path for gate drive and load current |
Safe Operating Area (SOA) - DC
Typical Applications
IPD031N03LGATMA1 is suitable for 6 applications: Server VRM Synchronous Rectification, Telecom Point-of-Load (POL) DC-DC Converter, Battery Management Load Switch, Hot-Swap / OR-ing Controller Switch, DC Motor Drive (H-Bridge Low-Side), Industrial 24V Bus Solid-State Relay (SSR).
Server VRM Synchronous Rectification
The IPD031N03LGATMA1 is a textbook low-side synchronous rectifier for 12 V-input buck VRMs in server and workstation motherboards. With RDS(on) of 3.1 mΩ at 10 V VGS and 90 A continuous drain current, the part dissipates only ~2.8 W at 30 A load, enabling >97% peak efficiency in multi-phase VR topologies. The OptiMOS 3 trench technology delivers low Qg/Qoss that minimizes dead-time body-diode conduction in 300-500 kHz switching designs. Engineers place this part on the low-side of each phase, paired with a dedicated gate driver and bootstrap circuit for the high-side switch.
Recommended
Telecom Point-of-Load (POL) DC-DC Converter
In 48 V-to-12 V or 12 V-to-1 V POL converters for telecom base stations, the IPD031N03LGATMA1 functions as the primary low-side switch in the synchronous-rectifier pair. Its 30 V Vdss rating suits 12 V bus rails with adequate transient margin, while the 3.1 mΩ RDS(on) keeps conduction losses below 1% at 25 A. The DPAK-2 (PG-TO252-3-11) package's drain tab provides Kelvin-source connectivity that simplifies thermal management on 2-oz copper. Designers select this part for compact, surface-mount POL modules where efficiency, size, and thermal performance are critical.
Recommended
Battery Management Load Switch
The IPD031N03LGATMA1 serves as a high-current load-disconnect switch in 12 V Li-ion battery management systems (BMS) for e-mobility and energy-storage applications. Its 90 A continuous current rating easily handles 5-10 kW peak loads, while the 3.1 mΩ RDS(on) limits steady-state voltage drop to ~93 mV at 30 A, preserving battery runtime. The MOSFET's low Qg allows PWM dimming or soft-start control via the gate pin. Place it in series with the battery positive rail, gate-pulled high through a 10 kΩ resistor and driven by a logic-level MOSFET driver for sub-microsecond disconnect response.
Recommended
Hot-Swap / OR-ing Controller Switch
In redundant -48 V telecom power OR-ing applications, the IPD031N03LGATMA1 acts as the OR-ing FET that prevents reverse current between paralleled power supplies. Its ultra-low 3.1 mΩ RDS(on) minimizes power dissipation to ~4.5 W at 38 A, allowing natural convection cooling on the PCB. The 30 V Vdss comfortably exceeds the 28 V regulated -48 V OR-ing voltage with margin for transients. Drive the gate with a dedicated OR-ing controller IC that regulates VGS to maintain a controlled forward voltage drop, minimizing both conduction and switching losses during supply switchover.
Recommended
DC Motor Drive (H-Bridge Low-Side)
The IPD031N03LGATMA1 is well-suited as the low-side switch in a 4-MOSFET H-bridge driving 12-24 V brushed DC motors up to 30 A continuous. Its 94 W power dissipation and DPAK-2 package handle repetitive 50 A peak inrush currents during motor startup without thermal shutdown. The 30 V Vdss rating supports inductive flyback transients up to ~50 V with adequate snubber sizing. Configure two IPD031N03LGATMA1 on the low side and two P-channel or higher-voltage N-channel MOSFETs on the high side, with a dedicated gate driver like the IR2114S for level shifting.
Recommended
Industrial 24V Bus Solid-State Relay (SSR)
In industrial automation, the IPD031N03LGATMA1 functions as the switching element in a 24 V DC solid-state relay (SSR) replacing mechanical contactors. Its 90 A current rating handles solenoid and motor loads, while the 3.1 mΩ RDS(on) keeps on-state voltage drop below 0.3 V at full load, eliminating heat sinks in compact panel-mount designs. The MOSFET's optical-isolated gate drive provides 5 kV galvanic isolation between logic and load, meeting IEC 61131-2 industrial control standards. Designers typically pair it with an optocoupler and gate-driver network to achieve sub-100 µs turn-off times for safety-critical applications.
Recommended
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Engineering reference data for IPD031N03LGATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | BSC014N04LSATMA1 | BSC0501NSIATMA1 | BSC0911NDATMA1 | BSC034N06NSATMA1 |
|---|---|---|---|---|---|
| Package | PG-TO252-3-11 (DPAK-2) | PG-TO252-3-11 (DPAK-2) - same | PG-TO252-3-11 (DPAK-2) - same | PG-TO252-3-11 (DPAK-2) - same | PG-TO252-3-11 (DPAK-2) - same |
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Drain-to-Source Voltage (Vdss) | 30 V | 40 V | 100 V | 30 V | 60 V |
| Continuous Drain Current @ 25°C | 90 A | 100 A | 50 A | 70 A | 85 A |
| RDS(on) Max @ VGS=10V | 3.1 mΩ | 1.4 mΩ | 50 mΩ | 9 mΩ | 3.4 mΩ |
| Power Dissipation | 94 W | 94 W | 94 W | 94 W | 94 W |
| Technology Generation | OptiMOS 3 | OptiMOS 3 | OptiMOS 3 | OptiMOS 5 | OptiMOS 3 |
| Unit Price (qty-1, as of 2026-09-14) | $0.92 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Lowest RDS(on) in 30 V DPAK-2 class (vs BSC0911NDATMA1)
- Higher peak current capability than 40V alternatives (vs BSC014N04LSATMA1)
- Optimized for 12V synchronous rectification (vs BSC0501NSIATMA1)
- Same footprint as 60V alternatives enables design reuse (vs BSC034N06NSATMA1)
Design Notes
Estimated: at 30 A continuous load and RDS(on) of 3.1 mΩ, the IPD031N03LGATMA1 dissipates approximately 2.8 W of conduction loss. With the PG-TO252-3-11 package thermal resistance of approximately 50 °C/W on a 200 mm² 2-oz copper pour, the junction temperature rises ~140 °C above ambient. For sustained 30 A operation, increase copper area to at least 400 mm² on both top and bottom layers, or add a small clip-on heatsink. Without these measures, sustained operation above 25 A risks thermal shutdown at the 175 °C Tj limit.
Place the gate-drive loop (gate resistor to gate pin to source pin back to driver ground) in a tight area of less than 10 mm² to minimize parasitic inductance. Excessive gate-loop inductance causes ringing and can exceed the ±20 V VGS absolute-maximum rating during turn-off. Keep the drain tab (DPAK back-metal) soldered to a continuous copper pour with at least 8 thermal vias (0.3 mm drill) underneath to provide low thermal resistance to inner PCB layers. Avoid routing high-current drain traces on inner layers where thermal dissipation is poor.
Do not exceed 30 V Vds even transiently; use a TVS clamp such as SMBJ5.0A across drain-to-source for inductive loads. Avoid operating below the 4.5 V gate-threshold region — incomplete enhancement can cause linear-region operation and rapid thermal failure. When used as a synchronous rectifier, ensure the dead-time between high-side and low-side switching is less than 100 ns to limit body-diode conduction loss. Finally, never connect the source pin to the drain tab, as the tab is internally bonded to drain (not source) in DPAK-2.
In high-frequency switching applications (>200 kHz), the OptiMOS 3's ultra-low Qg (~30 nC typical) reduces gate-drive losses, but the gate resistor value is critical. Use 4.7 Ω to 10 Ω gate resistors to dampen ringing without sacrificing switching speed. Add a 100 kΩ gate-source pull-down resistor to ensure the MOSFET stays off during controller power-up when gate-drive voltage is undefined. For pulse-width-modulated applications, verify that the gate-driver IC has sufficient source/sink current capability (≥2 A peak) to fully charge the MOSFET input capacitance within 20 ns.
Compliance Information
RoHS compliant and lead-free per Infineon product declaration. Halogen-free molding compound per Infineon OptiMOS 3 family standard. AEC-Q100 not applicable — this is a power MOSFET, not an automotive-qualified IC; no Q1 or Q-qualified variant in this package. REACH SVHC declarations available through Infineon environmental portal.
