IPG20N10S4L35AATMA1 - 100V Dual N-Ch 20A MOSFET | Infineon
MPN: IPG20N10S4L35AATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.65 | $16.50 |
| 100 | $1.42 | $142.00 |
| 500 | $1.18 | $590.00 |
| 1,000 | $0.98 | $980.00 |
IPG20N10S4L35AATMA1 Overview
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch that uses an insulated gate to modulate conduction between source and drain terminals. Within the broader power-semiconductor taxonomy, this part sits in the N-channel enhancement-mode MOSFET family, which is the most common topology for low-side and high-side switching. Logic-level MOSFETs such as the IPG20N10S4L-35 are designed to be fully enhanced at VGS as low as 4.5 V, allowing direct drive from microcontrollers, gate-driver ICs, and 5 V logic rails without a charge pump or level shifter.
Key differentiating features include 35 mΩ R<sub>DS(on)</sub> at 10 V VGS and 17 A ID, logic-level gate drive (fully enhanced at 4.5 V), dual N-channel configuration for synchronous or half-bridge topologies, and an integrated exposed pad (PG-TDSON-8-10) that doubles as the drain connection and thermal relief. The wettable-flank terminations enable automated optical inspection (AOI), which is required by most Tier-1 automotive PCB-assembly processes.
The IPG20N10S4L-35 uses Infineon's OptiMOS™ trench-cell process technology, which minimizes figure-of-merit (R<sub>DS(on)</sub> × Qg) to reduce both conduction and switching losses. The two FETs inside share the same silicon die geometry but are connected to independent source pins, allowing designers to use them in parallel, in a half-bridge, or as two independent low-side switches.
Typical applications include automotive LED drivers, 12 V/24 V DC-DC converters, motor control H-bridges, reverse-polarity protection circuits, and load-switching modules. The 100 V rating also makes the part suitable for 48 V mild-hybrid and industrial bus systems with adequate derating.
When designing with this part, place the gate-drive resistor (typically 10-100 Ω) close to the gate pin and minimize the gate-loop area to limit ringing. The exposed drain pad must be soldered to a sufficiently large copper pour (at least 25 mm² on a 1 oz board) to keep R<sub>θJA</sub> within the datasheet limits.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the Infineon datasheet, helping engineers select, source, and lay out the IPG20N10S4L-35 faster.
Drop-in alternatives for IPG20N10S4L35AATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IPG20N10S4L35AATMA1 (same form factor and footprint) — differing in AEC-Q101 Qualification, Avalanche Rating, FET Type, Operating Temperature Range, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IPG20N10S4L-26ATMA1
✅ Drop-In📋 Reference alternative (not in catalog)
IPG20N10S4L-35
✅ Drop-In📋 Reference alternative (not in catalog)
IPC50N04S5L5R5ATMA1
✅ Drop-In✓ In Stock
$0.36 / Unit
View Datasheet →BSC076N04NDATMA1
✅ Drop-In✓ In Stock
$0.82 / Unit
View Datasheet →NTMFS0D7N10MCL
✅ Drop-In📋 Reference alternative (not in catalog)
IPB35N10S3L26ATMA1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1.15 / Unit
View Datasheet →IPG20N10S4L35AATMA1 Maximum Ratings & Electrical Characteristics
| FET Type | Dual N-Channel (2 independent N-MOSFETs) |
| Technology | OptiMOS™ trench MOSFET, logic-level |
| Drain-to-Source Voltage (VDS) | 100 V |
| Continuous Drain Current (ID) @ TC=25°C | 20 A (per channel) |
| RDS(on) Max @ VGS=10 V, ID=17 A | 35 mΩ |
| Gate Threshold (VGS(th)) | Logic-level (typ. 1.7 V, fully enhanced at 4.5 V) |
| Power Dissipation (PD) @ TC=25°C | 43 W |
| Operating Temperature Range | -55°C to +175°C (TJ) |
| Package | PG-TDSON-8-10 (TDSON EP, wettable flank) |
| Mounting Type | Surface Mount |
| Avalanche Rating | 100% avalanche tested |
| AEC-Q101 Qualification | Yes (automotive grade) |
| RoHS Compliance | Yes (Green Product) |
| Drain Connection | Exposed pad (EP) tied to drain |
IPG20N10S4L35AATMA1 Pin Configuration
| Pin 1 | GATE 1 — Gate of MOSFET 1 (logic-level, 4.5 V enhancement) |
| Pin 2 | DRAIN 1 — Drain of MOSFET 1 (also exposed pad) |
| Pin 3 | SOURCE 1 — Source of MOSFET 1 |
| Pin 4 | SOURCE 1 — Source of MOSFET 1 (second bond pad) |
| Pin 5 | SOURCE 2 — Source of MOSFET 2 (second bond pad) |
| Pin 6 | SOURCE 2 — Source of MOSFET 2 |
| Pin 7 | DRAIN 2 — Drain of MOSFET 2 |
| Pin 8 | GATE 2 — Gate of MOSFET 2 (logic-level, 4.5 V enhancement) |
| Pin EP | DRAIN (PAD) — Exposed thermal pad - internally bonded to Drain 1 and Drain 2 |
Safe Operating Area (DC, TJ=175°C)
Typical Applications
IPG20N10S4L35AATMA1 is suitable for 6 applications: Automotive LED Driver (Daylight Running Lights), 48 V Mild-Hybrid DC-DC Converter, H-Bridge Motor Driver (12 V/24 V DC Motor), Reverse-Polarity Protection / Hot-Swap, Industrial Load Switching / Solenoid Drive, Battery Management - Cell Balancing / Protection.
Automotive LED Driver (Daylight Running Lights)
The IPG20N10S4L35AATMA1's 100 V VDS rating and logic-level gate drive make it ideal for automotive LED front-light modules and DRLs running on 12 V/24 V buses. With 35 mΩ RDS(on) at 10 V VGS, conduction losses stay below 5% even at 5 A continuous LED current, and the PG-TDSON-8-10 wettable-flank package enables fully automated AOI on Tier-1 PCB lines. Placed as a low-side switch in a buck topology, it dissipates approximately 0.875 W at 5 A (35 mΩ × 5²), well within the 43 W package limit with proper copper thermal relief. AEC-Q101 qualification ensures it survives automotive -40°C to +125°C ambient profiles.
Recommended
48 V Mild-Hybrid DC-DC Converter
The IPG20N10S4L35AATMA1 is a strong candidate for 48 V mild-hybrid DC-DC converters stepping down to 12 V rails for auxiliary loads. Its 100 V VDS comfortably handles 48 V nominal plus transient spikes up to 60 V during load-dump events, and the dual N-channel configuration enables a synchronous half-bridge topology that improves efficiency over diode rectification. The 35 mΩ RDS(on) keeps full-load conduction loss around 1.4 W per FET at 20 A, manageable in the PG-TDSON-8-10 package with a 25 mm² copper pour. Logic-level drive simplifies the bootstrap gate-driver design significantly.
Recommended
H-Bridge Motor Driver (12 V/24 V DC Motor)
For low-voltage brushed DC motors and small BLDC drives, the IPG20N10S4L35AATMA1's dual N-channel configuration provides a complete half-bridge in a single PG-TDSON-8-10 package, reducing PCB area by 50% versus discrete single-FET designs. The 100 V VDS provides ample headroom for 24 V nominal buses with inductive flyback transients clamped by the body diode or an external TVS. At 20 A peak per channel, the part can drive motors up to approximately 250 W mechanical output. Logic-level gates pair directly with 5 V gate-driver ICs or MCUs with PWM outputs for variable-speed control.
Recommended
Reverse-Polarity Protection / Hot-Swap
The IPG20N10S4L35AATMA1 functions excellently as a low-side reverse-polarity protection switch or hot-swap controller in 12 V/24 V industrial systems. With 100 V VDS it tolerates load transients far beyond the bus voltage, and 35 mΩ RDS(on) keeps insertion loss under 100 mV at 3 A continuous load. The logic-level gate allows simple MCU-controlled enable/disable for inrush current limiting using PWM soft-start. AEC-Q101 qualification is a plus for factory-floor equipment that must survive wide temperature swings and vibration.
Recommended
Industrial Load Switching / Solenoid Drive
For industrial PLC outputs, solenoid valves, and relay-replacement circuits, the IPG20N10S4L35AATMA1 provides rugged 100 V switching in a small PG-TDSON-8-10 package. With 100% avalanche rating it can absorb the inductive kickback from solenoids without external snubbers in most cases, simplifying the BOM. Logic-level gate drive is compatible with 5 V PLC logic outputs, and the dual-FET configuration allows two independent channels from a single IC, reducing board space and cost per channel.
Recommended
Battery Management - Cell Balancing / Protection
In multi-cell lithium battery packs, the IPG20N10S4L35AATMA1 can serve as a passive cell-balancing switch or as part of a battery-protection FET arrangement. The 100 V rating covers 14-16S Li-ion packs (up to 67.2 V nominal), and the logic-level gate simplifies drive from a low-voltage BMS AFE IC. The PG-TDSON-8-10 dual-FET configuration provides two balancing channels per IC, reducing PCB area in space-constrained battery modules. AEC-Q101 qualification is advantageous for e-mobility and stationary storage applications.
Recommended
Recommended Products Summary
Engineering reference data for IPG20N10S4L35AATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IPG20N10S4L-26ATMA1 | IPG20N10S4L-35 | IPC50N04S5L5R5ATMA1 | BSC076N04NDATMA1 | NTMFS0D7N10MCL |
|---|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | onsemi |
| Package | PG-TDSON-8-10 | PG-TDSON-8-10 (same) | PG-TDSON-8-10 (same) | PG-TDSON-8-10 (same) | PG-TDSON-8-10 (same) | SO-8FL/DFN-5x6 (drop-in land pattern) |
| Drain-Source Voltage (VDS) | 100 V | 100 V | 100 V | 40 V | 40 V | 100 V |
| Continuous Drain Current (ID) | 20 A | 20 A | 20 A | 50 A | 16 A | 20 A |
| RDS(on) Max @ 10 V | 35 mΩ | 26 mΩ | 35 mΩ | 5.5 mΩ | 7.6 mΩ | 37 mΩ |
| Gate Drive Level | Logic-level (4.5 V) | Logic-level (4.5 V) | Logic-level (4.5 V) | Logic-level | Standard (10 V) | Logic-level |
| AEC-Q101 Qualified | Yes | Yes | Yes | Yes | Yes | Yes |
| Power Dissipation (PD) | 43 W | 43 W | 43 W | 50 W | 36 W | 39 W |
Key Differentiators
- Logic-level gate drive (4.5 V) eliminates charge pump (vs BSC076N04NDATMA1)
- 100 V VDS covers 48 V mild-hybrid and industrial 24 V/36 V buses (vs IPC50N04S5L5R5ATMA1)
- Wettable-flank package enables automated optical inspection (vs STD25NF10LT4 (TO-252/DPAK))
Design Notes
Estimated: At continuous 20 A load with VGS=10 V, conduction loss = I² × RDS(on) = 20² × 0.035 = 14 W per channel. The PG-TDSON-8-10 has θJA ≈ 50°C/W on a standard 1 oz 25 mm² copper pour on JEDEC EIA/JESD51 2S2P board, giving junction temperature rise of 14 × 50 = 700°C above ambient - clearly unsustainable. Designers must limit continuous current to approximately 6-8 A per channel on minimal copper, or significantly increase copper area (≥100 mm²) or use forced-air cooling for higher continuous currents. Always verify with the datasheet SOA curves at the target VDS and pulse duration.
Place the gate-drive resistor (typically 10-100 Ω) as close as possible to the gate pin to minimize the gate-loop inductance and prevent ringing. Use a star-ground pattern tying source pins directly to the ground plane via short traces. The exposed drain pad must be soldered to a copper pour of at least 25 mm² on a 1 oz board; vias in the pad (filled and capped) significantly improve thermal performance. Keep high-current traces wide (>2 mm per ampere) and minimize the switching-node copper area to limit EMI.
In half-bridge configurations, the high-side and low-side switching nodes must not share copper area with sensitive analog or logic traces - the dV/dt can exceed 5 kV/μs. Use Kelvin connection to the low-side source pin (pin 3/4 for FET1, pin 5/6 for FET2) by routing the gate-drive return through a separate trace to the source pin rather than the power ground. This eliminates the source-inductance feedback that would otherwise slow turn-on and increase switching losses. Place a small RC snubber (10 Ω + 1 nF) across each FET if ringing exceeds 20% of VDS.
Do not drive the IPG20N10S4L35AATMA1 directly from a 3.3 V microcontroller GPIO - the datasheet specifies full enhancement at 4.5 V minimum, and 3.3 V drive leaves the MOSFET in the linear region with high RDS(on) and rapid thermal runaway. Use a 5 V gate-driver IC, a logic-level shifter, or a charge pump. Also avoid exceeding the 100 V VDS during inductive switching - always include a flyback diode, TVS clamp, or rely on the body diode with adequate snubbing for solenoid/relay/motor loads.
To minimize EMI from the IPG20N10S4L35AATMA1 in switching applications, slow the gate-drive edge by increasing the gate resistor to 47-100 Ω, which reduces dV/dt and the resulting high-frequency harmonics. Add a small ferrite bead or common-mode choke on the power input lines, and ensure the switching loop (DC+ bus → high-side FET → low-side FET → DC-) is kept physically tight and small. For automotive applications targeting CISPR 25 Class 5, the 100 V/35 mΩ OptiMOS™ is well-suited but may still require an input π-filter to meet conducted emissions limits above 30 MHz.
Compliance Information
AEC-Q101 qualified per Infineon datasheet. RoHS and REACH compliant (Green Product). 100% avalanche tested. Wettable-flank package for AOI compliance.
