EPM240GT100 - MAX II 240-LE CPLD, TQFP-100 | Intel (Altera)
MPN: EPM240GT100 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.5 | $11.50 |
| 10 | $10.2 | $102.00 |
| 100 | $8.95 | $895.00 |
| 500 | $7.8 | $3,900.00 |
| 1,000 | $6.95 | $6,950.00 |
Drop-in alternatives for EPM240GT100 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM240GT100I5N
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View Datasheet →EPM240T100I5N
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View Datasheet →EPM240T100C5N
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View Datasheet →EPM240GT100 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LEs) | 240 |
| Equivalent Macrocells | 192 |
| Non-Volatile Flash Memory | 8 Kbits |
| Maximum User I/Os | 80 |
| Package | TQFP-100 (GT suffix) |
| Process Technology | 0.18 um, 6-layer-metal flash |
| Core Voltage | 3.3 V or 2.5 V |
| I/O Standards Supported | 1.8V, 2.5V, 3.3V, 5V (MultiVolt) |
| Operating Temperature (Commercial) | 0 C to 85 C |
| Operating Temperature (Industrial) | -40 C to 100 C |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount |
| Design Software | Quartus II / Quartus Prime Lite |
EPM240GT100 Pin Configuration
| Pin 1 | I/O — General purpose user I/O pin (bank 1) |
| Pin 2 | I/O — General purpose user I/O pin (bank 1) |
| Pin 3 | I/O — General purpose user I/O pin (bank 1) |
| Pin 4 | I/O — General purpose user I/O pin (bank 1) |
| Pin 5 | I/O — General purpose user I/O pin (bank 1) |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — General purpose user I/O pin (bank 1) |
| Pin 8 | I/O — General purpose user I/O pin (bank 1) |
| Pin 9 | I/O — General purpose user I/O pin (bank 1) |
| Pin 10 | I/O — General purpose user I/O pin (bank 1) |
| Pin 11 | I/O — General purpose user I/O pin (bank 1) |
| Pin 12 | I/O — General purpose user I/O pin (bank 1) |
| Pin 13 | I/O — General purpose user I/O pin (bank 1) |
| Pin 14 | I/O — General purpose user I/O pin (bank 1) |
| Pin 15 | VCCIO1 — I/O bank 1 supply voltage (1.8V/2.5V/3.3V/5V) |
| Pin 16 | I/O — General purpose user I/O pin (bank 2) |
| Pin 17 | I/O — General purpose user I/O pin (bank 2) |
| Pin 18 | I/O — General purpose user I/O pin (bank 2) |
| Pin 19 | I/O — General purpose user I/O pin (bank 2) |
| Pin 20 | I/O — General purpose user I/O pin (bank 2) |
| Pin 21 | I/O — General purpose user I/O pin (bank 2) |
| Pin 22 | I/O — General purpose user I/O pin (bank 2) |
| Pin 23 | I/O — General purpose user I/O pin (bank 2) |
| Pin 24 | I/O — General purpose user I/O pin (bank 2) |
| Pin 25 | GND — Ground |
| Pin 26 | I/O — General purpose user I/O pin (bank 2) |
| Pin 27 | I/O — General purpose user I/O pin (bank 2) |
| Pin 28 | I/O — General purpose user I/O pin (bank 2) |
| Pin 29 | I/O — General purpose user I/O pin (bank 2) |
| Pin 30 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 31 | I/O — General purpose user I/O pin (bank 2) |
| Pin 32 | I/O — General purpose user I/O pin (bank 2) |
| Pin 33 | I/O — General purpose user I/O pin (bank 2) |
| Pin 34 | I/O — General purpose user I/O pin (bank 2) |
| Pin 35 | I/O — General purpose user I/O pin (bank 2) |
| Pin 36 | I/O — General purpose user I/O pin (bank 3) |
| Pin 37 | GND — Ground |
| Pin 38 | I/O — General purpose user I/O pin (bank 3) |
| Pin 39 | I/O — General purpose user I/O pin (bank 3) |
| Pin 40 | I/O — General purpose user I/O pin (bank 3) |
| Pin 41 | I/O — General purpose user I/O pin (bank 3) |
| Pin 42 | I/O — General purpose user I/O pin (bank 3) |
| Pin 43 | I/O — General purpose user I/O pin (bank 3) |
| Pin 44 | I/O — General purpose user I/O pin (bank 3) |
| Pin 45 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 46 | I/O — General purpose user I/O pin (bank 3) |
| Pin 47 | I/O — General purpose user I/O pin (bank 3) |
| Pin 48 | I/O — General purpose user I/O pin (bank 3) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — General purpose user I/O pin (bank 3) |
| Pin 51 | I/O — General purpose user I/O pin (bank 3) |
| Pin 52 | I/O — General purpose user I/O pin (bank 4) |
| Pin 53 | I/O — General purpose user I/O pin (bank 4) |
| Pin 54 | I/O — General purpose user I/O pin (bank 4) |
| Pin 55 | I/O — General purpose user I/O pin (bank 4) |
| Pin 56 | I/O — General purpose user I/O pin (bank 4) |
| Pin 57 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 58 | I/O — General purpose user I/O pin (bank 4) |
| Pin 59 | I/O — General purpose user I/O pin (bank 4) |
| Pin 60 | I/O — General purpose user I/O pin (bank 4) |
| Pin 61 | I/O — General purpose user I/O pin (bank 4) |
| Pin 62 | GND — Ground |
| Pin 63 | I/O — General purpose user I/O pin (bank 4) |
| Pin 64 | I/O — General purpose user I/O pin (bank 4) |
| Pin 65 | I/O — General purpose user I/O pin (bank 4) |
| Pin 66 | I/O — General purpose user I/O pin (bank 4) |
| Pin 67 | I/O — General purpose user I/O pin (bank 4) |
| Pin 68 | VCCINT — Core supply voltage (3.3V or 2.5V) |
| Pin 69 | I/O — General purpose user I/O pin (bank 4) |
| Pin 70 | I/O — General purpose user I/O pin (bank 4) |
| Pin 71 | I/O — General purpose user I/O pin (bank 4) |
| Pin 72 | GND — Ground |
| Pin 73 | I/O — General purpose user I/O pin (bank 1) |
| Pin 74 | I/O — General purpose user I/O pin (bank 1) |
| Pin 75 | I/O — General purpose user I/O pin (bank 1) |
| Pin 76 | TDI — JTAG Test Data In |
| Pin 77 | TMS — JTAG Test Mode Select |
| Pin 78 | TCK — JTAG Test Clock |
| Pin 79 | TDO — JTAG Test Data Out |
| Pin 80 | I/O — General purpose user I/O pin (bank 1) |
| Pin 81 | I/O — General purpose user I/O pin (bank 1) |
| Pin 82 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 83 | I/O — General purpose user I/O pin (bank 1) |
| Pin 84 | I/O — General purpose user I/O pin (bank 1) |
| Pin 85 | I/O — General purpose user I/O pin (bank 1) |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — General purpose user I/O pin (bank 1) |
| Pin 88 | I/O — General purpose user I/O pin (bank 1) |
| Pin 89 | I/O — General purpose user I/O pin (bank 1) |
| Pin 90 | I/O — General purpose user I/O pin (bank 1) |
| Pin 91 | I/O — General purpose user I/O pin (bank 1) |
| Pin 92 | I/O — General purpose user I/O pin (bank 1) |
| Pin 93 | I/O — General purpose user I/O pin (bank 1) |
| Pin 94 | VCCINT — Core supply voltage (3.3V or 2.5V) |
| Pin 95 | I/O — General purpose user I/O pin (bank 1) |
| Pin 96 | I/O — General purpose user I/O pin (bank 1) |
| Pin 97 | I/O — General purpose user I/O pin (bank 1) |
| Pin 98 | GND — Ground |
| Pin 99 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM240GT100 is suitable for 6 applications: Glue Logic Replacement, FPGA Configuration & Control, I/O Expander & Level Shifter, Bus Interface Bridge, Power-Up Sequencer & Supervisor, Industrial Control & Logic Consolidation.
Glue Logic Replacement
The EPM240GT100 is widely deployed as a single-chip replacement for multiple 74LS, 74HC, and 74FTTL discrete logic gates, latches, and decoders. With 240 logic elements in a TQFP-100, the device can absorb 30-60 discrete SSI/MSI parts onto one footprint, shrinking PCB area and BOM count. The non-volatile Flash means the circuit powers up in a known state every time - critical for FPGA configuration control, watchdog reset generation, and chip-select decoding. The 5V-tolerant MultiVolt I/O also lets the EPM240GT100 bridge legacy 5V logic to modern 3.3V FPGAs without level shifters.
Recommended
FPGA Configuration & Control
A classic use case is having the EPM240GT100 act as the configuration supervisor for a larger SRAM-based FPGA. The CPLD holds the FPGA's nSTATUS, nCONFIG, and CONF_DONE signals, generates multi-mode configuration clocks, selects between two bitstreams for failsafe updates, and sequences the FPGA's power rails. With 80 user I/Os in TQFP-100, the EPM240GT100 can simultaneously drive configuration, status LEDs, fan PWM, and housekeeping GPIO. Its instant-on behavior guarantees the FPGA is properly held in reset until supplies are stable - a level of robustness discrete logic cannot match.
Recommended
I/O Expander & Level Shifter
The EPM240GT100's MultiVolt I/O banks support 1.8V, 2.5V, 3.3V, and 5V signaling simultaneously on the same device. Engineers use it as an I/O expander for microcontrollers that lack sufficient GPIO, or as a level shifter between voltage domains. With 80 user I/Os in TQFP-100, the EPM240GT100 can implement 40+ bidirectional level-translated channels. The non-volatile configuration means each board powers up with the correct pin directions and pull-ups already configured, eliminating host-boot-time races seen with I/O expanders on I2C/SPI.
Recommended
Bus Interface Bridge
Designers use the EPM240GT100 to bridge between incompatible bus protocols - parallel memory to serial SPI, 8-bit MCU bus to 16-bit peripheral, or legacy ISA to modern glue logic. The 240 logic elements and 80 I/Os accommodate full 16-bit data plus 24-bit address plus control signal translation on a single chip. The deterministic MAX II timing (no async routing delays) is essential for bus-cycle-accurate bridges. The CPLD's fast tCO and tSU numbers also make it ideal for memory-interleaving controllers in legacy industrial retrofits.
Recommended
Power-Up Sequencer & Supervisor
The EPM240GT100 is ideal for sequencing multiple power rails in networking, server, and industrial systems. With a programmable state machine in 240 logic elements, the CPLD can monitor PG (power-good) inputs and assert EN (enable) outputs in a defined order with programmable delays. The non-volatile Flash means sequencing is hard-coded into the silicon - no firmware to misbehave. The 5V-tolerant inputs can directly monitor legacy analog supervisors, while 3.3V outputs can drive most modern POL regulators' enable pins.
Recommended
Industrial Control & Logic Consolidation
In factory automation and process control, the EPM240GT100 replaces racks of relay logic with a single reprogrammable device. Designers can implement safety interlocks, motor-start sequences, encoder quadrature decoding, PWM generation, and Modbus framing on one TQFP-100 chip. The industrial temperature grade variant (EPM240GT100I5N, -40C to 100C) handles factory floor conditions. The 100-pin TQFP footprint is also easy to hand-prototype or rework on legacy industrial designs where BGA assembly is impractical.
Recommended
Recommended Products Summary
Engineering reference data for EPM240GT100 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240GT100I5N | EPM240GT100C5N | EPM240F100I5N | EPM240F100C5N | EPM240T100I5N | EPM240T100C5N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 240 | 240 | 240 | 240 | 240 | 240 | 240 |
| Temperature Grade | Commercial 0-85C (assumed base EPM240GT100) | Industrial -40C to 100C | Commercial 0-85C | Industrial -40C to 100C | Commercial 0-85C | Industrial -40C to 100C | Commercial 0-85C |
| Speed Grade | G (faster than T, slower than F) | G | G | F (fastest) | F (fastest) | T (slowest) | T (slowest) |
| Non-Volatile Memory | 8 Kbits Flash | 8 Kbits Flash | 8 Kbits Flash | 8 Kbits Flash | 8 Kbits Flash | 8 Kbits Flash | 8 Kbits Flash |
| Maximum User I/Os | 80 | 80 | 80 | 80 | 80 | 80 | 80 |
| Core Voltage | 3.3V / 2.5V | 3.3V / 2.5V | 3.3V / 2.5V | 3.3V / 2.5V | 3.3V / 2.5V | 3.3V / 2.5V | 3.3V / 2.5V |
Key Differentiators
- Non-volatile flash configuration with instant-on behavior (vs SRAM-based FPGAs like Cyclone IV)
- MultiVolt I/O supporting 1.8V/2.5V/3.3V/5V in one device (vs Discrete 74-series level shifters)
- TQFP-100 footprint provides maximum EPM240 I/O count (vs EPM240GM100 (MBGA-100))
Design Notes
Estimated: The EPM240GT100 with all 80 I/Os toggling at 50 MHz draws approximately 30-50 mA from VCCINT (3.3V) and another 10-20 mA per VCCIO bank. Decouple each VCCINT and VCCIO pin with a 100 nF X7R ceramic placed within 5 mm of the pin, plus a 10 uF bulk capacitor at the supply entry. Use a star-ground topology tying all GND pins to a single solid ground plane under the TQFP-100 footprint. Do not share VCCIO banks between 5V and 3.3V loads - separate them onto independent VCCIO1..VCCIO4 rails so MultiVolt level shifting works correctly.
The TQFP-100 package has 0.5 mm lead pitch with exposed leads on all four sides. Use a 4-layer PCB with a solid ground plane on layer 2 directly under the CPLD to provide a low-impedance return path for the high-edge-rate I/O signals. Route JTAG signals (TDI, TMS, TCK, TDO) as a 4-wire bus with 22-33 ohm source-series termination if the JTAG chain exceeds 100 mm. The EPM240GT100 is a non-volatile flash device - programming times are typically under 1 second via JTAG, but the JTAG chain must be properly terminated at both ends with TCK pull-ups per IEEE 1149.1.
Do not assume the EPM240GT100 (240 LE) is pin-compatible with EPM570T100 (570 LE) or EPM2210F256 (2210 LE) just because the package outline matches - the larger MAX II devices have different JTAG pin assignments and additional power/ground pins. Always check the datasheet's TQFP-100 pinout table before swapping density variants. Also note that the 'GT' suffix denotes TQFP-100, while 'GM' is MBGA-100 and 'GF' is FineLine BGA-100 - the ball/pin counts match but the footprints do not interchange. Industrial-grade (I5N) parts require factory lead time of 6-10 weeks; commercial (C5N) parts typically ship from distributor stock.
Although the EPM240GT100 is a relatively slow CPLD (pin-to-pin delays in the 3-7 ns range), its MultiVolt I/O can drive 5V TTL loads directly when VCCIO is set to 3.3V, with marginal overshoot/undershoot possible. For busses longer than 50 mm or with 8+ loads, add 22-33 ohm series resistors at the source pins to dampen transmission-line ringing. The MAX II MultiTrack interconnect is deterministic - once you compile a design in Quartus, the timing report guarantees those numbers regardless of routing - so external signal-integrity analysis only needs to address the PCB traces, not internal device routing.
Compliance Information
RoHS and lead-free compliant per Intel/Altera MAX II product environmental documentation. Not AEC-Q100 qualified - this is a commercial/industrial-grade CPLD intended for non-automotive applications.
