EPM570GF100C5N - MAX II 570 LE CPLD, 100-FBGA | Altera
MPN: EPM570GF100C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.97 | $18.97 |
| 10 | $17.45 | $174.50 |
| 100 | $15.2 | $1,520.00 |
| 500 | $13.1 | $6,550.00 |
| 1,000 | $11.65 | $11,650.00 |
Drop-in alternatives for EPM570GF100C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM570F100C5N
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View Datasheet βEPM570GF100C5N Maximum Ratings & Electrical Characteristics
| Device Family | MAX II |
| Logic Elements | 570 |
| Macrocells | 440 |
| User I/Os | 76 |
| Propagation Delay (tPD) | 5.4 ns |
| Package | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Configuration Memory | On-chip Flash (non-volatile) |
| Core Voltage | 1.8 V (internal) |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs) |
| Operating Temperature | -40C to +125C (industrial) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1532 / JTAG (IEEE 1149.1) ISP |
| RoHS Status | Compliant (lead-free) |
| Logic Family / Process | CMOS, Flash-based LUT |
| LABs | 4 (16 macrocells per LAB) |
EPM570GF100C5N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 2) |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | VCCIO1 β I/O bank 1 supply voltage (1.8/2.5/3.3 V) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | I/O β User I/O pin (bank 1) |
| Pin 31 | I/O β User I/O pin (bank 1) |
| Pin 32 | I/O β User I/O pin (bank 1) |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | VCCIO3 β I/O bank 3 supply voltage (1.8/2.5/3.3 V) |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin (bank 4) |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | I/O β User I/O pin (bank 4) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | VCCIO4 β I/O bank 4 supply voltage (1.8/2.5/3.3 V) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | GND β Ground |
| Pin 78 | TDI β JTAG Test Data In |
| Pin 79 | TMS β JTAG Test Mode Select |
| Pin 80 | TCK β JTAG Test Clock |
| Pin 81 | TDO β JTAG Test Data Out |
| Pin 82 | nCONFIG β Configuration control (active-low) |
| Pin 83 | nSTATUS β Configuration status (active-low) |
| Pin 84 | CONF_DONE β Configuration done indicator |
| Pin 85 | VCCINT β Internal core supply (1.8 V) |
| Pin 86 | GND β Ground |
| Pin 87 | VCCIO2 β I/O bank 2 supply voltage (1.8/2.5/3.3 V) |
| Pin 88 | I/O β User I/O pin (bank 2) |
| Pin 89 | I/O β User I/O pin (bank 2) |
| Pin 90 | I/O β User I/O pin (bank 2) |
| Pin 91 | I/O β User I/O pin (bank 2) |
| Pin 92 | I/O β User I/O pin (bank 2) |
| Pin 93 | I/O β User I/O pin (bank 2) |
| Pin 94 | I/O β User I/O pin (bank 2) |
| Pin 95 | I/O β User I/O pin (bank 2) |
| Pin 96 | I/O β User I/O pin (bank 2) |
| Pin 97 | I/O β User I/O pin (bank 2) |
| Pin 98 | GND β Ground |
| Pin 99 | VCCIO1 β I/O bank 1 supply voltage (1.8/2.5/3.3 V) |
| Pin 100 | VCCINT β Internal core supply (1.8 V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GF100C5N is suitable for 6 applications: Industrial Glue Logic and Bus Bridging, I/O Expansion for Microcontrollers, Power Sequencing and Reset Distribution, Portable Consumer and Handheld Devices, LED Display Multiplexing and Drive, Legacy System Replacement and Obsolescence Management.
Industrial Glue Logic and Bus Bridging
The EPM570GF100C5N is widely used as glue logic in industrial controllers where deterministic pin-to-pin timing (5.4 ns tPD) and instant-on Flash configuration are essential. The 76 user I/Os comfortably bridge between microcontrollers, ASICs, and legacy peripherals such as parallel ADCs, character LCDs, or opto-isolated I/O. With 1.8/2.5/3.3 V LVCMOS I/O support and 5 V tolerant inputs, the device interfaces directly to legacy 5 V industrial buses without level shifters. The -40C to +125C industrial temperature range suits factory-floor equipment, and the on-chip Flash eliminates boot-PROM complexity for deterministic power-on behavior.
Recommended
I/O Expansion for Microcontrollers
Adding I/O to a microcontroller is a classic CPLD use case, and the EPM570GF100C5N with 76 user I/Os handles PWM generation, quadrature decoding, and shift-register multiplexing that would otherwise consume scarce MCU pins. The deterministic 5.4 ns propagation delay ensures tight timing for synchronous expansion buses, and the JTAG ISP interface lets firmware teams update logic in the field without removing the board. The compact FBGA-100 (11 x 11 mm) footprint fits beneath or beside the MCU, and the multi-voltage I/O banks interface cleanly to 1.8 V, 3.3 V, and 5 V mixed-signal designs common in IoT edge nodes.
Recommended
Power Sequencing and Reset Distribution
Power-rail sequencing and reset signal distribution are ideal MAX II CPLD applications because of their instant-on Flash memory and configurable output-enable logic. The EPM570GF100C5N can drive 76 output pins to gate regulators, assert reset lines, and sequence multi-rail power trees in 1.8 V / 2.5 V / 3.3 V domains. Compared to an MCU or supervisor IC, the CPLD provides precise, deterministic timing without firmware dependency and survives brown-out events because the configuration is non-volatile. The FBGA-100 package fits into compact PMIC companion boards.
Recommended
Portable Consumer and Handheld Devices
The EPM570GF100C5N's low quiescent power, instant-on Flash, and small 11 x 11 mm BGA footprint make it suitable for portable consumer products where battery life and board area are at a premium. Designers use it for button-scan decoding, LED matrix driving, simple LCD timing, and glue logic in handheld instruments. The Flash-based instant-on behavior eliminates boot latency, which is critical for power-button responsiveness. Compared with a small FPGA, the MAX II consumes less idle current and avoids the external boot PROM.
Recommended
LED Display Multiplexing and Drive
Driving multiplexed LED arrays and seven-segment displays is a classic CPLD application where the EPM570GF100C5N's 76 I/Os and deterministic timing shine. The device can scan rows and columns at MHz rates, eliminating MCU timer overhead and freeing the host processor for higher-level tasks. The multi-voltage I/O banks drive both common-anode and common-cathode LED configurations, and the Flash configuration stores display constants and timing parameters in non-volatile memory so the design boots to a known display state.
Recommended
Legacy System Replacement and Obsolescence Management
The EPM570GF100C5N is a key part for maintaining installed-base industrial and telecom equipment that was designed around the MAX II family. Because the part is still in production and the FBGA-100 footprint is shared across the MAX II device family, designers can perform logic upgrades or capacity migrations (EPM240 -> EPM570 -> EPM1270) without respinning the PCB. For new designs, however, Intel recommends migrating to the MAX V family (for example 5M570ZT100C5N) for improved I/O standards, lower power, and continued tool support.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GF100C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570F100C5N | EPM570F100C4N | EPM570F100I5N | EPM1270GF100C5N | EPM570F256C5N | EPM240GF100C5N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | FBGA-100 (11x11 mm, 1.0 mm pitch) | FBGA-100 (11x11 mm) - same | FBGA-100 (11x11 mm) - same | FBGA-100 (11x11 mm) - same | FBGA-100 (11x11 mm) - same | FBGA-256 - different | FBGA-100 (11x11 mm) - same |
| Logic Elements | 570 | 570 | 570 | 570 | 1270 | 570 | 240 |
| Macrocells | 440 | 440 | 440 | 440 | 980 | 440 | 192 |
| User I/Os | 76 | 76 | 76 | 76 | 76 | 160 | 80 |
| tPD (ns) | 5.4 ns | 5.4 ns | 7.0 ns (slower) | 5.4 ns | 6.0 ns | 5.4 ns | 4.5 ns |
| Operating Temperature | -40C to +125C | 0C to +85C (commercial) | 0C to +85C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C |
| RoHS Compliance | Yes (lead-free) | No (contains Pb) | No (contains Pb) | No (contains Pb) | Yes (lead-free) | No (contains Pb) | Yes (lead-free) |
| Unit Price (qty 1, USD) | 18.97 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Higher logic capacity in the same footprint (vs EPM240GF100C5N)
- RoHS-compliant lead-free packaging (vs EPM570F100C5N)
- Industrial temperature range (vs EPM570F100C4N)
Design Notes
The EPM570GF100C5N requires two distinct supply rails: VCCINT for the internal core (1.8 V typical) and VCCIO1/VCCIO2/VCCIO3/VCCIO4 for each I/O bank (1.8/2.5/3.3 V). Decouple each VCCIO bank with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and add a bulk 10 uF tantalum or ceramic capacitor near the supply pins. Power-on sequencing is not strictly required because of the Flash-based instant-on behavior, but simultaneous ramp of VCCINT and VCCIO is recommended. Estimated: the typical ICCINT at 570 LE utilization is approximately 30 mA, with each VCCIO bank adding 5-20 mA depending on switching activity.
The 100-ball FBGA package uses a 1.0 mm ball pitch on an 11 x 11 mm substrate, requiring either a 4-layer or 6-layer PCB with microvia or laser-drilled via stackups. Use a non-solder-mask-defined (NSMD) land pad with a 0.45 mm diameter for reliable assembly. Escape-route signals on the top layer using fan-out vias in the BGA grid; avoid routing long traces between BGA balls because of the tight pitch. Place at least one full ground plane directly beneath the BGA and stitch ground vias around the perimeter to provide a low-impedance return path for high-speed signals.
Do not exceed the absolute maximum VCCIO of 4.6 V or the 5.0 V tolerant input voltage limit on any user I/O pin. When interfacing to a 5 V bus, configure the I/O standard as 3.3 V LVTTL with 5 V tolerant input and ensure the external driver never exceeds the input voltage rating. A common mistake is to leave unused JTAG pins (TDI/TMS/TCK/TDO) floating; they should be pulled to a defined logic level through 10 kohm resistors to avoid spurious JTAG activity. Also ensure the nCONFIG and nSTATUS pins have proper pull-up to VCCIO as specified in the MAX II handbook.
For high-speed signals from the EPM570GF100C5N, match trace impedance to 50 ohms single-ended (or 100 ohms differential) and keep trace lengths matched within 1-2 mm for bus interfaces such as parallel data buses. Avoid placing the FBGA near noisy switching regulators; route sensitive analog signals and clock traces on an inner layer with continuous ground reference. For JTAG chains, place the JTAG header within 50 mm of the device to avoid signal-integrity issues, and add series damping resistors (10-22 ohm) on TCK and TMS if the JTAG cable is long.
Compliance Information
RoHS compliant per the 'G' suffix in the part number (green/lead-free FBGA-100 package). Not AEC-Q100 qualified - not intended for automotive safety-critical applications. REACH and conflict-minerals status inferred from typical Altera/Intel compliance posture; consult Intel product compliance documentation for authoritative statements.
