10AS032H3F35I2SG - Arria 10 SX SoC FPGA 320K LE | Intel/Altera
MPN: 10AS032H3F35I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2680 | $26,800.00 |
| 100 | $2480 | $248,000.00 |
| 500 | $2295 | $1,147,500.00 |
| 1,000 | $2120 | $2,120,000.00 |
Drop-in alternatives for 10AS032H3F35I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS032H3F35I2LG
✅ Drop-In✓ In Stock
$1590 / Unit
View Datasheet →10AS032H3F35E2SG
✅ Drop-In✓ In Stock
$2450 / Unit
View Datasheet →10AS032H3F35E2LG
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$3650 / Unit
View Datasheet →10AS032H3F34I2SG
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View Datasheet →10AS032H2F35I2SG
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View Datasheet →10AS032H3F35I2SG Maximum Ratings & Electrical Characteristics
| Product Type | SoC FPGA (System-on-Chip with ARM Cortex-A9 HPS) |
| Family | Arria 10 SX |
| Logic Elements | 320K |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Frequency | 1.5 GHz |
| Package | 1152-ball FCBGA, 35x35 mm |
| Mounting Type | Surface Mount (flip-chip BGA) |
| Operating Temperature Grade | Industrial (-40C to +100C) |
| Process Node | 20 nm TSMC |
| Transceivers | Up to 17.4 Gbps multi-gigabit transceivers |
| Memory Interfaces | DDR4/DDR3 hard memory controllers |
| DSP Blocks | Variable-precision DSP blocks |
| Embedded Memory | M20K blocks |
| RoHS Status | Compliant (per distributor listing) |
| Lead-Free | Yes (per distributor listing) |
| Minimum Supply Voltage | 0.87 V (core) |
10AS032H3F35I2SG 1152-ball fcbga, 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS032H3F35I2SG (1152-ball fcbga, 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS032H3F35I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H3F35I2SG is suitable for 6 applications: Wireless Baseband and Radio Unit Processing, Broadcast and Professional Video Processing, Medical Imaging Accelerator (CT/MRI/Ultrasound), Military and Aerospace Secure Communications, High-Performance Industrial Vision Systems, 5G and LTE Small-Cell Baseband.
Wireless Baseband and Radio Unit Processing
The 10AS032H3F35I2SG fits wireless baseband and radio-unit (RRU) designs because the Arria 10 SX integrates up to 17.4 Gbps transceivers that natively support CPRI, OBSAI, and JESD204B/C links to RF DACs/ADCs. With 320K logic elements, the FPGA fabric can host multi-carrier LTE/5G NR PHY layers, digital pre-distortion, and crest-factor reduction simultaneously. The 1.5 GHz dual-core ARM Cortex-A9 HPS handles L2/L3 stack, OAM, and timing synchronization, offloading the host processor. Total system BOM drops by eliminating an external CPU plus a separate FPGA. Reference companion parts include CPRI Framer/MII PHYs and JESD204B ADCs such as the AD9680.
Recommended
Broadcast and Professional Video Processing
The 10AS032H3F35I2SG suits broadcast video processing because the 320K logic elements and variable-precision DSP blocks implement multi-channel HEVC/H.264 encoding, de-interlacing, color-space conversion, and on-screen display at 4K60 and 8K resolutions. The dual 1.5 GHz ARM Cortex-A9 cores run a Linux media stack for file I/O, network protocols, and overlay graphics. Multi-gigabit transceivers at 17.4 Gbps support 12G-SDI, DisplayPort 1.4, and HDMI 2.0b aggregation. The 1152-ball FCBGA gives the I/O density needed for four simultaneous 12G-SDI streams plus PCIe Gen3 host connectivity. Reference companion parts include 12G-SDI cable equalizers and HDMI retimers.
Recommended
Medical Imaging Accelerator (CT/MRI/Ultrasound)
The 10AS032H3F35I2SG fits medical imaging accelerators because the Arria 10 SX fabric can run back-projection, beam-forming, and image-reconstruction pipelines with deterministic latency while the HPS executes the user interface, DICOM stack, and database I/O. The variable-precision DSP blocks accelerate floating-point FFT and convolution kernels at lower power than discrete DSPs. PCIe Gen3 transceivers link directly to host workstation CPUs, and the dual ARM cores manage patient-data security policies. The industrial temperature grade (-40C to +100C) supports cart-side and operating-room deployments. Reference companion parts include JESD204B ADCs and high-speed DDR4 memory.
Recommended
Military and Aerospace Secure Communications
The 10AS032H3F35I2SG serves military and aerospace secure-communication platforms because the Arria 10 SX architecture supports AES/SHA acceleration in the FPGA fabric plus the dual ARM Cortex-A9 HPS for software crypto and key management. Up to 17.4 Gbps transceivers support high-speed links to RF front-ends, optical networks, and serial RapidIO backplanes. The industrial temperature grade and flip-chip BGA package provide the ruggedization margin needed for airborne and ground-mobile platforms. ECC on the HPS L2 cache and bitstream AES encryption protect classified data at rest and in transit. Reference companion parts include rad-tolerant transceivers and secure boot EEPROMs.
Recommended
High-Performance Industrial Vision Systems
The 10AS032H3F35I2SG fits high-performance industrial machine vision because the Arria 10 SX fabric can process multi-megapixel Camera Link, CoaXPress, and GigE Vision streams simultaneously while the HPS runs a real-time Linux controller for PLC integration, defect logging, and SCADA connectivity. Up to 17.4 Gbps transceivers host CoaXPress 2.0 and 10 GigE Vision links at full line rate. Variable-precision DSP blocks accelerate convolutional neural networks for inline defect detection at sub-frame latency. The industrial temperature grade and 1152-ball FCBGA give the durability required for factory-floor deployments. Reference companion parts include CoaXPress repeaters and PoE controllers.
Recommended
5G and LTE Small-Cell Baseband
The 10AS032H3F35I2SG supports 5G and LTE small-cell baseband designs because the Arria 10 SX delivers 320K logic elements of PHY-layer acceleration alongside the dual ARM Cortex-A9 HPS running L2/L3 protocol stack. The integrated multi-gigabit transceivers provide CPRI and eCPRI connectivity to radio units while PCIe Gen3 interfaces to host fronthaul accelerators. Hardened DDR4 controllers handle high-bandwidth memory access with low latency. Industrial temperature grade and the rugged FCBGA package support outdoor small-cell enclosures. Reference companion parts include fronthaul SFP+ modules and PoE power controllers.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H3F35I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H3F35I2LG | 10AS032H3F35E2SG | 10AS032H3F35E2LG | 10AS032H3F34I2SG | 10AS032H2F35I2SG |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1152-ball FCBGA 35x35 mm (F35) | 1152-ball FCBGA 35x35 mm (F35) - same | 1152-ball FCBGA 35x35 mm (F35) - same | 1152-ball FCBGA 35x35 mm (F35) - same | 1152-ball FCBGA 34x34 mm (F34) - different PCB land pattern | 1152-ball FCBGA 35x35 mm (F35) - same |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 320K | 320K | 320K | 320K | 320K | 320K |
| HPS Configuration | H3 (higher HPS performance) | H3 | H3 | H3 | H3 | H2 (lower HPS performance) |
| HPS Core | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 @ 1.5 GHz | Dual ARM Cortex-A9 (lower HPS perf) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Commercial (E suffix) | Commercial (E suffix) | Industrial | Industrial |
| Transceiver Speed | Up to 17.4 Gbps | Up to 17.4 Gbps | Up to 17.4 Gbps | Up to 17.4 Gbps | Up to 17.4 Gbps | Up to 17.4 Gbps |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- 320K LE Arria 10 SX with dual 1.5 GHz ARM Cortex-A9 HPS in industrial grade (vs 10AS032H2F35I2SG)
- Larger 35x35 mm FCBGA substrate (F35) provides maximum I/O count and highest transceiver count (vs 10AS032H3F34I2SG)
- Industrial temperature grade (-40C to +100C) supports outdoor, factory-floor, and airborne deployments (vs 10AS032H3F35E2SG)
Design Notes
The 1152-ball FCBGA 35x35 mm package requires a high-density PCB with at least 8-12 routing layers, microvia/stacked-via technology, and 0.4 mm or finer pitch escape routing. Transceiver and DDR4 channels must be length-matched within 25-50 mils to satisfy setup/hold budgets; use the Arria 10 SX pinout files and Quartus Prime pin planner before finalizing stack-up. Place decoupling capacitors as close to each power ball as possible to manage the 20-40 W envelope.
Estimated: at full transceiver activity and 25C ambient, the 10AS032H3F35I2SG typically dissipates 20-40 W; junction-to-ambient thermal resistance depends on the PCB design and heatsink. Use a thermal pad or heatsink with sufficient airflow (>=200 LFM) and verify with a thermal simulation. The flip-chip BGA package has a center thermal pad that should be soldered to the PCB thermal vias for best heat extraction.
Do not select a non-SoC Arria 10 GX/GT variant when HPS is required - there is no migration path that adds the ARM subsystem back. Verify the exact ordering part-number suffix (I vs E temperature grade, G vs L speed grade, H2 vs H3 HPS performance, F34 vs F35 substrate) before generating PCB layout, because each combination has a different pinout. Also reserve configuration flash and HPS boot flash on the schematic before board spin, as the Arria 10 SX requires both for production operation.
Compliance Information
RoHS and lead-free status confirmed by DigiKey distributor listing as of 2026-09-05. Halogen-free status not explicitly stated in distributor data; consult Intel product declaration documents. AEC-Q100 not applicable for FPGA. REACH compliance assumed from Intel standard product compliance policy.
