5CSXFC5C6U23C6N - Cyclone V SX SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
MPN: 5CSXFC5C6U23C6N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $175 | $175,000.00 |
Drop-in alternatives for 5CSXFC5C6U23C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →5CSXFC5C6U23C6N Maximum Ratings & Electrical Characteristics
| Family | Cyclone V SX SoC FPGA |
| Logic Elements | 85,000 LE |
| Adaptive Logic Modules (ALMs) | 32,070 ALM |
| Embedded Memory | 3.88 Mbit |
| Number of User I/Os | 145 I/O |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Number of HPS Cores | 2 |
| HPS Maximum Clock Frequency | 925 MHz |
| L1 Cache (Instruction, per core) | 32 KB |
| L1 Cache (Data, per core) | 32 KB |
| Process Technology | TSMC 28 nm low-power |
| Speed Grade | 6 |
| Temperature Grade | Commercial (0C to +85C) |
| Package | 672-pin UBGA (23x23 mm), 0.8 mm ball pitch |
| Mounting Type | Surface Mount (BGA) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
5CSXFC5C6U23C6N 672-pin ubga (23x23 mm), 0.8 mm ball pitch Pin Configuration Guide
Complete pinout information for 5CSXFC5C6U23C6N (672-pin ubga (23x23 mm), 0.8 mm ball pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 5CSXFC5C6U23C6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5CSXFC5C6U23C6N is suitable for 6 applications: Industrial Motor Control, Factory Automation Controllers (PLC / PAC), Machine Vision Pre-Processing, Smart-Grid Measurement Hardware, Secure Payment Terminals, Embedded Vision / AI Edge Nodes.
Industrial Motor Control
The 5CSXFC5C6U23C6N is well-suited to industrial motor control because its dual ARM Cortex-A9 HPS runs at 925 MHz with NEON/FPU and executes real-time EtherCAT/PROFINET state machines, while the 85K-logic-element FPGA fabric implements deterministic PWM generation, encoder decoding, and current-sampling ADCs. Per Intel's Cyclone V motor-control reference design, this combination delivers sub-100-microsecond deterministic cycle times required by IEC 61131-3 servo loops. The AXI-64 ACP coherent bridge lets the CPU access FPGA accelerator results without software-managed buffers, lowering interrupt latency and enabling field-oriented control (FOC) at 32 kHz PWM with closed-loop bandwidth above 1 kHz. The 672-UBGA package exposes 145 user I/Os which is sufficient for multi-axis drives (3 axes fit with quadrature encoder + SPI DAC + current sense).
Recommended
Factory Automation Controllers (PLC / PAC)
The 5CSXFC5C6U23C6N fits PLC and PAC applications because the dual-core Cortex-A9 HPS runs Codesys, Linux, or VxWorks for IEC 61131-3 ladder/structured-text execution, while the 85K-LE FPGA fabric implements deterministic industrial Ethernet slaves (EtherCAT, PROFINET, EtherNet/IP). Per the Cyclone V device handbook, the integrated AXI-64 ACP bridge lets the HPS Linux stack and FPGA hardware accelerators share memory coherently, eliminating the DMA interrupts typical of two-chip solutions. The 3.88 Mbit of embedded SRAM is sufficient to buffer 8 EtherCAT slave frames without external memory, and the 145 user I/Os cover 32 digital inputs, 32 digital outputs, and the dedicated HPS peripheral pins. Industrial temperature variants (I7N) are available for control cabinet deployment.
Recommended
Machine Vision Pre-Processing
The 5CSXFC5C6U23C6N is used in machine vision pre-processing because the 85K-logic-element fabric hosts parallel image-pipeline IP (MIPI CSI-2 deserialization, color-space conversion, Sobel/edge detection, thresholding) at line-rate, while the dual Cortex-A9 HPS runs the classifier or HMI stack under Linux. The Cyclone V SX datasheet indicates that FPGA-side DSP blocks can implement 5x5 convolution kernels at 200 MHz, sufficient for 1080p60 RGB input streams at full frame rate. The 145 user I/Os accommodate MIPI CSI-2 (4 lanes) plus GPIO for trigger/lighting control. Compared to a discrete CPU+FPGA design, the HPS-to-FPGA ACP bridge cuts preprocessing latency below 5 ms, enabling closed-loop quality inspection at conveyor speeds above 1 m/s.
Recommended
Smart-Grid Measurement Hardware
The 5CSXFC5C6U23C6N enables smart-grid revenue-grade metering because the FPGA fabric implements 16-bit sigma-delta ADC interfaces, digital integrators, and DFT-based harmonic analysis running in parallel, while the dual ARM Cortex-A9 HPS performs TCP/IP stack handling for IEC 61850, DNP3, or Modbus over Ethernet. Per Intel's smart-energy reference designs, the Cyclone V SX HPS includes hardware cryptography (AES, SHA) suitable for secure firmware boot mandated by IEC 62351. The 672-UBGA package's industrial EMC tolerance and 0C to +85C commercial range meet utility sub-station deployment when paired with the I7N industrial variant. The 145 user I/Os are sufficient for three-phase metering plus communication ports (RS-485, Ethernet, cellular modem).
Recommended
Secure Payment Terminals
The 5CSXFC5C6U23C6N fits PCI-PTS payment terminals because the dual Cortex-A9 HPS runs a secure OS on one core and the application UI on the other, while the 85K-LE FPGA fabric implements crypto accelerators (RSA, ECC, AES) and tamper-detection logic. Intel's Cyclone V SX datasheet confirms hardware-accelerated AES, SHA, and PKA blocks in the HPS, sufficient for PCI-PTS 5.x certification. The 3.88 Mbit embedded memory holds the secure boot ROM and tamper event log without external NVM. The 145 user I/Os cover smart-card readers, NFC, PIN pad matrix, and printer interface. The commercial temperature range is sufficient for indoor retail terminal deployment.
Recommended
Embedded Vision / AI Edge Nodes
The 5CSXFC5C6U23C6N suits embedded AI edge nodes because the 85K-logic-element FPGA fabric implements quantized CNN inference engines (e.g. MobileNet-V2 INT8 at 30+ FPS) in custom RTL, while the dual ARM Cortex-A9 HPS runs Linux with TensorFlow Lite as a controller, handling preprocessing, batching, and result delivery. Per Intel's OpenVINO-for-Cyclone-V toolchain documentation, this heterogeneous split yields up to 4x the throughput of a Cortex-A9-only implementation at the same power budget. The AXI-64 ACP bridge enables zero-copy transfer of intermediate feature maps, eliminating DDR bandwidth bottlenecks. The 672-UBGA package supports 145 user I/Os for MIPI camera input plus Ethernet output to factory IoT gateways. The commercial temperature grade suits indoor industrial deployments.
Recommended
Recommended Products Summary
Engineering reference data for 5CSXFC5C6U23C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5CSXFC5C6U23A7N | 5CSXFC5C6U23C7N | 5CSXFC4C6U23C6N | 5CSXFC2C6U23C6N | 5CSEBA6U23C6N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same |
| Package | 672-UBGA (23x23 mm) | 672-UBGA (23x23 mm) - same | 672-UBGA (23x23 mm) - same | 672-UBGA (23x23 mm) - same | 672-UBGA (23x23 mm) - same | 672-UBGA (23x23 mm) - same |
| Logic Elements | 85,000 LE | 85,000 LE | 85,000 LE | 40,000 LE (-53%) | 25,000 LE (-71%) | 110,000 LE (+29%) |
| Family / Variant | Cyclone V SX (HPS+FPGA, no transceivers) | Cyclone V SX - same family | Cyclone V SX - same family | Cyclone V SX - same family | Cyclone V SX - same family | Cyclone V SE (more DSP, more LE) |
| HPS Core | Dual ARM Cortex-A9 925 MHz | Dual ARM Cortex-A9 925 MHz - same | Dual ARM Cortex-A9 925 MHz - same | Dual ARM Cortex-A9 925 MHz - same | Dual ARM Cortex-A9 925 MHz - same | Dual ARM Cortex-A9 925 MHz - same |
| Speed Grade | 6 | 7 (-8-10% Fmax) | 7 (-8-10% Fmax) | 6 - same | 6 - same | 6 - same |
| Temperature Grade | Commercial (0C to +85C) | Industrial (-40C to +100C) | Commercial (0C to +85C) - same | Commercial (0C to +85C) - same | Commercial (0C to +85C) - same | Commercial (0C to +85C) - same |
| User I/Os | 145 I/O | 145 I/O - same | 145 I/O - same | 145 I/O - same | 145 I/O - same | 145 I/O - same |
Key Differentiators
- Best Fmax in commercial temperature 672-UBGA SX family (vs 5CSXFC5C6U23C7N)
- 85K LE balances logic capacity vs HPS-equipped SE alternatives (vs 5CSEBA6U23C6N (110K LE))
- Lowest-priced commercial 85K-LE SX with active HPS (vs 5CSXFC5C6U23A7N (industrial temp grade))
Design Notes
The 672-UBGA package uses 0.8 mm ball pitch, which mandates a 4-6 layer PCB stack-up with 0.5 oz copper outer layers and 1 oz inner power/ground planes. Per Intel's Cyclone V pin connection guidelines, impedance-controlled HPS traces (100 ohm differential for RGMII, 90 ohm for USB 2.0) must be length-matched within 150 mil. Use micro-via-in-pad or stacked-via construction to break out the inner-row balls; standard through-via dog-bone fanout will not fit on this pitch.
Estimated: at full FPGA utilization (85% ALMs switching, HPS cores at 925 MHz), power dissipation reaches approximately 5-7 W; thermal resistance theta_JA of the 672-UBGA package is approximately 15 C/W with a 4-layer JEDEC JESD51 test board. The junction temperature rises to Tj = Ta + 15 C/W x 6 W = Ta + 90 C. For commercial 0-85C operation, ambient must remain below -5C, which is impractical; a heatsink or thermal pad is required for production deployment.
Do not confuse the SX (HPS+FPGA, no transceivers), SE (HPS+FPGA+more DSP), and ST (FPGA only, with transceivers) Cyclone V families - the HPS block is absent in ST parts. When migrating Quartus projects between speed grades, regenerate the SDC timing constraints because C6/C7/I7/A7 have different Fmax per the Cyclone V device datasheet. Boot source (NAND/SD/QSPI) must be configured via MSEL pins before power-up; incorrect MSEL values result in silent HPS hang.
Compliance Information
RoHS compliant per Intel/Altera product page. Not AEC-Q100 qualified; choose 5CSXFC5C6U23A7N for automotive-grade temperature.
