5CSEBA5U23C6N - Cyclone V SE SoC FPGA 85K LE | Altera / Intel
MPN: 5CSEBA5U23C6N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $203.88 | $203.88 |
| 10 | $183.49 | $1,834.90 |
| 100 | $163.1 | $16,310.00 |
| 500 | $142.72 | $71,360.00 |
| 1,000 | $122.33 | $122,330.00 |
Drop-in alternatives for 5CSEBA5U23C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5CSEBA5U23A7N
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View Datasheet β5CSEBA5U23C6N Maximum Ratings & Electrical Characteristics
| Family | Cyclone V SE SoC FPGA |
| Process Technology | 28 nm low-power |
| Logic Elements | 85 K |
| HPS Cores | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 925 MHz |
| User I/O Pins | 145 |
| Package | 672-UBGA (23x23 mm) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0C to +85C (commercial) |
| Speed Grade | -6 |
| Supply Voltage (Core) | 1.1 V |
| Embedded Memory | 4,446 Kbits |
| Embedded Multipliers | 156 (18x18) |
| Memory Controllers | 2 (hard DDR2/DDR3/LPDDR2) |
| RoHS Status | Compliant |
| MSL Level | 3 (168 hours) |
5CSEBA5U23C6N Pin Configuration
| Pin A1 | VCC β Core supply voltage (1.1 V) |
| Pin A2 | GPIO β User I/O pin, bank 3A |
| Pin A3 | GPIO β User I/O pin, bank 3A |
| Pin B1 | VCCIO3A β I/O supply, bank 3A |
| Pin B2 | GPIO β User I/O pin, bank 3A |
| Pin B3 | GPIO β User I/O pin, bank 3A |
| Pin C1 | GND β Ground |
| Pin C2 | GPIO β User I/O pin, bank 3B |
| Pin C3 | GPIO β User I/O pin, bank 3B |
| Pin D1 | VCCIO3B β I/O supply, bank 3B |
| Pin D2 | GPIO β User I/O pin, bank 3B |
| Pin D3 | GPIO β User I/O pin, bank 4A |
| Pin E1 | GND β Ground |
| Pin E2 | VCCIO4A β I/O supply, bank 4A |
| Pin E3 | GPIO β User I/O pin, bank 4A |
| Pin F1 | GPIO β User I/O pin, bank 4B |
| Pin F2 | GPIO β User I/O pin, bank 4B |
| Pin F3 | VCCIO4B β I/O supply, bank 4B |
| Pin G1 | GND β Ground |
| Pin G2 | GPIO β User I/O pin, bank 5A |
| Pin G3 | GPIO β User I/O pin, bank 5A |
| Pin H1 | VCCIO5A β I/O supply, bank 5A |
| Pin H2 | GPIO β User I/O pin, bank 5A |
| Pin H3 | GPIO β User I/O pin, bank 5B |
| Pin J1 | GND β Ground |
| Pin J2 | VCCIO5B β I/O supply, bank 5B |
| Pin J3 | GPIO β User I/O pin, bank 5B |
| Pin K1 | GPIO β User I/O pin, bank 6A |
| Pin K2 | GPIO β User I/O pin, bank 6A |
| Pin K3 | VCCIO6A β I/O supply, bank 6A |
| Pin L1 | GND β Ground |
| Pin L2 | GPIO β User I/O pin, bank 6B |
| Pin L3 | GPIO β User I/O pin, bank 6B |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5CSEBA5U23C6N is suitable for 7 applications: Industrial Motor Control, Machine Vision Systems, Embedded HMI and Panel PCs, Factory Automation Controllers, Software-Defined Radio Front-Ends, Portable Medical Imaging, Broadcast Video Processing.
Industrial Motor Control
The 5CSEBA5U23C6N is well suited to multi-axis servo and stepper motor control where deterministic real-time loops must run alongside communication stacks. The 85K LE fabric can host 4 to 8 PWM generation cores with field-oriented control state machines at 100 kHz loop rates, while the dual 925 MHz Cortex-A9 HPS runs Linux/RTOS for trajectory planning and EtherCAT/CAN-FD master stacks. Hard DDR3 controller on the HPS sustains large lookup-table buffering for sinusoidal commutation profiles.
Recommended
Machine Vision Systems
The 5CSEBA5U23C6N's 85K LE fabric can implement hardware-accelerated image processing pipelines (Sobel, Gaussian, threshold) at GigE Vision or USB3 Vision frame rates, while the Cortex-A9 HPS handles TCP/IP streaming, GigE Vision control protocol, and host-side metadata extraction. The 145 user I/O pins accept multiple MIPI-CSI-2 or LVDS camera lanes through soft deserializer IPs, and the 4,446 Kbit embedded memory buffers line-scan data between processing stages.
Recommended
Embedded HMI and Panel PCs
HMI applications benefit from the 5CSEBA5U23C6N's combination of a Linux-capable Cortex-A9 HPS for Qt/Web GUI rendering and FPGA fabric for deterministic touch-screen latency, multi-protocol industrial fieldbus bridging (PROFINET, EtherNet/IP), and encoder input conditioning. The HPS subsystem drives LVDS or RGB interfaces to 7 to 15 inch panels at 60 fps, while the FPGA fabric implements the HMI reactivity loop. Hard PCIe Gen2 endpoint enables expansion to gigabit Ethernet or Wi-Fi modules.
Recommended
Factory Automation Controllers
The 5CSEBA5U23C6N serves as a programmable logic controller (PLC) and edge gateway, with the HPS running containerized automation software (CODESYS, Node-RED) and the FPGA implementing IEC 61131-3 soft-CPU cores, fast digital I/O debouncing, and protocol translation. Industrial temperature variants in the same package enable cabinet-mounted deployment. The 145 user I/O count supports dozens of digital inputs and outputs per controller card without external I/O expanders.
Recommended
Software-Defined Radio Front-Ends
In SDR applications the 5CSEBA5U23C6N's FPGA fabric implements DDC/DUC chains, FFT engines, and channelizer logic for narrowband and wideband receivers, while the Cortex-A9 HPS runs GNU Radio or custom DSP stacks for demodulation and protocol decode. Hard memory controllers sustain high-bandwidth ADC capture buffers, and 145 user I/O pins accept JESD204B or LVDS data from RF ADCs. The 925 MHz HPS frequency is sufficient for protocol and demodulation processing in real time.
Recommended
Portable Medical Imaging
Portable ultrasound and endoscopy systems use the 5CSEBA5U23C6N to combine FPGA-based beamforming and image preprocessing with ARM Cortex-A9-based system control, patient data logging, and DICOM stack management. Low-power 28 nm process technology supports battery-powered operation, and the HPS hard DDR3 controller enables large cine-loop buffering. Same-package industrial-temperature variants support ambulance and field-hospital deployments.
Recommended
Broadcast Video Processing
The 5CSEBA5U23C6N FPGA fabric implements SDI de-embedders, color-space converters, frame-rate conversion, and HDR tone-mapping for broadcast video pipelines up to 12G-SDI data rates, while the Cortex-A9 HPS handles ancillary data extraction, closed-caption processing, and IP-network management. The 672-UBGA package provides sufficient I/O for quad-link 3G-SDI or dual-link 12G-SDI ingest with downstream routing. Hard PCIe enables ingest cards in server-based broadcast infrastructure.
Recommended
Recommended Products Summary
Engineering reference data for 5CSEBA5U23C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5CSEBA5U23A7N | 5CSEBA5U23I7N | 5CSEBA5U23C7N | 5CSEBA5U23C8N | 5CSEBA5U23I7SN | 5CSEBA5U23I7LN |
|---|---|---|---|---|---|---|---|
| Package | 672-UBGA (23x23) | 672-UBGA (23x23) - same | 672-UBGA (23x23) - same | 672-UBGA (23x23) - same | 672-UBGA (23x23) - same | 672-UBGA (23x23) - same | 672-UBGA (23x23) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 85 K | 85 K (same die) | 85 K (same die) | 85 K (same die) | 85 K (same die) | 85 K (same die) | 85 K (same die) |
| Speed Grade | -6 | -7 (faster) | -7 (faster) | -7 (faster) | -8 (slower, lower power) | -7 (faster) | -7 (faster) |
| Temperature Grade | Commercial 0C to +85C | Commercial 0C to +85C | Industrial -40C to +100C | Commercial 0C to +85C | Commercial 0C to +85C | Industrial -40C to +100C | Industrial -40C to +100C |
| HPS Cores | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz | Dual Cortex-A9 925 MHz |
| User I/O | 145 | 145 | 145 | 145 | 145 | 145 | 145 |
| Embedded Memory | 4,446 Kbits | 4,446 Kbits | 4,446 Kbits | 4,446 Kbits | 4,446 Kbits | 4,446 Kbits | 4,446 Kbits |
| Unit Price (qty-1, USD) | 203.88 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Balanced mid-density LE count with full HPS feature set (vs 5CSEBA4U23C6N (4U is 40K LE variant))
- Mid-tier speed grade balances Fmax and dynamic power (vs 5CSEBA5U23C8N (-8 grade, lowest speed bin))
- Commercial temperature grade for cost-sensitive non-automotive use (vs 5CSEBA5U23I7N (-7 industrial temperature grade))
Design Notes
The Cyclone V SE SoC FPGA requires four distinct power rails: VCC (1.1 V core), VCCPGM (1.1-1.5 V configuration), VCCIO_x (per-bank I/O at 1.2/1.5/1.8/2.5/3.3 V), and VCCPD (3.3 V pre-driver). Sequencing must enforce HPS power-up before fabric I/O activation; failure to sequence causes latch-up in the HPS-to-FPGA bridges. Use the Cyclone V Power Management User Guide and dedicated EN5367QI or LTC3619 sequencers. Decoupling: 0402 100 nF X7R per VCC/VCCIO pin pair plus 22 uF 0805 bulk on each rail, placed within 5 mm of BGA balls.
At typical SoC workloads (HPS 60% utilization, FPGA 70% utilization), expect 3-5 W dissipation in the 672-UBGA package. The Cyclone V device datasheet specifies theta_JA of approximately 11 C/W with a 4-layer JEDEC JESD51 test PCB; the 23x23 mm body with 1.0 mm ball pitch requires a 6-layer PCB with continuous ground plane under the BGA for adequate spreading. Industrial deployments must derate junction temperature to <100C; the -6 speed grade commercial variant specifies 0C-85C ambient with 100C max junction.
The 672-UBGA at 1.0 mm pitch requires PCB design rules of 0.4 mm pad, 0.2 mm trace/space, and microvia-in-pad (stacked via) construction for reliable BGA assembly. Escape routing on the top layer must use 0.1 mm/0.1 mm line/space with 4-5 routing tracks between adjacent balls. Use Intel's Cyclone V SE SoC development kit reference layout (DK-DEV-5CSEBA6N) as the golden reference. Match all DDR3 traces to 50 ohm single-ended with length matching within +/-25 mil across the byte group.
Three recurring pitfalls in 5CSEBA5U23C6N designs: (1) MSEL pin setting must be pulled high/low through 4.7 kohm resistors to select boot source - floating MSEL pins cause boot ROM to enter a non-deterministic state; (2) the HPS reset line (HPS_nRST) must be driven by an external supervisor, not the FPGA fabric, to ensure correct boot sequencing; (3) configuration pins (nCONFIG, nSTATUS, CONF_DONE) need 10 kohm pull-ups to VCCPD. Per the Cyclone V handbook configuration chapter, omitting these resistors causes intermittent boot failures in production.
Compliance Information
RoHS compliant per Intel Cyclone V device datasheet material declaration. Not AEC-Q100 qualified (industrial grade only - automotive variants are Cyclone V Auto family with different part numbers). Lead-free BGA balls, halogen-free per IEC 61249-2-21.
